From patchwork Tue Feb 20 16:06:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564213 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E5A5C54788 for ; Tue, 20 Feb 2024 16:08:09 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdb-00026U-Nd; Tue, 20 Feb 2024 11:06:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdZ-00022r-59 for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:29 -0500 Received: from mail-lj1-x233.google.com ([2a00:1450:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSdX-0005Di-47 for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:28 -0500 Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2d23a22233fso27535541fa.2 for ; Tue, 20 Feb 2024 08:06:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445185; x=1709049985; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9wiR3lcsTzDl1fZCKpUeESX9s4fyTRWelZyXZYZsdUc=; b=hCqcg+VhEj9bNSzHXRngiEI+kzjuYP/r/h2eMFzxLSJ2nPiKhgRbKCgopu4c3NVAuG eHc9vShHcYqfdOVYRAK5g06gorKzzlFQJYoPoxI4Ze0rYYeFr+5030dDm4SmPaF6zuPO 5deQOvW+YuV+cvRsZzFyfsSqS3/+N2DUggIEC/hqiRSR9Upjh6HMbN/U066Gh+7xOnXD EDJRMAfoe4NgCgbLhwLVNdnKhButVsri2YPJLScr3t/l7OfP1jUI//ahbsoiGDhoEVzo 9DKLMySDZqPUik7Ezt8lxIxsN0BbcKcoQIlh2bUh67YDxa9NmwveEiSdDJALOiL0zieQ lF0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445185; x=1709049985; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9wiR3lcsTzDl1fZCKpUeESX9s4fyTRWelZyXZYZsdUc=; b=e4pDCqJvFGyaXeQKC/owEwjdImHEASsfzJncb6wX/x5WwV8lXOgRG9RcUG6dJ9pcpP aYAZv+kLOOerktTr2/6VRhiME8ODX8kvFG+ig+bnOcw0IPT1ha40EStWhyz4EfBd8EF9 vuD06qcBZm3iz/zTi2NJGw3ddJP4eB4lnIGNcEpAGV/EFVPW1nfl6OXNL03r0ped1ZaN xAbb2hYTAajf7TYTU9IgHdfIwz8xYB0nGGOZCuNjUBI5lgyIzn1Ar6PUW/TS5OeqeHY8 SyMbKop36B7uOOjT4AUSWtUGmbhcw74EzAqMTPbeSRNk0/ubYu2UqU/XESwjbUq9qsG6 Q8lQ== X-Gm-Message-State: AOJu0Yy79KlcIrI8d+iiBJONyPLLlsY5DKbr5LrSGA6XiC+EKKKil4K6 edZvwsanMd5N0LY30aFGE1zg/5Bi7uz6FJTGRCwS5uj1PteWebHmXdc4iEXOt3W6XMhCVtiUR/e + X-Google-Smtp-Source: AGHT+IEamTj4KBKl/bX2+Tk1qjNpSTaAcx2EquDav82UUZz/ymddyRrGhPGy5TNCZXL/ra7HBU2M0A== X-Received: by 2002:a2e:920a:0:b0:2d2:2888:17eb with SMTP id k10-20020a2e920a000000b002d2288817ebmr7101957ljg.6.1708445185181; Tue, 20 Feb 2024 08:06:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 01/10] hw/i386: Store pointers to IDE buses in PCMachineState Date: Tue, 20 Feb 2024 16:06:13 +0000 Message-Id: <20240220160622.114437-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::233; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the two IDE bus BusState pointers to the set we keep in PCMachineState. This allows us to avoid passing them to pc_cmos_init(), and also will allow a refactoring of how we call pc_cmos_init_late(). Signed-off-by: Peter Maydell Acked-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu --- include/hw/i386/pc.h | 4 +++- hw/i386/pc.c | 5 ++--- hw/i386/pc_piix.c | 16 +++++++--------- hw/i386/pc_q35.c | 9 ++++----- 4 files changed, 16 insertions(+), 18 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ec0e5efcb28..8f8ac894b10 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -17,6 +17,8 @@ #define HPET_INTCAP "hpet-intcap" +#define MAX_IDE_BUS 2 + /** * PCMachineState: * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling @@ -37,6 +39,7 @@ typedef struct PCMachineState { PFlashCFI01 *flash[2]; ISADevice *pcspk; DeviceState *iommu; + BusState *idebus[MAX_IDE_BUS]; /* Configuration options: */ uint64_t max_ram_below_4g; @@ -182,7 +185,6 @@ void pc_basic_device_init(struct PCMachineState *pcms, bool create_fdctrl, uint32_t hpet_irqs); void pc_cmos_init(PCMachineState *pcms, - BusState *ide0, BusState *ide1, ISADevice *s); void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 196827531a5..8b0f54e284c 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -574,7 +574,6 @@ static void pc_cmos_init_late(void *opaque) } void pc_cmos_init(PCMachineState *pcms, - BusState *idebus0, BusState *idebus1, ISADevice *rtc) { int val; @@ -634,8 +633,8 @@ void pc_cmos_init(PCMachineState *pcms, /* hard drives and FDC */ arg.rtc_state = s; - arg.idebus[0] = idebus0; - arg.idebus[1] = idebus1; + arg.idebus[0] = pcms->idebus[0]; + arg.idebus[1] = pcms->idebus[1]; qemu_register_reset(pc_cmos_init_late, &arg); } diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 999b7b806ca..8df88a6ccd1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -68,7 +68,6 @@ #include "kvm/kvm-cpu.h" #include "target/i386/cpu.h" -#define MAX_IDE_BUS 2 #define XEN_IOAPIC_NUM_PIRQS 128ULL #ifdef CONFIG_IDE_ISA @@ -114,7 +113,6 @@ static void pc_init1(MachineState *machine, Object *piix4_pm = NULL; qemu_irq smi_irq; GSIState *gsi_state; - BusState *idebus[MAX_IDE_BUS]; ISADevice *rtc_state; MemoryRegion *ram_memory; MemoryRegion *pci_memory = NULL; @@ -299,8 +297,8 @@ static void pc_init1(MachineState *machine, piix4_pm = object_resolve_path_component(OBJECT(pci_dev), "pm"); dev = DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); pci_ide_create_devs(PCI_DEVICE(dev)); - idebus[0] = qdev_get_child_bus(dev, "ide.0"); - idebus[1] = qdev_get_child_bus(dev, "ide.1"); + pcms->idebus[0] = qdev_get_child_bus(dev, "ide.0"); + pcms->idebus[1] = qdev_get_child_bus(dev, "ide.1"); } else { isa_bus = isa_bus_new(NULL, system_memory, system_io, &error_abort); @@ -312,8 +310,8 @@ static void pc_init1(MachineState *machine, i8257_dma_init(OBJECT(machine), isa_bus, 0); pcms->hpet_enabled = false; - idebus[0] = NULL; - idebus[1] = NULL; + pcms->idebus[0] = NULL; + pcms->idebus[1] = NULL; } if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { @@ -342,7 +340,7 @@ static void pc_init1(MachineState *machine, pc_nic_init(pcmc, isa_bus, pci_bus); if (pcmc->pci_enabled) { - pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); + pc_cmos_init(pcms, rtc_state); } #ifdef CONFIG_IDE_ISA else { @@ -361,9 +359,9 @@ static void pc_init1(MachineState *machine, * second one. */ busname[4] = '0' + i; - idebus[i] = qdev_get_child_bus(DEVICE(dev), busname); + pcms->idebus[i] = qdev_get_child_bus(DEVICE(dev), busname); } - pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); + pc_cmos_init(pcms, rtc_state); } #endif diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index d346fa3b1d6..71402c36eb2 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -126,7 +126,6 @@ static void pc_q35_init(MachineState *machine) PCIBus *host_bus; PCIDevice *lpc; DeviceState *lpc_dev; - BusState *idebus[MAX_SATA_PORTS]; ISADevice *rtc_state; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *system_io = get_system_io(); @@ -300,13 +299,13 @@ static void pc_q35_init(MachineState *machine) ICH9_SATA1_FUNC), "ich9-ahci"); ich9 = ICH9_AHCI(pdev); - idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); - idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); + pcms->idebus[0] = qdev_get_child_bus(DEVICE(pdev), "ide.0"); + pcms->idebus[1] = qdev_get_child_bus(DEVICE(pdev), "ide.1"); g_assert(MAX_SATA_PORTS == ich9->ahci.ports); ide_drive_get(hd, ich9->ahci.ports); ahci_ide_create_devs(&ich9->ahci, hd); } else { - idebus[0] = idebus[1] = NULL; + pcms->idebus[0] = pcms->idebus[1] = NULL; } if (machine_usb(machine)) { @@ -327,7 +326,7 @@ static void pc_q35_init(MachineState *machine) smbus_eeprom_init(pcms->smbus, 8, NULL, 0); } - pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state); + pc_cmos_init(pcms, rtc_state); /* the rest devices to which pci devfn is automatically assigned */ pc_vga_init(isa_bus, host_bus); From patchwork Tue Feb 20 16:06:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564215 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E610DC48BC3 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 02/10] hw/i386/pc: Do pc_cmos_init_late() from pc_machine_done() Date: Tue, 20 Feb 2024 16:06:14 +0000 Message-Id: <20240220160622.114437-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the i386 PC machine, we want to run the pc_cmos_init_late() function only once the IDE and floppy drive devices have been set up. We currently do this using qemu_register_reset(), and then have the function call qemu_unregister_reset() on itself, so it runs exactly once. This was an expedient way to do it back in 2010 when we first added this (in commit c0897e0cb94e8), but now we have a more obvious point to do "machine initialization that has to happen after generic device init": the machine-init-done hook. Do the pc_cmos_init_late() work from our existing PC machine init done hook function, so we can drop the use of qemu_register_reset() and qemu_unregister_reset(). Because the pointers to the devices we need (the IDE buses and the RTC) are now all in the machine state, we don't need the pc_cmos_init_late_arg struct and can just pass the PCMachineState pointer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu --- hw/i386/pc.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8b0f54e284c..4c3cfe9fc35 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -465,11 +465,6 @@ static void pc_cmos_init_floppy(MC146818RtcState *rtc_state, ISADevice *floppy) mc146818rtc_set_cmos_data(rtc_state, REG_EQUIPMENT_BYTE, val); } -typedef struct pc_cmos_init_late_arg { - MC146818RtcState *rtc_state; - BusState *idebus[2]; -} pc_cmos_init_late_arg; - typedef struct check_fdc_state { ISADevice *floppy; bool multiple; @@ -530,23 +525,25 @@ static ISADevice *pc_find_fdc0(void) return state.floppy; } -static void pc_cmos_init_late(void *opaque) +static void pc_cmos_init_late(PCMachineState *pcms) { - pc_cmos_init_late_arg *arg = opaque; - MC146818RtcState *s = arg->rtc_state; + X86MachineState *x86ms = X86_MACHINE(pcms); + MC146818RtcState *s = MC146818_RTC(x86ms->rtc); int16_t cylinders; int8_t heads, sectors; int val; int i, trans; val = 0; - if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 0, - &cylinders, &heads, §ors) >= 0) { + if (pcms->idebus[0] && + ide_get_geometry(pcms->idebus[0], 0, + &cylinders, &heads, §ors) >= 0) { cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors); val |= 0xf0; } - if (arg->idebus[0] && ide_get_geometry(arg->idebus[0], 1, - &cylinders, &heads, §ors) >= 0) { + if (pcms->idebus[0] && + ide_get_geometry(pcms->idebus[0], 1, + &cylinders, &heads, §ors) >= 0) { cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors); val |= 0x0f; } @@ -558,10 +555,11 @@ static void pc_cmos_init_late(void *opaque) geometry. It is always such that: 1 <= sects <= 63, 1 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS geometry can be different if a translation is done. */ - if (arg->idebus[i / 2] && - ide_get_geometry(arg->idebus[i / 2], i % 2, + BusState *idebus = pcms->idebus[i / 2]; + if (idebus && + ide_get_geometry(idebus, i % 2, &cylinders, &heads, §ors) >= 0) { - trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1; + trans = ide_get_bios_chs_trans(idebus, i % 2) - 1; assert((trans & ~3) == 0); val |= trans << (i * 2); } @@ -569,15 +567,12 @@ static void pc_cmos_init_late(void *opaque) mc146818rtc_set_cmos_data(s, 0x39, val); pc_cmos_init_floppy(s, pc_find_fdc0()); - - qemu_unregister_reset(pc_cmos_init_late, opaque); } void pc_cmos_init(PCMachineState *pcms, ISADevice *rtc) { int val; - static pc_cmos_init_late_arg arg; X86MachineState *x86ms = X86_MACHINE(pcms); MC146818RtcState *s = MC146818_RTC(rtc); @@ -631,11 +626,7 @@ void pc_cmos_init(PCMachineState *pcms, val |= 0x04; /* PS/2 mouse installed */ mc146818rtc_set_cmos_data(s, REG_EQUIPMENT_BYTE, val); - /* hard drives and FDC */ - arg.rtc_state = s; - arg.idebus[0] = pcms->idebus[0]; - arg.idebus[1] = pcms->idebus[1]; - qemu_register_reset(pc_cmos_init_late, &arg); + /* hard drives and FDC are handled by pc_cmos_init_late() */ } static void handle_a20_line_change(void *opaque, int irq, int level) @@ -703,6 +694,8 @@ void pc_machine_done(Notifier *notifier, void *data) /* update FW_CFG_NB_CPUS to account for -device added CPUs */ fw_cfg_modify_i16(x86ms->fw_cfg, FW_CFG_NB_CPUS, x86ms->boot_cpus); } + + pc_cmos_init_late(pcms); } void pc_guest_info_init(PCMachineState *pcms) From patchwork Tue Feb 20 16:06:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 838F4C5475B for ; Tue, 20 Feb 2024 16:07:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdc-00026n-IK; Tue, 20 Feb 2024 11:06:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdZ-00023G-Qh for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:29 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSdX-0005Er-Q5 for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:29 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-41272d92b8dso778065e9.1 for ; Tue, 20 Feb 2024 08:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445186; x=1709049986; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJNxNHiqA9T4HKtvdwd+S2EJnh6+yff9KeawpRzL/Bw=; b=oI7uj454n/km6OvPtvr90DbHlQ2SSeULVG46ZJayK4s2tAX9N1vFSF7HgFt87qId1q jHuGRNvIxqv5pbbUITDNm1WpmHAo3vBLSaW7hzji91bGn+JKOOJDmVd1E0eHJIAF2JTp Vi67ty5vvp7bFijenLF4WZ4lUuTOamx2Z5taWq12ShWtZKMoMlgkII2MD+tl0MycXL4j jPWyRWy8N/JbSgrQx/iUrpH1MXSkL+CCjwfggsDprVL5PknrFl8cJYIdhH5jYOSyVCeq TVy0vpAuyvC2xzFJK+v4uFtadT4kaPCK6WIMAT8JSDPhZ2N8nE89bNzSAHwXwLXLMtzf yh0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445186; x=1709049986; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJNxNHiqA9T4HKtvdwd+S2EJnh6+yff9KeawpRzL/Bw=; b=bzeOKFgcUIY/pvizF45MeTLVzChVzsg1qoI5/mi18JLl+vd6iSO/8LmY8yX7ekYgPb GTVzjno2+bg6fYqGwtkietiWqK1UPuVizKpdzY7wtKgoNDqif3t6+OBMJWcYSeBQhDhH g24DbAyH7CmG0rAWRB7QH0Iw2iSEle878y39ZByfiu6MjHNjmfvE7crMq2Uezw92pdro IXqAMUZI+/TxCuA81hMackiLcrixHoqr7LWMy39zQhDAGVMzyZCzDw2i38jIwAF6ZNu+ UATLIP2TxueExzSUsx3DM466xsJ8MN3OKckyP2UFdxoHR7VP3/i2j5UggrMzrrKDZipC 6jmw== X-Gm-Message-State: AOJu0YywDHyo2CHoefGPe5zgTBjHTbLJMUm09Xuot3B9NPcoZ/lz7zDB 7WAIhcVnw+iL5/Bo0MEQwA71T0cxNoNgLipwvNAvk9WHsKMQT8m8zcL4XZaV0+itbES+9Rkn5a3 K X-Google-Smtp-Source: AGHT+IFeU5PZxzVPy1Gh00CPjFD54ps6gsQeXY+rE7vJtnAWAZ4tVlTT1oPapjSX9s3xitdNZ7jM3g== X-Received: by 2002:a05:600c:3111:b0:412:71d2:9c17 with SMTP id g17-20020a05600c311100b0041271d29c17mr742858wmo.6.1708445186459; Tue, 20 Feb 2024 08:06:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 03/10] system/bootdevice: Don't unregister reset handler in restore_boot_order() Date: Tue, 20 Feb 2024 16:06:15 +0000 Message-Id: <20240220160622.114437-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently the qemu_register_reset() API permits the reset handler functions registered with it to remove themselves from within the callback function. This is fine with our current implementation, but is a bit odd, because generally reset is supposed to be idempotent, and doesn't fit well in a three-phase-reset world where a resettable object will get multiple callbacks as the system is reset. We now have only one user of qemu_register_reset() which makes use of the ability to unregister itself within the callback: restore_boot_order(). We want to change our implementation of qemu_register_reset() to something where it would be awkward to maintain the "can self-unregister" feature. Rather than making that reimplementation complicated, change restore_boot_order() so that it doesn't unregister itself but instead returns doing nothing for any calls after it has done the "restore the boot order" work. Signed-off-by: Peter Maydell Acked-by: Richard Henderson Reviewed-by: Zhao Liu --- It would be nicer not to use reset at all, especially since I'm not a fan of conflating "system is reset" with "system boots", but I didn't have a good idea for how to do that. --- system/bootdevice.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/system/bootdevice.c b/system/bootdevice.c index 2106f1026ff..2c55c9bd90c 100644 --- a/system/bootdevice.c +++ b/system/bootdevice.c @@ -101,20 +101,23 @@ void validate_bootdevices(const char *devices, Error **errp) void restore_boot_order(void *opaque) { char *normal_boot_order = opaque; - static int first = 1; + static int bootcount = 0; - /* Restore boot order and remove ourselves after the first boot */ - if (first) { - first = 0; + switch (bootcount++) { + case 0: + /* First boot: use the one-time config */ + return; + case 1: + /* Second boot: restore normal boot order */ + if (boot_set_handler) { + qemu_boot_set(normal_boot_order, &error_abort); + } + g_free(normal_boot_order); + return; + default: + /* Subsequent boots: keep using normal boot order */ return; } - - if (boot_set_handler) { - qemu_boot_set(normal_boot_order, &error_abort); - } - - qemu_unregister_reset(restore_boot_order, normal_boot_order); - g_free(normal_boot_order); } void check_boot_index(int32_t bootindex, Error **errp) From patchwork Tue Feb 20 16:06:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E9D6C48BC3 for ; Tue, 20 Feb 2024 16:07:36 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdf-00028S-BA; Tue, 20 Feb 2024 11:06:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdb-00026W-QT for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:31 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSdY-0005F0-J8 for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:31 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4126f48411dso4930975e9.0 for ; Tue, 20 Feb 2024 08:06:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445187; x=1709049987; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0HnwHWnmE66bJ5KZzVID8fJ3qSazlGzlBgZNC57rU+s=; b=ACo7/si7HBiM8/Z93QSdbXr4HZD0caSv3Kbp6ryPVeUf7rbSr9OifnR+SCoV8GqYEg gEeUtEua84mNz9fQkaSwa6i65F5N1/s6o9ViOWZb4aGFvB0bLhdk2JyHqWhwaKPOi5SN huZAvyGA9tOm/YPxClqZpsoZZyXPuu126bkTuAm6MGqzDGWktxjMjJnRdpd66TnYITM2 sQ9fgu5JrsBD186rS8Ca+8ugT1rrr5ViQMD5eGfdcnNNxBnVwtviID/Hvba84JLF/OBD n+Iw34pgPU1NUhFypy8LSAu7XMDuUVaOLzGtl2yAvKL2oIvkG1KbYxf5Hj2Te3Pz8xjj KJuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445187; x=1709049987; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0HnwHWnmE66bJ5KZzVID8fJ3qSazlGzlBgZNC57rU+s=; b=Rnn2G9KXoCKRdS2i6t5MAcQ7B3Uh3Ayg2pfpaOFLo4jDEZ3nBiuqCQTR0u8BdvtnK8 mh5l+s4FbKN0I6xxjqrdoUL/Vn1xsbEPH48Ak3HYA0eqZZJmRvNtOJ+jYf5bWkn3JWXI 9AIiLkdyeV3BctjO004TkvJv5koSC6muzOX5mBdEAgb8HlpsIK6pQ4M+jD4GTvyBneit vlCmSQFVKwWAntoYELSJIkh6Pdi/01+RLM3r9LDs4QBATklop3qiP896nmmXa1s0oOpp Z5oEJRa46gQjQARVBe3TtMMh9+H09XSHtA6ZosCjYmXKbFpzYcLzDEpIrW7dfUsC5lwW cNmg== X-Gm-Message-State: AOJu0YxJk+z1kJcNaZ4f/iNl9kb3knYQ1szMOsqKtgNzitpbsu/OPwIi 6K5K40vBlsW3WlipoOoWKVztbbSJfogtivtGrzsZaCaikq2tZTelvGlXP+S2XqAqmwcKvWCv8C/ g X-Google-Smtp-Source: AGHT+IHWwpEYkU3V3rbr6dCWboC6iHviqdeymbJ31jTDGnEHxvy1lDWm4eqU/SefGIZ7VxM3rq8z6w== X-Received: by 2002:a05:600c:358b:b0:412:6e83:b89d with SMTP id p11-20020a05600c358b00b004126e83b89dmr2125103wmq.8.1708445187036; Tue, 20 Feb 2024 08:06:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 04/10] include/qom/object.h: New OBJECT_DEFINE_SIMPLE_TYPE{, _WITH_INTERFACES} macros Date: Tue, 20 Feb 2024 16:06:16 +0000 Message-Id: <20240220160622.114437-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have an OBJECT_DEFINE_TYPE_EXTENDED macro, plus several variations on it, which emits the boilerplate for the TypeInfo and ensures it is registered with the type system. However, all the existing macros insist that the type being defined has its own FooClass struct, so they aren't useful for the common case of a simple leaf class which doesn't have any new methods or any other need for its own class struct (that is, for the kind of type that OBJECT_DECLARE_SIMPLE_TYPE declares). Pull the actual implementation of OBJECT_DEFINE_TYPE_EXTENDED out into a new DO_OBJECT_DEFINE_TYPE_EXTENDED which parameterizes the value we use for the class_size field. This lets us add a new OBJECT_DEFINE_SIMPLE_TYPE which does the same job as the various existing OBJECT_DEFINE_*_TYPE_* family macros for this kind of simple type, and the variant OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES for when the type will implement some interfaces. Reviewed-by: Daniel P. Berrangé Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- docs/devel/qom.rst | 34 +++++++++++-- include/qom/object.h | 114 +++++++++++++++++++++++++++++++++---------- 2 files changed, 117 insertions(+), 31 deletions(-) diff --git a/docs/devel/qom.rst b/docs/devel/qom.rst index 9918fac7f21..0889ca949c1 100644 --- a/docs/devel/qom.rst +++ b/docs/devel/qom.rst @@ -348,12 +348,14 @@ used. This does the same as OBJECT_DECLARE_SIMPLE_TYPE(), but without the 'struct MyDeviceClass' definition. To implement the type, the OBJECT_DEFINE macro family is available. -In the simple case the OBJECT_DEFINE_TYPE macro is suitable: +For the simplest case of a leaf class which doesn't need any of its +own virtual functions (i.e. which was declared with OBJECT_DECLARE_SIMPLE_TYPE) +the OBJECT_DEFINE_SIMPLE_TYPE macro is suitable: .. code-block:: c :caption: Defining a simple type - OBJECT_DEFINE_TYPE(MyDevice, my_device, MY_DEVICE, DEVICE) + OBJECT_DEFINE_SIMPLE_TYPE(MyDevice, my_device, MY_DEVICE, DEVICE) This is equivalent to the following: @@ -370,7 +372,6 @@ This is equivalent to the following: .instance_size = sizeof(MyDevice), .instance_init = my_device_init, .instance_finalize = my_device_finalize, - .class_size = sizeof(MyDeviceClass), .class_init = my_device_class_init, }; @@ -385,13 +386,36 @@ This is sufficient to get the type registered with the type system, and the three standard methods now need to be implemented along with any other logic required for the type. +If the class needs its own virtual methods, or has some other +per-class state it needs to store in its own class struct, +then you can use the OBJECT_DEFINE_TYPE macro. This does the +same thing as OBJECT_DEFINE_SIMPLE_TYPE, but it also sets the +class_size of the type to the size of the class struct. + +.. code-block:: c + :caption: Defining a type which needs a class struct + + OBJECT_DEFINE_TYPE(MyDevice, my_device, MY_DEVICE, DEVICE) + If the type needs to implement one or more interfaces, then the -OBJECT_DEFINE_TYPE_WITH_INTERFACES() macro can be used instead. -This accepts an array of interface type names. +OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES() and +OBJECT_DEFINE_TYPE_WITH_INTERFACES() macros can be used instead. +These accept an array of interface type names. The difference between +them is that the former is for simple leaf classes that don't need +a class struct, and the latter is for when you will be defining +a class struct. .. code-block:: c :caption: Defining a simple type implementing interfaces + OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(MyDevice, my_device, + MY_DEVICE, DEVICE, + { TYPE_USER_CREATABLE }, + { NULL }) + +.. code-block:: c + :caption: Defining a type implementing interfaces + OBJECT_DEFINE_TYPE_WITH_INTERFACES(MyDevice, my_device, MY_DEVICE, DEVICE, { TYPE_USER_CREATABLE }, diff --git a/include/qom/object.h b/include/qom/object.h index afccd24ca7a..f52ab216cdd 100644 --- a/include/qom/object.h +++ b/include/qom/object.h @@ -258,6 +258,51 @@ struct Object DECLARE_INSTANCE_CHECKER(InstanceType, MODULE_OBJ_NAME, TYPE_##MODULE_OBJ_NAME) +/** + * DO_OBJECT_DEFINE_TYPE_EXTENDED: + * @ModuleObjName: the object name with initial caps + * @module_obj_name: the object name in lowercase with underscore separators + * @MODULE_OBJ_NAME: the object name in uppercase with underscore separators + * @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore + * separators + * @ABSTRACT: boolean flag to indicate whether the object can be instantiated + * @CLASS_SIZE: size of the type's class + * @...: list of initializers for "InterfaceInfo" to declare implemented interfaces + * + * This is the base macro used to implement all the OBJECT_DEFINE_* + * macros. It should never be used directly in a source file. + */ +#define DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \ + MODULE_OBJ_NAME, \ + PARENT_MODULE_OBJ_NAME, \ + ABSTRACT, CLASS_SIZE, ...) \ + static void \ + module_obj_name##_finalize(Object *obj); \ + static void \ + module_obj_name##_class_init(ObjectClass *oc, void *data); \ + static void \ + module_obj_name##_init(Object *obj); \ + \ + static const TypeInfo module_obj_name##_info = { \ + .parent = TYPE_##PARENT_MODULE_OBJ_NAME, \ + .name = TYPE_##MODULE_OBJ_NAME, \ + .instance_size = sizeof(ModuleObjName), \ + .instance_align = __alignof__(ModuleObjName), \ + .instance_init = module_obj_name##_init, \ + .instance_finalize = module_obj_name##_finalize, \ + .class_size = CLASS_SIZE, \ + .class_init = module_obj_name##_class_init, \ + .abstract = ABSTRACT, \ + .interfaces = (InterfaceInfo[]) { __VA_ARGS__ } , \ + }; \ + \ + static void \ + module_obj_name##_register_types(void) \ + { \ + type_register_static(&module_obj_name##_info); \ + } \ + type_init(module_obj_name##_register_types); + /** * OBJECT_DEFINE_TYPE_EXTENDED: * @ModuleObjName: the object name with initial caps @@ -284,32 +329,10 @@ struct Object #define OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \ MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \ ABSTRACT, ...) \ - static void \ - module_obj_name##_finalize(Object *obj); \ - static void \ - module_obj_name##_class_init(ObjectClass *oc, void *data); \ - static void \ - module_obj_name##_init(Object *obj); \ - \ - static const TypeInfo module_obj_name##_info = { \ - .parent = TYPE_##PARENT_MODULE_OBJ_NAME, \ - .name = TYPE_##MODULE_OBJ_NAME, \ - .instance_size = sizeof(ModuleObjName), \ - .instance_align = __alignof__(ModuleObjName), \ - .instance_init = module_obj_name##_init, \ - .instance_finalize = module_obj_name##_finalize, \ - .class_size = sizeof(ModuleObjName##Class), \ - .class_init = module_obj_name##_class_init, \ - .abstract = ABSTRACT, \ - .interfaces = (InterfaceInfo[]) { __VA_ARGS__ } , \ - }; \ - \ - static void \ - module_obj_name##_register_types(void) \ - { \ - type_register_static(&module_obj_name##_info); \ - } \ - type_init(module_obj_name##_register_types); + DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \ + MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \ + ABSTRACT, sizeof(ModuleObjName##Class), \ + __VA_ARGS__) /** * OBJECT_DEFINE_TYPE: @@ -368,6 +391,45 @@ struct Object MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \ true, { NULL }) +/** + * OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES: + * @ModuleObjName: the object name with initial caps + * @module_obj_name: the object name in lowercase with underscore separators + * @MODULE_OBJ_NAME: the object name in uppercase with underscore separators + * @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore + * separators + * + * This is a variant of OBJECT_DEFINE_TYPE_EXTENDED, which is suitable for + * the case of a non-abstract type, with interfaces, and with no requirement + * for a class struct. + */ +#define OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ModuleObjName, \ + module_obj_name, \ + MODULE_OBJ_NAME, \ + PARENT_MODULE_OBJ_NAME, ...) \ + DO_OBJECT_DEFINE_TYPE_EXTENDED(ModuleObjName, module_obj_name, \ + MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, \ + false, 0, __VA_ARGS__) + +/** + * OBJECT_DEFINE_SIMPLE_TYPE: + * @ModuleObjName: the object name with initial caps + * @module_obj_name: the object name in lowercase with underscore separators + * @MODULE_OBJ_NAME: the object name in uppercase with underscore separators + * @PARENT_MODULE_OBJ_NAME: the parent object name in uppercase with underscore + * separators + * + * This is a variant of OBJECT_DEFINE_TYPE_EXTENDED, which is suitable for + * the common case of a non-abstract type, without any interfaces, and with + * no requirement for a class struct. If you declared your type with + * OBJECT_DECLARE_SIMPLE_TYPE then this is probably the right choice for + * defining it. + */ +#define OBJECT_DEFINE_SIMPLE_TYPE(ModuleObjName, module_obj_name, \ + MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME) \ + OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ModuleObjName, module_obj_name, \ + MODULE_OBJ_NAME, PARENT_MODULE_OBJ_NAME, { NULL }) + /** * struct TypeInfo: * @name: The name of the type. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 05/10] hw/core: Add documentation and license comments to reset.h Date: Tue, 20 Feb 2024 16:06:17 +0000 Message-Id: <20240220160622.114437-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add the usual boilerplate license/copyright comment to reset.h (using the text from reset.c), and document the existing functions. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- include/sysemu/reset.h | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h index 609e4d50c26..6aa11846a69 100644 --- a/include/sysemu/reset.h +++ b/include/sysemu/reset.h @@ -1,3 +1,29 @@ +/* + * Reset handlers. + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2016 Red Hat, Inc. + * Copyright (c) 2024 Linaro, Ltd. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + #ifndef QEMU_SYSEMU_RESET_H #define QEMU_SYSEMU_RESET_H @@ -5,9 +31,62 @@ typedef void QEMUResetHandler(void *opaque); +/** + * qemu_register_reset: Register a callback for system reset + * @func: function to call + * @opaque: opaque data to pass to @func + * + * Register @func on the list of functions which are called when the + * entire system is reset. The functions are called in the order in + * which they are registered. + * + * In general this function should not be used in new code where possible; + * for instance device model reset is better accomplished using the + * methods on DeviceState. + * + * It is not permitted to register or unregister reset functions from + * within the @func callback. + * + * We assume that the caller holds the BQL. + */ void qemu_register_reset(QEMUResetHandler *func, void *opaque); + +/** + * qemu_register_reset_nosnapshotload: Register a callback for system reset + * @func: function to call + * @opaque: opaque data to pass to @func + * + * This is the same as qemu_register_reset(), except that @func is + * not called if the reason that the system is being reset is to + * put it into a clean state prior to loading a snapshot (i.e. for + * SHUTDOWN_CAUSE_SNAPSHOT_LOAD). + */ void qemu_register_reset_nosnapshotload(QEMUResetHandler *func, void *opaque); + +/** + * qemu_unregister_reset: Unregister a system reset callback + * @func: function registered with qemu_register_reset() + * @opaque: the same opaque data that was passed to qemu_register_reset() + * + * Undo the effects of a qemu_register_reset(). The @func and @opaque + * must both match the arguments originally used with qemu_register_reset(). + * + * We assume that the caller holds the BQL. + */ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque); + +/** + * qemu_devices_reset: Perform a complete system reset + * @reason: reason for the reset + * + * This function performs the low-level work needed to do a complete reset + * of the system (calling all the callbacks registered with + * qemu_register_reset()). It should only be called by the code in a + * MachineClass reset method. + * + * If you want to trigger a system reset from, for instance, a device + * model, don't use this function. Use qemu_system_reset_request(). + */ void qemu_devices_reset(ShutdownCause reason); #endif From patchwork Tue Feb 20 16:06:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564214 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DAB47C48BC3 for ; Tue, 20 Feb 2024 16:08:13 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdg-00029R-Ez; Tue, 20 Feb 2024 11:06:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdc-00027B-I1 for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:32 -0500 Received: from mail-lf1-x12f.google.com ([2a00:1450:4864:20::12f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSda-0005FJ-FP for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:32 -0500 Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-512cba0f953so583809e87.2 for ; Tue, 20 Feb 2024 08:06:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445188; x=1709049988; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ddKtqyWJkcgxhf/BG7mdQTStu44ETF+Ta3q791Jg39I=; b=i7ki35Gg07AFoxj5eJLneHeWqWUoWsDZJiCRzLkRUH4vVKEiF5MYXkAfSuUzPjhc7B S9hPqfn+gUU2LcSQy8RilnMl+poszhMEYeiIgdi7xWS7m/6hOVKRNqPElL/e7eLCAxS7 HT/KIs7P0/kKi5AtLJdm2He/9gxo37m/0aF5UOjyKCD/8dD0VR0u3ncjSO/yxC7TzHSv +N5UTOr3E++V8EmprvcFD5S3fnjc9J5+7Wie2UTDJKxZ14eHkIp9z6yXA06TbKyVh5Hz Q/0wldsUqAiUQLtGTyW0rlQo1j2iXr4laY0EMVPyeDjBMZLpY1mbtfmXLXpZv+ItAnGF 3WZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445188; x=1709049988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ddKtqyWJkcgxhf/BG7mdQTStu44ETF+Ta3q791Jg39I=; b=iUHm+3/nGvNum6QLQd3sJr85kraKvU0x8uUbtYQSLd71qmS+8CXSYy8cyXwzWRyQmB 85fmc1CJHZfkRmAjfWYgubHPDaFBJGDphhiaASMYRC69M6VMlQMftVybEbaf2EmPN67d YyC0IUmongU+3QXhRBqsUpFs5k2y/G/iViEGDIMhtOWZQmMdC2RKcgX7g4X2apyo6lim w9UuF3IBLmu8ZyK1p7ZRW4K6/XAi3Bnio+7rLWLD087LZ0zn0iCSSik4i5P+TsUCemCV SbV3+BphP0yyzvGnHL7BZCMkNmXM5MP/1vTsMGAXq/2ancmQtNO48wkmXZoMRSoJuHLO O/Ng== X-Gm-Message-State: AOJu0YxtYnFchQN8Bpb8CJQsmPh+d+85mCUK4rELvJ9mdztgU5jDYr8y phoAOkrUx11vZKdzdgODClBl4374YNfdIyBGdUzXh4YS+eW+66yOulydmnv93an0/JEHS6H3ApV n X-Google-Smtp-Source: AGHT+IErMCe2fH02jbYeG2pO/xVhKdENQOdZQ8KAKyjjSXf7QXft1BX3kKRnDdY85G4R4Bw6+R286w== X-Received: by 2002:ac2:446d:0:b0:512:bf09:5ea9 with SMTP id y13-20020ac2446d000000b00512bf095ea9mr2607364lfl.63.1708445188220; Tue, 20 Feb 2024 08:06:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 06/10] hw/core: Add ResetContainer which holds objects implementing Resettable Date: Tue, 20 Feb 2024 16:06:18 +0000 Message-Id: <20240220160622.114437-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implement a ResetContainer. This is a subclass of Object, and it implements the Resettable interface. The container holds a list of arbitrary other objects which implement Resettable, and when the container is reset, all the objects it contains are also reset. This will allow us to have a 3-phase-reset equivalent of the old qemu_register_reset() API: we will have a single "simulation reset" top level ResetContainer, and objects in it are the equivalent of the old QEMUResetHandler functions. The qemu_register_reset() API manages its list of callbacks using a QTAILQ, but here we use a GPtrArray for our list of Resettable children: we expect the "remove" operation (which will need to do an iteration through the list) to be fairly uncommon, and we get simpler code with fewer memory allocations. Since there is currently no listed owner in MAINTAINERS for the existing reset-related source files, create a new section for them, and add these new files there also. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu --- MAINTAINERS | 10 +++++ include/hw/core/resetcontainer.h | 48 ++++++++++++++++++++ hw/core/resetcontainer.c | 76 ++++++++++++++++++++++++++++++++ hw/core/meson.build | 1 + 4 files changed, 135 insertions(+) create mode 100644 include/hw/core/resetcontainer.h create mode 100644 hw/core/resetcontainer.c diff --git a/MAINTAINERS b/MAINTAINERS index 7d61fb93194..df8a526905b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3667,6 +3667,16 @@ F: hw/core/clock-vmstate.c F: hw/core/qdev-clock.c F: docs/devel/clocks.rst +Reset framework +M: Peter Maydell +S: Maintained +F: include/hw/resettable.h +F: include/hw/core/resetcontainer.h +F: include/sysemu/reset.h +F: hw/core/reset.c +F: hw/core/resettable.c +F: hw/core/resetcontainer.c + Usermode Emulation ------------------ Overall usermode emulation diff --git a/include/hw/core/resetcontainer.h b/include/hw/core/resetcontainer.h new file mode 100644 index 00000000000..23db0c7a880 --- /dev/null +++ b/include/hw/core/resetcontainer.h @@ -0,0 +1,48 @@ +/* + * Reset container + * + * Copyright (c) 2024 Linaro, Ltd + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef HW_RESETCONTAINER_H +#define HW_RESETCONTAINER_H + +/* + * The "reset container" is an object which implements the Resettable + * interface. It contains a list of arbitrary other objects which also + * implement Resettable. Resetting the reset container resets all the + * objects in it. + */ + +#include "qom/object.h" + +#define TYPE_RESETTABLE_CONTAINER "resettable-container" +OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER) + +/** + * resettable_container_add: Add a resettable object to the container + * @rc: container + * @obj: object to add to the container + * + * Add @obj to the ResettableContainer @rc. @obj must implement the + * Resettable interface. + * + * When @rc is reset, it will reset every object that has been added + * to it, in the order they were added. + */ +void resettable_container_add(ResettableContainer *rc, Object *obj); + +/** + * resettable_container_remove: Remove an object from the container + * @rc: container + * @obj: object to remove from the container + * + * Remove @obj from the ResettableContainer @rc. @obj must have been + * previously added to this container. + */ +void resettable_container_remove(ResettableContainer *rc, Object *obj); + +#endif diff --git a/hw/core/resetcontainer.c b/hw/core/resetcontainer.c new file mode 100644 index 00000000000..cd627f16f0e --- /dev/null +++ b/hw/core/resetcontainer.c @@ -0,0 +1,76 @@ +/* + * Reset container + * + * Copyright (c) 2024 Linaro, Ltd + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +/* + * The "reset container" is an object which implements the Resettable + * interface. It contains a list of arbitrary other objects which also + * implement Resettable. Resetting the reset container resets all the + * objects in it. + */ + +#include "qemu/osdep.h" +#include "hw/resettable.h" +#include "hw/core/resetcontainer.h" + +struct ResettableContainer { + Object parent; + ResettableState reset_state; + GPtrArray *children; +}; + +OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(ResettableContainer, resettable_container, RESETTABLE_CONTAINER, OBJECT, { TYPE_RESETTABLE_INTERFACE }, { }) + +void resettable_container_add(ResettableContainer *rc, Object *obj) +{ + g_ptr_array_add(rc->children, obj); +} + +void resettable_container_remove(ResettableContainer *rc, Object *obj) +{ + g_ptr_array_remove(rc->children, obj); +} + +static ResettableState *resettable_container_get_state(Object *obj) +{ + ResettableContainer *rc = RESETTABLE_CONTAINER(obj); + return &rc->reset_state; +} + +static void resettable_container_child_foreach(Object *obj, + ResettableChildCallback cb, + void *opaque, ResetType type) +{ + ResettableContainer *rc = RESETTABLE_CONTAINER(obj); + unsigned int len = rc->children->len; + + for (unsigned int i = 0; i < len; i++) { + cb(g_ptr_array_index(rc->children, i), opaque, type); + /* Detect callbacks trying to unregister themselves */ + assert(len == rc->children->len); + } +} + +static void resettable_container_init(Object *obj) +{ + ResettableContainer *rc = RESETTABLE_CONTAINER(obj); + + rc->children = g_ptr_array_new(); +} + +static void resettable_container_finalize(Object *obj) +{ +} + +static void resettable_container_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->get_state = resettable_container_get_state; + rc->child_foreach = resettable_container_child_foreach; +} diff --git a/hw/core/meson.build b/hw/core/meson.build index 67dad04de55..e26f2e088c3 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -4,6 +4,7 @@ hwcore_ss.add(files( 'qdev-properties.c', 'qdev.c', 'reset.c', + 'resetcontainer.c', 'resettable.c', 'vmstate-if.c', # irq.c needed for qdev GPIO handling: From patchwork Tue Feb 20 16:06:19 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 07/10] hw/core/reset: Add qemu_{register, unregister}_resettable() Date: Tue, 20 Feb 2024 16:06:19 +0000 Message-Id: <20240220160622.114437-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Implement new functions qemu_register_resettable() and qemu_unregister_resettable(). These are intended to be three-phase-reset aware equivalents of the old qemu_register_reset() and qemu_unregister_reset(). Instead of passing in a function pointer and opaque, you register any QOM object that implements the Resettable interface. The implementation is simple: we have a single global instance of a ResettableContainer, which we reset in qemu_devices_reset(), and the Resettable objects passed to qemu_register_resettable() are added to it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- include/sysemu/reset.h | 37 ++++++++++++++++++++++++++++++++++--- hw/core/reset.c | 31 +++++++++++++++++++++++++++++-- 2 files changed, 63 insertions(+), 5 deletions(-) diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h index 6aa11846a69..a3de48cb9cf 100644 --- a/include/sysemu/reset.h +++ b/include/sysemu/reset.h @@ -31,6 +31,36 @@ typedef void QEMUResetHandler(void *opaque); +/** + * qemu_register_resettable: Register an object to be reset + * @obj: object to be reset: it must implement the Resettable interface + * + * Register @obj on the list of objects which will be reset when the + * simulation is reset. These objects will be reset in the order + * they were added, using the three-phase Resettable protocol, + * so first all objects go through the enter phase, then all objects + * go through the hold phase, and then finally all go through the + * exit phase. + * + * It is not permitted to register or unregister reset functions or + * resettable objects from within any of the reset phase methods of @obj. + * + * We assume that the caller holds the BQL. + */ +void qemu_register_resettable(Object *obj); + +/** + * qemu_unregister_resettable: Unregister an object to be reset + * @obj: object to unregister + * + * Remove @obj from the list of objects which are reset when the + * simulation is reset. It must have been previously added to + * the list via qemu_register_resettable(). + * + * We assume that the caller holds the BQL. + */ +void qemu_unregister_resettable(Object *obj); + /** * qemu_register_reset: Register a callback for system reset * @func: function to call @@ -44,8 +74,8 @@ typedef void QEMUResetHandler(void *opaque); * for instance device model reset is better accomplished using the * methods on DeviceState. * - * It is not permitted to register or unregister reset functions from - * within the @func callback. + * It is not permitted to register or unregister reset functions or + * resettable objects from within the @func callback. * * We assume that the caller holds the BQL. */ @@ -81,7 +111,8 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque); * * This function performs the low-level work needed to do a complete reset * of the system (calling all the callbacks registered with - * qemu_register_reset()). It should only be called by the code in a + * qemu_register_reset() and resetting all the Resettable objects registered + * with qemu_register_resettable()). It should only be called by the code in a * MachineClass reset method. * * If you want to trigger a system reset from, for instance, a device diff --git a/hw/core/reset.c b/hw/core/reset.c index d3263b613e6..a9b30e705fe 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -26,8 +26,23 @@ #include "qemu/osdep.h" #include "qemu/queue.h" #include "sysemu/reset.h" +#include "hw/resettable.h" +#include "hw/core/resetcontainer.h" -/* reset/shutdown handler */ +/* + * Return a pointer to the singleton container that holds all the Resettable + * items that will be reset when qemu_devices_reset() is called. + */ +static ResettableContainer *get_root_reset_container(void) +{ + static ResettableContainer *root_reset_container; + + if (!root_reset_container) { + root_reset_container = + RESETTABLE_CONTAINER(object_new(TYPE_RESETTABLE_CONTAINER)); + } + return root_reset_container; +} typedef struct QEMUResetEntry { QTAILQ_ENTRY(QEMUResetEntry) entry; @@ -71,6 +86,16 @@ void qemu_unregister_reset(QEMUResetHandler *func, void *opaque) } } +void qemu_register_resettable(Object *obj) +{ + resettable_container_add(get_root_reset_container(), obj); +} + +void qemu_unregister_resettable(Object *obj) +{ + resettable_container_remove(get_root_reset_container(), obj); +} + void qemu_devices_reset(ShutdownCause reason) { QEMUResetEntry *re, *nre; @@ -83,5 +108,7 @@ void qemu_devices_reset(ShutdownCause reason) } re->func(re->opaque); } -} + /* Reset the simulation */ + resettable_reset(OBJECT(get_root_reset_container()), RESET_TYPE_COLD); +} From patchwork Tue Feb 20 16:06:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2327C48BC3 for ; Tue, 20 Feb 2024 16:08:00 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdh-00029k-41; Tue, 20 Feb 2024 11:06:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdf-00028f-Ew for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:35 -0500 Received: from mail-lj1-x22d.google.com ([2a00:1450:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSdc-0005Fj-8U for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:34 -0500 Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2d22fa5c822so37841111fa.2 for ; Tue, 20 Feb 2024 08:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445189; x=1709049989; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Jfb6LK3pNRRXWdJpN9nL5H3Sn5ptvJuNMXpqXvwtbCQ=; b=OBWbDMUqHZ09vRof42SCvr0BYOfBDS8v06Rv4wH7uIlf3bjJDGAR1ne4JkoVvvIKqP Po0/nOQcxvS/Pr56UlxW76Q2wBRPQ7z8CTynWZp3zWQdn4LGkbM+G7DqNImbzHdRnD48 r6ylyJjuhryh+ZnUNpYNRA2IvURFMGUzS3rIV+kHScgDNFfmshoT5Qj6J/yE92zGVXZO cYaagk7xbzgVocqsYGA4gZQTRkdYboGBXQ8KC7v+xC5Im+04rsgb1bbe0eYjv/Szdd1j 4Y4bIiH6KE7ro8bWZTi8BepCabXJ7UY2lyxWgHOMZqYcH3JCPHhvrPPL7Mf0eAW6Q/kB CIBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445189; x=1709049989; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Jfb6LK3pNRRXWdJpN9nL5H3Sn5ptvJuNMXpqXvwtbCQ=; b=QMd1+pLksUvMkYOGnwB97zzuvz4YRLS+hW5KnBaB0lhkXRK358V1zAGQMY+dweKeJ3 FxWFP4Mkp0vdbNdIs+zCsUWCiOTeKg+I00lp7tuCE1fd71rp6AMPEbTF4r10B8hzFs5h 9q0vtHBo/GNlXPHTKhpoSNrVVWaZzrNXIKQhXnxfVY1LiDAZa/ST2d6zEvYCFzCEEK6K cMoijwdSP4C6bqqBBDGfbhLLOi4F0NHQO0cyjTj5jw9VQ7Ad+6kyVS0+pbArJTKWiK7b rypksySz6IagqzC6VzDNSoej7WB43WwzspO8dMDVQLP5qZv/0vT/zd/y1l1W/axVS41h GNuA== X-Gm-Message-State: AOJu0YzHuqEXmnzw/2f7hIKYnQfDE5r9qgjq0eSDPQne4Lln+8t5EjDl xJyzjtwRRycuQawNPbHF0fq7vTsLJytGSUPCR1MJSSoXZkrgSo1C615kj2F9ktPdfpvPE2meTNM E X-Google-Smtp-Source: AGHT+IHLbyca7SNk5UfhFX0gGCZagNHJL8z+9i5Mr/w55acm6ld04jsNt29vr1rAHd9ufySAtJjr2Q== X-Received: by 2002:a05:6512:3a83:b0:512:b04a:aa56 with SMTP id q3-20020a0565123a8300b00512b04aaa56mr7055557lfu.24.1708445189424; Tue, 20 Feb 2024 08:06:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 08/10] hw/core/reset: Implement qemu_register_reset via qemu_register_resettable Date: Tue, 20 Feb 2024 16:06:20 +0000 Message-Id: <20240220160622.114437-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reimplement qemu_register_reset() via qemu_register_resettable(). We define a new LegacyReset object which implements Resettable and defines its reset hold phase method to call a QEMUResetHandler function. When qemu_register_reset() is called, we create a new LegacyReset object and add it to the simulation_reset ResettableContainer. When qemu_unregister_reset() is called, we find the LegacyReset object in the container and remove it. This implementation of qemu_unregister_reset() means we'll end up scanning the ResetContainer's list of child objects twice, once to find the LegacyReset object, and once in g_ptr_array_remove(). In theory we could avoid this by having the ResettableContainer interface include a resettable_container_remove_with_equal_func() that took a callback method so that we could use g_ptr_array_find_with_equal_func() and g_ptr_array_remove_index(). But we don't expect qemu_unregister_reset() to be called frequently or in hot paths, and we expect the simulation_reset container to usually not have many children. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- The way that a legacy reset function needs to check the ShutdownCause and this doesn't line up with the ResetType is a bit awkward; this is an area we should come back and clean up, but I didn't want to tackle that in this patchset. --- include/sysemu/reset.h | 7 ++- hw/core/reset.c | 137 +++++++++++++++++++++++++++++++---------- 2 files changed, 110 insertions(+), 34 deletions(-) diff --git a/include/sysemu/reset.h b/include/sysemu/reset.h index a3de48cb9cf..ada4527e67e 100644 --- a/include/sysemu/reset.h +++ b/include/sysemu/reset.h @@ -67,8 +67,11 @@ void qemu_unregister_resettable(Object *obj); * @opaque: opaque data to pass to @func * * Register @func on the list of functions which are called when the - * entire system is reset. The functions are called in the order in - * which they are registered. + * entire system is reset. Functions registered with this API and + * Resettable objects registered with qemu_register_resettable() are + * handled together, in the order in which they were registered. + * Functions registered with this API are called in the 'hold' phase + * of the 3-phase reset. * * In general this function should not be used in new code where possible; * for instance device model reset is better accomplished using the diff --git a/hw/core/reset.c b/hw/core/reset.c index a9b30e705fe..d50da7e3041 100644 --- a/hw/core/reset.c +++ b/hw/core/reset.c @@ -24,7 +24,6 @@ */ #include "qemu/osdep.h" -#include "qemu/queue.h" #include "sysemu/reset.h" #include "hw/resettable.h" #include "hw/core/resetcontainer.h" @@ -44,45 +43,128 @@ static ResettableContainer *get_root_reset_container(void) return root_reset_container; } -typedef struct QEMUResetEntry { - QTAILQ_ENTRY(QEMUResetEntry) entry; +/* + * Reason why the currently in-progress qemu_devices_reset() was called. + * If we made at least SHUTDOWN_CAUSE_SNAPSHOT_LOAD have a corresponding + * ResetType we could perhaps avoid the need for this global. + */ +static ShutdownCause device_reset_reason; + +/* + * This is an Object which implements Resettable simply to call the + * callback function in the hold phase. + */ +#define TYPE_LEGACY_RESET "legacy-reset" +OBJECT_DECLARE_SIMPLE_TYPE(LegacyReset, LEGACY_RESET) + +struct LegacyReset { + Object parent; + ResettableState reset_state; QEMUResetHandler *func; void *opaque; bool skip_on_snapshot_load; -} QEMUResetEntry; +}; -static QTAILQ_HEAD(, QEMUResetEntry) reset_handlers = - QTAILQ_HEAD_INITIALIZER(reset_handlers); +OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(LegacyReset, legacy_reset, LEGACY_RESET, OBJECT, { TYPE_RESETTABLE_INTERFACE }, { }) + +static ResettableState *legacy_reset_get_state(Object *obj) +{ + LegacyReset *lr = LEGACY_RESET(obj); + return &lr->reset_state; +} + +static void legacy_reset_hold(Object *obj) +{ + LegacyReset *lr = LEGACY_RESET(obj); + + if (device_reset_reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD && + lr->skip_on_snapshot_load) { + return; + } + lr->func(lr->opaque); +} + +static void legacy_reset_init(Object *obj) +{ +} + +static void legacy_reset_finalize(Object *obj) +{ +} + +static void legacy_reset_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->get_state = legacy_reset_get_state; + rc->phases.hold = legacy_reset_hold; +} void qemu_register_reset(QEMUResetHandler *func, void *opaque) { - QEMUResetEntry *re = g_new0(QEMUResetEntry, 1); + Object *obj = object_new(TYPE_LEGACY_RESET); + LegacyReset *lr = LEGACY_RESET(obj); - re->func = func; - re->opaque = opaque; - QTAILQ_INSERT_TAIL(&reset_handlers, re, entry); + lr->func = func; + lr->opaque = opaque; + qemu_register_resettable(obj); } void qemu_register_reset_nosnapshotload(QEMUResetHandler *func, void *opaque) { - QEMUResetEntry *re = g_new0(QEMUResetEntry, 1); + Object *obj = object_new(TYPE_LEGACY_RESET); + LegacyReset *lr = LEGACY_RESET(obj); - re->func = func; - re->opaque = opaque; - re->skip_on_snapshot_load = true; - QTAILQ_INSERT_TAIL(&reset_handlers, re, entry); + lr->func = func; + lr->opaque = opaque; + lr->skip_on_snapshot_load = true; + qemu_register_resettable(obj); +} + +typedef struct FindLegacyInfo { + QEMUResetHandler *func; + void *opaque; + LegacyReset *lr; +} FindLegacyInfo; + +static void find_legacy_reset_cb(Object *obj, void *opaque, ResetType type) +{ + LegacyReset *lr; + FindLegacyInfo *fli = opaque; + + /* Not everything in the ResettableContainer will be a LegacyReset */ + lr = LEGACY_RESET(object_dynamic_cast(obj, TYPE_LEGACY_RESET)); + if (lr && lr->func == fli->func && lr->opaque == fli->opaque) { + fli->lr = lr; + } +} + +static LegacyReset *find_legacy_reset(QEMUResetHandler *func, void *opaque) +{ + /* + * Find the LegacyReset with the specified func and opaque, + * by getting the ResettableContainer to call our callback for + * every item in it. + */ + ResettableContainer *rootcon = get_root_reset_container(); + ResettableClass *rc = RESETTABLE_GET_CLASS(rootcon); + FindLegacyInfo fli; + + fli.func = func; + fli.opaque = opaque; + fli.lr = NULL; + rc->child_foreach(OBJECT(rootcon), find_legacy_reset_cb, + &fli, RESET_TYPE_COLD); + return fli.lr; } void qemu_unregister_reset(QEMUResetHandler *func, void *opaque) { - QEMUResetEntry *re; + Object *obj = OBJECT(find_legacy_reset(func, opaque)); - QTAILQ_FOREACH(re, &reset_handlers, entry) { - if (re->func == func && re->opaque == opaque) { - QTAILQ_REMOVE(&reset_handlers, re, entry); - g_free(re); - return; - } + if (obj) { + qemu_unregister_resettable(obj); + object_unref(obj); } } @@ -98,16 +180,7 @@ void qemu_unregister_resettable(Object *obj) void qemu_devices_reset(ShutdownCause reason) { - QEMUResetEntry *re, *nre; - - /* reset all devices */ - QTAILQ_FOREACH_SAFE(re, &reset_handlers, entry, nre) { - if (reason == SHUTDOWN_CAUSE_SNAPSHOT_LOAD && - re->skip_on_snapshot_load) { - continue; - } - re->func(re->opaque); - } + device_reset_reason = reason; /* Reset the simulation */ resettable_reset(OBJECT(get_root_reset_container()), RESET_TYPE_COLD); From patchwork Tue Feb 20 16:06:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DC061C48BC3 for ; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 09/10] hw/core/machine: Use qemu_register_resettable for sysbus reset Date: Tue, 20 Feb 2024 16:06:21 +0000 Message-Id: <20240220160622.114437-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::235; envelope-from=peter.maydell@linaro.org; helo=mail-lj1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move the reset of the sysbus (and thus all devices and buses anywhere on the qbus tree) from qemu_register_reset() to qemu_register_resettable(). This is a behaviour change: because qemu_register_resettable() is aware of three-phase reset, this now means that: * 'enter' phase reset methods of devices and buses are called before any legacy reset callbacks registered with qemu_register_reset() * 'exit' phase reset methods of devices and buses are called after any legacy qemu_register_reset() callbacks Put another way, a qemu_register_reset() callback is now correctly ordered in the 'hold' phase along with any other 'hold' phase methods. The motivation for doing this is that we will now be able to resolve some reset-ordering issues using the three-phase mechanism, because the 'exit' phase is always after the 'hold' phase, even when the 'hold' phase function was registered with qemu_register_reset(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Zhao Liu --- I believe that given we don't make much use of enter/exit phases currently that this is unlikely to cause unexpected regressions due to an accidental reset-order dependency that is no longer satisfied, but it's always possible... --- hw/core/machine.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/core/machine.c b/hw/core/machine.c index fb5afdcae4c..9ac5d5389a6 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -1577,14 +1577,13 @@ void qdev_machine_creation_done(void) /* TODO: once all bus devices are qdevified, this should be done * when bus is created by qdev.c */ /* - * TODO: If we had a main 'reset container' that the whole system - * lived in, we could reset that using the multi-phase reset - * APIs. For the moment, we just reset the sysbus, which will cause + * This is where we arrange for the sysbus to be reset when the + * whole simulation is reset. In turn, resetting the sysbus will cause * all devices hanging off it (and all their child buses, recursively) * to be reset. Note that this will *not* reset any Device objects * which are not attached to some part of the qbus tree! */ - qemu_register_reset(resettable_cold_reset_fn, sysbus_get_default()); + qemu_register_resettable(OBJECT(sysbus_get_default())); notifier_list_notify(&machine_init_done_notifiers, NULL); From patchwork Tue Feb 20 16:06:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13564216 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 55A43C48BC3 for ; Tue, 20 Feb 2024 16:08:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rcSdi-0002Ap-Nc; Tue, 20 Feb 2024 11:06:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rcSdf-00028X-7M for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:35 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rcSdc-0005G0-FI for qemu-devel@nongnu.org; Tue, 20 Feb 2024 11:06:34 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-41269c801eeso13266925e9.2 for ; Tue, 20 Feb 2024 08:06:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1708445190; x=1709049990; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ItiTCkAfmzt4OaTQ5t65CWwnYcleCpOpQ9IF8gCFhuc=; b=jcbstVlL9o8xKfoeXjqHmARA7c8+9YChtFy31J2nwUzA6GcUrjC4HcBy8BUgFBj9KQ av7UHtgv1hIWqtUb7nCDmA8iiTPm05FhXCNeQvo0rO/ELdGxb8GofBxOSbYa0HVG25RH LAjriSnZ1HjwBB1IQYOCt3ZVB3REO240z5PJCovCIRsNpR77EH7gvLdxHWg6evp4IdhZ xHpM/scLG7CxX/pztj1hWFhzPYIX0QF2hCmrhHdIVQjYG23L84wO3DOe1GX2fyysOV3T FKRlPlZQQnt0amakwga3fZH7O78APBcKaZA+tcRv3uTA5aluXUvE4S8TMyp4X/Hhvc+c 3kWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708445190; x=1709049990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ItiTCkAfmzt4OaTQ5t65CWwnYcleCpOpQ9IF8gCFhuc=; b=gecI4L9b2Aalbn/CvjGkRUO8phKv/m47w5YpnZ8GnbCAbcZzyKm2SKQ5euOAny/yn7 rmt4xDEvGoIH25/V3ABldvaGA86y+1Ip9cIxhzNSvb86wXdoGxOrphs1ESEHehCJDzys uVTTJqx5fhbTt2Z8dy8il9KaGsK/zAitBbAB5YgcE2Z6phu8f6/5Pd9I+gSthIstm97J V5y4CQp1ySae2gN0LrfRm46v2Bw4zluBe2cZ144tSRINVggjZ1uZkckbBDubTQFdOnEk iGRBLmdNLSgQt5+rowhLSB3bZkxnJKV1IJjDkoHZgPh4BNbE4oYK/MSE95MLyDnImJcM fuUA== X-Gm-Message-State: AOJu0Yyi1t1tg9qu7xXkQ1UqusR6Og02SD5DRw2H05UO2Q6+YST/7kNw nlHMjMIcE7LAvJp8vhW0eSNxtZLFJR3A/baKH97NBWXsKbXXKt4BR5KjFlOR8ml+QbNiCmWRGWd l X-Google-Smtp-Source: AGHT+IG5fA8cRiSQZMvAw0nvfAZ0CNed/B4mryIZdzif8FxC3m1+XlnhTHny8WnaRTLLkhdnPDB33g== X-Received: by 2002:a05:600c:4706:b0:412:7180:eaf7 with SMTP id v6-20020a05600c470600b004127180eaf7mr792749wmo.6.1708445190608; Tue, 20 Feb 2024 08:06:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f8-20020a05600c4e8800b0040f0219c371sm15299927wmq.19.2024.02.20.08.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 08:06:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , "Michael S. Tsirkin" , "Gonglei (Arei)" Subject: [PATCH 10/10] docs/devel/reset: Update to discuss system reset Date: Tue, 20 Feb 2024 16:06:22 +0000 Message-Id: <20240220160622.114437-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240220160622.114437-1-peter.maydell@linaro.org> References: <20240220160622.114437-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that system reset uses a three-phase-reset, update the reset documentation to include a section describing how this works. Include documentation of the current major beartrap in reset, which is that only devices on the qbus tree will get automatically reset. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- This merely documents the current situation, and says nothing about what we might like to do with it in future... --- docs/devel/reset.rst | 44 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index d4e79718bac..2ea85e7779b 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -11,8 +11,8 @@ whole group can be reset consistently. Each individual member object does not have to care about others; in particular, problems of order (which object is reset first) are addressed. -As of now DeviceClass and BusClass implement this interface. - +The main object types which implement this interface are DeviceClass +and BusClass. Triggering reset ---------------- @@ -288,3 +288,43 @@ There is currently 2 cases where this function is used: 2. *hot bus change*; it means an existing live device is added, moved or removed in the bus hierarchy. At the moment, it occurs only in the raspi machines for changing the sdbus used by sd card. + +Reset of the complete system +---------------------------- + +Reset of the complete system is a little complicated. The typical +flow is: + +1. Code which wishes to reset the entire system does so by calling + ``qemu_system_reset_request()``. This schedules a reset, but the + reset will happen asynchronously after the function returns. + That makes this safe to call from, for example, device models. + +2. The function which is called to make the reset happen is + ``qemu_system_reset()``. Generally only core system code should + call this directly. + +3. ``qemu_system_reset()`` calls the ``MachineClass::reset`` method of + the current machine, if it has one. That method must call + ``qemu_devices_reset()``. If the machine has no reset method, + ``qemu_system_reset()`` calls ``qemu_devices_reset()`` directly. + +4. ``qemu_devices_reset()`` performs a reset of the system, using + the three-phase mechanism listed above. It resets all objects + that were registered with it using ``qemu_register_resettable()``. + It also calls all the functions registered with it using + ``qemu_register_reset()``. Those functions are called during the + "hold" phase of this reset. + +5. The most important object that this reset resets is the + 'sysbus' bus. The sysbus bus is the root of the qbus tree. This + means that all devices on the sysbus are reset, and all their + child buses, and all the devices on those child buses. + +6. Devices which are not on the qbus tree are *not* automatically + reset! (The most obvious example of this is CPU objects, but + anything that directly inherits from ``TYPE_OBJECT`` or ``TYPE_DEVICE`` + rather than from ``TYPE_SYS_BUS_DEVICE`` or some other plugs-into-a-bus + type will be in this category.) You need to therefore arrange for these + to be reset in some other way (e.g. using ``qemu_register_resettable()`` + or ``qemu_register_reset()``).