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Wed, 21 Feb 2024 09:17:21 -0800 (PST) Date: Wed, 21 Feb 2024 17:17:15 +0000 In-Reply-To: <20240221171716.1260192-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20240221171716.1260192-1-nabihestefan@google.com> X-Mailer: git-send-email 2.44.0.rc0.258.g7320e95886-goog Message-ID: <20240221171716.1260192-2-nabihestefan@google.com> Subject: [PATCH 1/2] hw/arm/smmuv3: Check StreamIDs against SMMU_IDR1.SIDSIZE value From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, qemu-block@nongnu.org, its@irrelevant.dk, kbusch@kernel.org, eric.auger@redhat.com, roqueh@google.com, nabihestefan@google.com Received-SPF: pass client-ip=2607:f8b0:4864:20::b49; envelope-from=3ITDWZQwKChA3qryxu89uvq3w44w1u.s426u2A-tuBu1343w3A.47w@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Roque Arcudia Hernandez Current implementation checks the StreamIDs against STRTAB_BASE_CFG.LOG2SIZE register field value and a constant SMMU_IDR1_SIDSIZE which is also used as initial value for field SMMU_IDR1.SIDSIZE. This limits the possibility of extending the SMMUv3 by inheritance and redefining the value of SMMU_IDR1.SIDSIZE because the check is hardcoded to the constant SMMU_IDR1_SIDSIZE rather than the register value. Signed-off-by: Roque Arcudia Hernandez Signed-off-by: Nabih Estefan Reviewed-by: Eric Auger --- hw/arm/smmuv3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 9eb56a70f3..a01031821a 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -580,15 +580,17 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, { dma_addr_t addr, strtab_base; uint32_t log2size; + uint32_t idr1_sidsize; int strtab_size_shift; int ret; trace_smmuv3_find_ste(sid, s->features, s->sid_split); log2size = FIELD_EX32(s->strtab_base_cfg, STRTAB_BASE_CFG, LOG2SIZE); + idr1_sidsize = FIELD_EX32(s->idr[1], IDR1, SIDSIZE); /* * Check SID range against both guest-configured and implementation limits */ - if (sid >= (1 << MIN(log2size, SMMU_IDR1_SIDSIZE))) { + if (sid >= (1 << MIN(log2size, idr1_sidsize))) { event->type = SMMU_EVT_C_BAD_STREAMID; return -EINVAL; } From patchwork Wed Feb 21 17:17:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nabih Estefan X-Patchwork-Id: 13566016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD5E3C48BEB for ; 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envelope-from=3IjDWZQwKChE4rszyv9Avwr4x55x2v.t537v3B-uvCv2454x4B.58x@flex--nabihestefan.bounces.google.com; helo=mail-yb1-xb49.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Roque Arcudia Hernandez According to the SMMU specification the StreamID construction and size is IMPLEMENTATION DEFINED, the size being between 0 and 32 bits. This patch creates virtual functions get_sid and get_iommu_mr to allow different implementations of how the StreamID is constructed via inheritance. The default implementation of these functions will match the current ones where the BDF is used directly as StreamID. Signed-off-by: Roque Arcudia Hernandez Signed-off-by: Nabih Estefan --- hw/arm/smmu-common.c | 12 ++++++++++++ include/hw/arm/smmu-common.h | 16 +++++++++++----- 2 files changed, 23 insertions(+), 5 deletions(-) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 4caedb4998..14b3240a88 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -621,6 +621,11 @@ static const PCIIOMMUOps smmu_ops = { }; IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid) +{ + return ARM_SMMU_GET_CLASS(s)->get_iommu_mr(s, sid); +} + +static IOMMUMemoryRegion *smmu_base_iommu_mr(SMMUState *s, uint32_t sid) { uint8_t bus_n, devfn; SMMUPciBus *smmu_bus; @@ -659,6 +664,11 @@ void smmu_inv_notifiers_all(SMMUState *s) } } +static uint32_t smmu_base_get_sid(SMMUDevice *sdev) +{ + return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); +} + static void smmu_base_realize(DeviceState *dev, Error **errp) { SMMUState *s = ARM_SMMU(dev); @@ -709,6 +719,8 @@ static void smmu_base_class_init(ObjectClass *klass, void *data) device_class_set_parent_realize(dc, smmu_base_realize, &sbc->parent_realize); rc->phases.hold = smmu_base_reset_hold; + sbc->get_sid = smmu_base_get_sid; + sbc->get_iommu_mr = smmu_base_iommu_mr; } static const TypeInfo smmu_base_info = { diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 5ec2e6c1a4..d53121fe37 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -131,6 +131,9 @@ typedef struct SMMUIOTLBKey { uint8_t level; } SMMUIOTLBKey; +#define TYPE_ARM_SMMU "arm-smmu" +OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) + struct SMMUState { /* */ SysBusDevice dev; @@ -147,6 +150,9 @@ struct SMMUState { PCIBus *primary_bus; }; +typedef uint32_t GetSidFunc(SMMUDevice *obj); +typedef IOMMUMemoryRegion *GetIommuMr(SMMUState *s, uint32_t sid); + struct SMMUBaseClass { /* */ SysBusDeviceClass parent_class; @@ -154,19 +160,19 @@ struct SMMUBaseClass { /*< public >*/ DeviceRealize parent_realize; + GetSidFunc *get_sid; + GetIommuMr *get_iommu_mr; }; -#define TYPE_ARM_SMMU "arm-smmu" -OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) - /* Return the SMMUPciBus handle associated to a PCI bus number */ SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); /* Return the stream ID of an SMMU device */ -static inline uint16_t smmu_get_sid(SMMUDevice *sdev) +static inline uint32_t smmu_get_sid(SMMUDevice *sdev) { - return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); + SMMUState *s = sdev->smmu; + return ARM_SMMU_GET_CLASS(s)->get_sid(sdev); } /**