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h=From:To:Cc:Subject:Date:From; b=Kw5eMDedqwPd5fm1THu7PwcO6N2aqZ+w3fn9gK7B4R2IELsLRCS6hOiLBJb4BERWY tL1aXBZL9aaQBFDi8On87sq+vbSkMA0yIN+MXeDTZPYrhzpC9R54L5mQlSOsneGgQH I3JRl9P+UbCzC3uktpWG4abMtbsMHrb0mchEMfjSV3zpNWVDr1h+4fDMWKitRS/4bX 6ZnXYggC+f1PrzAg0tdYkDRvV5fjRhmaK6DNZRckNFtlsBGymjZuu6pCveT1h9EDHJ dS/9H5jTc4yz7OcDo4Em3LpHC4kzbByW+m+q//nYEl7y4VvSo9HQzPNLp6BWQL79dp Z0QvsPcxUWvcA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Palmer Dabbelt , Conor Dooley , charlie@rivosinc.com, palmer@dabbelt.com, guoren@kernel.org Subject: [PATCH v3] RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs Date: Fri, 23 Feb 2024 11:31:31 +0000 Message-ID: <20240223-tidings-shabby-607f086cb4d7@spud> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3425; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=0aloUhejevM2QGLo+D0YdTrhD45VzCfjr27GffhjM90=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKk3moS2vBC8Ki31e0rBh1DXO8IBp5ctyJ+8SzDFY7a8z gNDi/MKHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIXisjwwKNNVoOMsY5Cb0B V36vLTZ8cOlnunjXs2md7o/iJ1zY+4+RYUuu8NWf3Xs/Vtf0Bix5NGfaQ/OwF+3hiYz+DVMe6q2 dwgIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240223_113150_498891_A0867E18 X-CRM114-Status: GOOD ( 16.15 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Palmer Dabbelt Before attempting to support the pre-ratification version of vector found on older T-Head CPUs, disallow "v" in riscv,isa on these platforms. The deprecated property has no clear way to communicate the specific version of vector that is supported and much of the vendor provided software puts "v" in the isa string. riscv,isa-extensions should be used instead. This should not be too much of a burden for these systems, as the vendor shipped devicetrees and firmware do not work with a mainline kernel and will require updating. We can limit this restriction to only ignore v in riscv,isa on CPUs that report T-Head's vendor ID and a zero marchid. Newer T-Head CPUs that support the ratified version of vector should report non-zero marchid, according to Guo Ren [1]. Link: https://lore.kernel.org/linux-riscv/CAJF2gTRy5eK73=d6s7CVy9m9pB8p4rAoMHM3cZFwzg=AuF7TDA@mail.gmail.com/ [1] Fixes: dc6667a4e7e3 ("riscv: Extending cpufeature.c to detect V-extension") Signed-off-by: Palmer Dabbelt Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Acked-by: Guo Ren --- I'd forgotten about this patch, the plan had been to sit on it until someone actually reported encountering this, but Palmer asked me to resend this as part of reviving the attempt to mainline the basic support for vector on these devices. I guess the riscv,isa-extensions support actually landed after the v2 was written, so v3 is less complicated since there's full support for parsing the new property and all we have to do is block V in the !acpi case when parsing riscv,isa now. As Guo Ren suggested, I decreased the size of the hammer further, so that the c908, that does implment the ratified V extension, can set "v" in riscv,isa. Other than that, what changed is just a rebase on top of the changes since July. v2 is in the Link: tag above. cc: charlie@rivosinc.com cc: conor.dooley@microchip.com cc: linux-riscv@lists.infradead.org cc: palmer@dabbelt.com cc: guoren@kernel.org --- arch/riscv/kernel/cpufeature.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..3a05af7be510 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "copy-unaligned.h" @@ -538,6 +539,20 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); } + /* + * "V" in ISA strings is ambiguous in practice: it should mean + * just the standard V-1.0 but vendors aren't well behaved. + * Many vendors with T-Head CPU cores which implement the 0.7.1 + * version of the vector specification put "v" into their DTs. + * CPU cores with the ratified spec will contain non-zero + * marchid. + */ + if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID && + riscv_cached_marchid(cpu) == 0x0) { + this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; + clear_bit(RISCV_ISA_EXT_v, isainfo->isa); + } + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't