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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id cw16-20020a170907161000b00a4306ac853fsm1182007ejd.206.2024.02.25.09.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 09:33:15 -0800 (PST) From: Gabor Juhos Date: Sun, 25 Feb 2024 18:32:54 +0100 Subject: [PATCH 1/3] clk: qcom: gcc-ipq5018: fix 'enable_reg' offset of 'gcc_gmac0_sys_clk' Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240225-gcc-ipq5018-register-fixes-v1-1-3c191404d9f0@gmail.com> References: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> In-Reply-To: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Gokul Sriram Palanisamy , Varadarajan Narayanan , Sricharan Ramabadhran Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The value of the 'enable_reg' field in the 'gcc_gmac0_sys_clk' clock definition seems wrong as it is greater than the 'max_register' value defined in the regmap configuration. Additionally, all other gmac specific branch clock definitions within the driver uses the same value both for the 'enable_reg' and for the 'halt_reg' fields. Due to the lack of documentation the correct value is not known. Looking into the downstream driver does not help either, as that uses the same (presumably wrong) value [1]. Nevertheless, change the 'enable_reg' field of 'gcc_gmac0_sys_clk' to use the value from the 'halt_reg' field so it follows the pattern used in other gmac clock definitions. The change is based on the assumption that the register layout of this clock is the same as the other gmac clocks. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L1889 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov Reviewed-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 4aba47e8700d2..cef9a1e7c9fdb 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -1754,7 +1754,7 @@ static struct clk_branch gcc_gmac0_sys_clk = { .halt_check = BRANCH_HALT_DELAY, .halt_bit = 31, .clkr = { - .enable_reg = 0x683190, + .enable_reg = 0x68190, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_gmac0_sys_clk", From patchwork Sun Feb 25 17:32:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabor Juhos X-Patchwork-Id: 13571007 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 635F018EB3; Sun, 25 Feb 2024 17:33:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708882401; cv=none; b=NAmmV8nPJdJ/C5cMfXXspdXha45tKNqiYXAmPgwO+AugpDHbOEsm9npxsAHGEYZkNRcZca5z+m+eNunIVy8SFL+Vo7dUTslXBwx3tr0Q8PjRORu5euHkaKf2Th5Nj+x4NscBXm/X7kjshoGqC+/LfX81xJFeco7pObK294Hjz2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708882401; c=relaxed/simple; bh=u13Abosjh0ga614pMN+V5dneBLpTZCOLofp1E7MVTPQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gN7uzIb/ZyQB/dnAxKHw9iYx9G7d18pB/4QcgoATw6z5hDkpvOYY7vh6O/UWUCt+iNMlVGsU4kYNJ6q15YnVYZ67xRTSwI2aKmQP9kuTpRNiDuZth85nWUi1qpNNI7G9kx1USgcyl3MCBxTFfiepAGc/utRss7cJJWUwW+laJJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CTSHE6E+; arc=none smtp.client-ip=209.85.208.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CTSHE6E+" Received: by mail-ed1-f47.google.com with SMTP id 4fb4d7f45d1cf-565c6cf4819so986247a12.1; Sun, 25 Feb 2024 09:33:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708882397; x=1709487197; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=u98TGKSGxMD5MBX7AoX+yh5eBYy610WHJxOYWlsyDu8=; b=CTSHE6E+atDbBAaTek/Et+y/D8x+ejXzMM4bzMo9S0tMyo1rxUlQr0Us2By9ICAf/3 ZlC0t8b8gJNcq1G016YErXW07hBumDA/jNhKTHQp5NGRqJQusQaSC1iAt7cNJdzVTAF8 ft2EvOaDcRhP+xNElCtxiPbc4lYQfDw4RYCf48A1Vdzatd8Nr52YYMtLTIm98E1oqhaU pxcOaugMva8UMVc88O/T29abmCkMf8GbMHCWXMiIraOkVd9FUCKCOVbDfvNXQbvDhP/k DN8+WDNoychVuiIfLdKMNkWdG2AAC5XbvlVgSVKsgYKYG02Yrjcux/Ag8p2m2T81rht7 X5Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708882397; x=1709487197; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u98TGKSGxMD5MBX7AoX+yh5eBYy610WHJxOYWlsyDu8=; b=gsAVjBOaS61gIezdigNWIM1WwOeER49KjsB9UAESPos3gVLgcyO/A55qjkDSccbrN0 YT4C8EQdXfrafb/PaGlJL4WlgEo92/Ua9qyoIXpkH43GiiWUl0Dpgq5raX7n+c5qRZSm Bij9FwkRhVIrCU/47aZLD54Nd+7DAKo7IHT0foy0fEZmN3+JlIXfFk5CYoQNZTjpy4DB G0T5JrbQpKN0fclxRqNCHVm/ApFw1ETPvK2GeDGLWrj+IMqJdTTXUyGfKsWk5wOhYpbm nVfeizWDJpx+V3ezcYa1j1AUlwfYkll7E1+sYB/dPFJ6hMwdLpRe+pDDr3jv1YfeYpPr o3Ug== X-Forwarded-Encrypted: i=1; AJvYcCX8oumgwBicj7IjtKz2Lj1d7VgVn4PZd4S+WnQY8UTSSYpCMyFbPHn1ml22rHjluhLsi5OXh6wtXgwPQVFSbbdX/3itVAvMtnUzJUlJ+eGo744ICEIPC1Vu8LlbohNdnBnMXIO3PAAy X-Gm-Message-State: AOJu0YwpF+PfL035sCocdDvziXOqs99jfXBKY1nfnRz+BYmgmllpAudq ckaseaDh+eoj61WeteRxzyNZeO75nsjgtgi2d7UBQQhByCHGXZv2 X-Google-Smtp-Source: AGHT+IF9xvmeRkngW8HgN9QJ8ja1/uQuYQMA3p+UHNLddikjuLZBWi9qZwv/pr+xVo9KTAeZAdQ17w== X-Received: by 2002:a17:906:918:b0:a3f:ae09:5f8a with SMTP id i24-20020a170906091800b00a3fae095f8amr4367654ejd.14.1708882397499; Sun, 25 Feb 2024 09:33:17 -0800 (PST) Received: from [192.168.20.102] (57657817.catv.pool.telekom.hu. [87.101.120.23]) by smtp.googlemail.com with ESMTPSA id cw16-20020a170907161000b00a4306ac853fsm1182007ejd.206.2024.02.25.09.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 09:33:16 -0800 (PST) From: Gabor Juhos Date: Sun, 25 Feb 2024 18:32:55 +0100 Subject: [PATCH 2/3] clk: qcom: gcc-ipq5018: fix 'halt_reg' offset of 'gcc_pcie1_pipe_clk' Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240225-gcc-ipq5018-register-fixes-v1-2-3c191404d9f0@gmail.com> References: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> In-Reply-To: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Gokul Sriram Palanisamy , Varadarajan Narayanan , Sricharan Ramabadhran Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The following table shows the values of the 'halt_reg' and the 'enable_reg' fields from the pcie clocks defined in the current driver: clock halt_reg enable_reg gcc_pcie0_ahb_clk 0x75010 0x75010 gcc_pcie0_aux_clk 0x75014 0x75014 gcc_pcie0_axi_m_clk 0x75008 0x75008 gcc_pcie0_axi_s_bridge_clk 0x75048 0x75048 gcc_pcie0_axi_s_clk 0x7500c 0x7500c gcc_pcie0_pipe_clk 0x75018 0x75018 gcc_pcie1_ahb_clk 0x76010 0x76010 gcc_pcie1_aux_clk 0x76014 0x76014 gcc_pcie1_axi_m_clk 0x76008 0x76008 gcc_pcie1_axi_s_bridge_clk 0x76048 0x76048 gcc_pcie1_axi_s_clk 0x7600c 0x7600c gcc_pcie1_pipe_clk 8* 0x76018 Based on the table, it is quite likely that the pcie0 and the pci1 clocks are using the same register layout, however it seems that the value of the 'halt_reg' field in the 'gcc_pcie1_pipe_clk' clock is wrong. In the downstream driver [1], the same '0x76018' value is used for both the 'halt_reg' and for the 'enable_reg' fields of the 'gcc_pcie1_pipe_clk' clock. Update the current driver to use the same value used downstream as probably that is the correct value. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L2316 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov Reviewed-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index cef9a1e7c9fdb..5e81cfa77293a 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -2180,7 +2180,7 @@ static struct clk_branch gcc_pcie1_axi_s_clk = { }; static struct clk_branch gcc_pcie1_pipe_clk = { - .halt_reg = 8, + .halt_reg = 0x76018, .halt_check = BRANCH_HALT_DELAY, .halt_bit = 31, .clkr = { From patchwork Sun Feb 25 17:32:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabor Juhos X-Patchwork-Id: 13571008 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBBB01B81D; Sun, 25 Feb 2024 17:33:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708882402; cv=none; b=VGEboWjzsJwU7M2MR5EfaOk3s/9ciYElMwQCqspDiQsNkTgjSScFBmTkoz4sj+lmt2DHjrR8U1KJvnYrMVS36edI2tqCmJQej5WtNI+86hOQI3qDJPyeQCNi723JhRmG8c18aW3MlhFzanwErTJZfgI1gZsmMXL+kVYPs486hsw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708882402; c=relaxed/simple; bh=INmmxuDp3cZ7nvFnkIiCImfSB4wWRoqAPhib6ZOQFDk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mV/57h68H+/6ARdaTolcpymaHHdo/1qi0sffQ9tnHanZ/5VP96w9VJnsyYTdCjAfJZwu5rB2nyfYyHRt7BpIBgFLUouL9Z71My8H7A6uSSr1OD4Y+iZr3hhdr9h7mKAhnVMTHOvW+tGMN5Y6CSilOMF8Ad/NYRxhPrriTJiOZH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Mz9RBH2y; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Mz9RBH2y" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-563f675be29so2240692a12.0; Sun, 25 Feb 2024 09:33:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1708882399; x=1709487199; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vTMU7fFyDVEAl7ngOGbrGMHQBoOhZMAo5bweFW6SN0g=; b=Mz9RBH2yax8ghyg+Gbb7AM4WSsunRkqQrYFpYmcysSljlbHvnzBZs9hA3NNtyqZfZi qryhwsPV96geoXS7FRFYm4Iu8ZyM2G2rfSrw5Cea/ORCoFMNOlzdcuxGZFUqH+kAnZMp 9yYgKgLmfBQeM/LCPJ5jWXoEX7occTpmjpw5pJJsTV6XMA3d6Y/KDOAQbBmA2YM0/E0y WEMxih8E2lpjvNZdQtORuloKFNNjhOm9P0xDOhTBiu2CpjFVbk0cLgSxEy8HpSsRMhSd NJJzoK4Mv/a+5/F0bd/LYmNVxx2Otqdb2r4HMrsjzooP6OGetz4Yxm67r1cnNCXLrlCc e+Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708882399; x=1709487199; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vTMU7fFyDVEAl7ngOGbrGMHQBoOhZMAo5bweFW6SN0g=; b=juUN9VryHntA33uG1XIwd7y8YO1OH7eFkZxJeR2PA8BQ+dqOEff7sgLFydTrHJ2y2Z n5jZhlgCNpGw1SwlhtzaGY/YCQJ+j0pW9ajfSgzvQXDK4CVqE5UMF805mMHKeb3vuECf bPUgW1N+Bo+svdCCheMa0qmVfac/YCxcDZlmHWjD6gtYkJRmpOpCzeV2JqoNY/QcR6/4 laNQBZ9kzhQKDHifqXaVqP6aaUk3D3CV2BZdMIfWez8TFfYQ5NTFjEo6Oc0g44G3/T77 DmT7AMfwquKbgzdfNLuQYb0sSunChtwUfWyC6b3O1rnhx42XLDCjFZKTmq69lrElR53Z harA== X-Forwarded-Encrypted: i=1; AJvYcCW2wQtjVuYNSyxvVLtPO/AXpp/PntHqHGLLXeBHJQCg56r34KmXlhm3cqMR7NpPJ0zXF7bd0iZ60xjGXKJGzvpCYk2Tpzg7OTsVmKuvncqRCOYGz4U/zAQ9ktiZ1uigcpYSaFUPsQ7S X-Gm-Message-State: AOJu0YyT0uQw1N71G9sFsJ/qHzz6KrYxgvlvgVDWBadvXSAn+HEUMwjK GHcSfi1M0oHYIB88Gidrzjy+Ac5ELlxXkJrh4BWXy4gfB6xzTzNu93THlHFOM88= X-Google-Smtp-Source: AGHT+IGn12BKwQjq/ATn5nMB6OP8QGv/a73XT8HyNqL84j2OZ8Qo6zibPGlR26E0RiE6ilwquduFjQ== X-Received: by 2002:a17:906:6701:b0:a3f:6717:37ae with SMTP id a1-20020a170906670100b00a3f671737aemr3422585ejp.69.1708882399029; Sun, 25 Feb 2024 09:33:19 -0800 (PST) Received: from [192.168.20.102] (57657817.catv.pool.telekom.hu. [87.101.120.23]) by smtp.googlemail.com with ESMTPSA id cw16-20020a170907161000b00a4306ac853fsm1182007ejd.206.2024.02.25.09.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Feb 2024 09:33:18 -0800 (PST) From: Gabor Juhos Date: Sun, 25 Feb 2024 18:32:56 +0100 Subject: [PATCH 3/3] clk: qcom: gcc-ipq5018: fix register offset for GCC_UBI0_AXI_ARES reset Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240225-gcc-ipq5018-register-fixes-v1-3-3c191404d9f0@gmail.com> References: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> In-Reply-To: <20240225-gcc-ipq5018-register-fixes-v1-0-3c191404d9f0@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Gokul Sriram Palanisamy , Varadarajan Narayanan , Sricharan Ramabadhran Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The current register offset used for the GCC_UBI0_AXI_ARES reset seems wrong. Or at least, the downstream driver uses [1] the same offset which is used for other the GCC_UBI0_*_ARES resets. Change the code to use the same offset used in the downstream driver and also specify the reset bit explicitly to use the same format as the followup entries. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov Reviewed-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 5e81cfa77293a..e2bd54826a4ce 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3632,7 +3632,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, [GCC_TCSR_BCR] = { 0x28000, 0 }, [GCC_TLMM_BCR] = { 0x34000, 0 }, - [GCC_UBI0_AXI_ARES] = { 0x680}, + [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },