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Do below changes to pass dtb_binding check: - Remove dma-coherent and fsl,pcie-scfg because not every SOC need it. - Set unevaluatedProperties to true in fsl,layerscape-pcie.yaml. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 87 +++++++++++++ .../bindings/pci/fsl,layerscape-pcie.yaml | 121 ++++++++++++++++++ .../bindings/pci/layerscape-pci.txt | 79 ------------ 3 files changed, 208 insertions(+), 79 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml new file mode 100644 index 0000000000000..cf517e4e46a33 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + items: + - enum: + - fsl,ls1028a-pcie-ep + - fsl,ls2046a-pcie-ep + - fsl,ls2088a-pcie-ep + - fsl,ls1046a-pcie-ep + - fsl,ls1043a-pcie-ep + - fsl,ls1012a-pcie-ep + - fsl,lx2160ar2-pcie-ep + - const: fsl,ls-pcie-ep + + reg: + description: base addresses and lengths of the PCIe controller register blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-names + diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml new file mode 100644 index 0000000000000..3f2d058701d22 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + and thus inherits all the common properties defined in snps,dw-pcie.yaml. + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + enum: + - fsl,ls1021a-pcie + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1088a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + - fsl,ls1028a-pcie + - fsl,lx2160a-pcie + + reg: + description: base addresses and lengths of the PCIe controller register blocks. + + interrupts: + description: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + + interrupt-names: + minItems: 1 + maxItems: 3 + description: It could include the following entries. + items: + oneOf: + - description: + Used for interrupt line which reports AER events when + non MSI/MSI-X/INTx mode is used. + const: aer + - description: + Used for interrupt line which reports PME events when + non MSI/MSI-X/INTx mode is used. + const: pme + - description: + Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) + which has a single interrupt line for miscellaneous controller + events(could include AER and PME events). + const: intr + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: Must include two entries. + The first entry must be a link to the SCFG device node + The second entry is the physical PCIe controller index starting from '0'. + This is used to get SCFG PEXN registers + + dma-coherent: + description: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + +unevaluatedProperties: true + +required: + - compatible + - reg + - interrupt-names + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index ee8a4791a78b4..0000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,79 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller version -information. - -Required properties: -- compatible: should contain the platform identifier such as: - RC mode: - "fsl,ls1021a-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1043a-pcie" - "fsl,ls1012a-pcie" - "fsl,ls1028a-pcie" - EP mode: - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: It could include the following entries: - "aer": Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used - "pme": Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry is the physical PCIe controller index starting from '0'. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Optional properties: -- big-endian: If the PEX_LUT and PF register block is in big-endian, specify - this property. - -Example: - - pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 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Fri, 1 Mar 2024 16:28:04 +0000 From: Frank Li To: conor@kernel.org Cc: Frank.Li@nxp.com, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, helgaas@kernel.org, imx@lists.linux.dev, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, robh@kernel.org Subject: [PATCH v6 2/3] dt-bindings: pci: layerscape-pci: Add snps,dw-pcie.yaml reference Date: Fri, 1 Mar 2024 11:27:40 -0500 Message-Id: <20240301162741.765524-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240301162741.765524-1-Frank.Li@nxp.com> References: <20240301162741.765524-1-Frank.Li@nxp.com> X-ClientProxiedBy: SJ0PR03CA0388.namprd03.prod.outlook.com (2603:10b6:a03:3a1::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DBBPR04MB7865:EE_ X-MS-Office365-Filtering-Correlation-Id: fb7081b4-ebfb-457e-d4a6-08dc3a0c922b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Clean up all context that already exist in snps,dw-pcie.yaml. Update interrupt-names requirement for difference compatible string. Set 'unevaluatedProperties' back to 'false'. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie.yaml | 104 +++++++++++++----- 1 file changed, 78 insertions(+), 26 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml index 3f2d058701d22..137cc17933a4b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -11,7 +11,6 @@ maintainers: description: This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. @@ -36,31 +35,18 @@ properties: - fsl,lx2160a-pcie reg: - description: base addresses and lengths of the PCIe controller register blocks. + maxItems: 2 + + reg-names: + maxItems: 2 interrupts: - description: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -69,23 +55,88 @@ properties: The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: - description: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly + dma-coherent: true + + msi-parent: true + + iommu-map: true big-endian: $ref: /schemas/types.yaml#/definitions/flag description: If the PEX_LUT and PF register block is in big-endian, specify this property. -unevaluatedProperties: true +unevaluatedProperties: false required: - compatible - reg - interrupt-names +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - if: + properties: + compatible: + enum: + - fsl,lx2160a-pcie + then: + properties: + interrupts: + maxItems: 3 + interrupt-names: + items: + - const: pme + - const: aer + - const: intr + + - if: + properties: + compatible: + enum: + - fsl,ls1028a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: pme + - const: aer + + - if: + properties: + compatible: + enum: + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1021a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: intr + + - if: + properties: + compatible: + enum: + - fsl,ls1088a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: aer + examples: - | #include @@ -98,7 +149,7 @@ examples: compatible = "fsl,ls1088a-pcie"; reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; + reg-names = "dbi", "config"; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ interrupt-names = "aer"; #address-cells = <3>; @@ -116,6 +167,7 @@ examples: <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + msi-map = <0 &its 0 1>; /* Fixed-up by bootloader */ }; }; ... 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Remove context that exist in snps,dw-pcie-ep.yaml. Add an example for pcie-ep. Signed-off-by: Frank Li --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 54 ++++++++++--------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml index cf517e4e46a33..07965683beece 100644 --- a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -10,8 +10,7 @@ maintainers: - Frank Li description: - This PCIe RC controller is based on the Synopsys DesignWare PCIe IP - and thus inherits all the common properties defined in snps,dw-pcie.yaml. + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP. This controller derives its clocks from the Reset Configuration Word (RCW) which is used to describe the PLL settings at the time of chip-reset. @@ -35,31 +34,18 @@ properties: - const: fsl,ls-pcie-ep reg: - description: base addresses and lengths of the PCIe controller register blocks. + maxItems: 2 + + reg-names: + maxItems: 2 interrupts: - description: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. + minItems: 1 + maxItems: 3 interrupt-names: minItems: 1 maxItems: 3 - description: It could include the following entries. - items: - oneOf: - - description: - Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used. - const: aer - - description: - Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used. - const: pme - - description: - Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). - const: intr fsl,pcie-scfg: $ref: /schemas/types.yaml#/definitions/phandle @@ -68,10 +54,7 @@ properties: The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: - description: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly + dma-coherent: true big-endian: $ref: /schemas/types.yaml#/definitions/flag @@ -85,3 +68,24 @@ required: - reg - interrupt-names +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "dbi", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "app"; + }; + }; +...