From patchwork Mon Mar 4 20:25:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581186 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EECE7AE75; Mon, 4 Mar 2024 20:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583947; cv=fail; b=QoFInEwIytbEoQpmM+PJbcdPvivbHCdugNt7bUCR4VHgt4mxgdnvg273761Lsp8N5McZeXEu5dBpwTTPUwegj+MZ/FRsxzGu22v2GkJd2RT3xlhsruaELiVCiFqvpsOkBmK0JdM5OTRB+nOHucLmHAs4mcsHowJUDFTHsDCS5mI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583947; c=relaxed/simple; bh=8Hb5H4vKR0NdWcesuU43bjOBcLuppR7GFSBarkVTO54=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=FcB/aFYrlX3j9CAb4s/uT/8IwME+iH7TD9dkL8GJEQ6Oe6e1AJzVytQhIbYXv9l4iX1Y+WOM3qLgtOJ6i+zFMMHuWkgH8J/SJ27vp5bfyav/RKmrwS7jQi/vamin1usxbWcKE9/9gCa2R5f2VxHosSvYleWf14HBxwjajqxS0+o= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=b8WXU1Gr; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="b8WXU1Gr" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bJlfTx3NDJh49MHK2olkT7bUYvXljGODYdSp6zYxRqghCGcc6x2l4MITzdDtJKO1KwXSvsDg4+2pJrj/F6H7ev5/2phJ29hJEsVS83tf3E9Dk899JjBDshojOgVbC5B1Dvfom1GwSKMZwF0BQ/deZLcNq/qQqMDjwtVvElGPvUFeFpB+sZpommcOgNCM185YFPRCNayA8gRVaGN41zVgPd7JjCP/KpGI1xPeGit6IjcUIr/VZIXymNT2j9Hz0VB9LWa1tDxeAmTO9hmd0wcimPVDxMy+3p3I/2AHxqRfYr3DIlNyeQMIb5qZNu1i+1rCzly/axkkcUsGraG0fdw0IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1bsOd5bZlzmjRcAY9umW8miaTRo9tpipw/T4Uh3Ro+c=; b=XvX/74xFAf5UgtQ4W2Vav4fpd2qq/cN49ddJakGyQ4p3KK5XA5OWt9A5/84gsFBF9Taf7Hrfa9nM4etQ4NeWwDtxgDayKEK2IPtDzoGL8GrRqQW9tF8XjjE47AI7kHXmnNXFbMlI41c4fX034umeF+VIjhRU09HnswBiH3Nf8F2KCT6/WrC20H144T43gAhnm3RXvlJOnzrg2xcuiCWdQwfpwgR4QcZtiQ05lya+n4HHqL8Di8fl9+pRoD8MFpmEX4wIgc0z7VvYk1kIlBwgpWH0PDXeWQLaSqZblPdvThwXAtJtyln3v++HrQ88ISkVbMbzD7OXK1nipMmrXnAS3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1bsOd5bZlzmjRcAY9umW8miaTRo9tpipw/T4Uh3Ro+c=; b=b8WXU1GrEsdPNt7d9b02YJJrzHE/6yf4Z5r5AN8z0sijugIc14cOQXurErNa2CFXVTGjHTnFye0nFs9hvHzJNAby34rgEKNaP0AGCxgiLXUAM5DmBfvRY7ZPOSPSkdWpN19Pa+4qs6fH39dA1tX/0slclB8WUIkH0/97e+YCtT4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:39 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:39 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:06 -0500 Subject: [PATCH v2 1/6] PCI: imx6: Rename imx6_* with imx_* Message-Id: <20240304-pci2_upstream-v2-1-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583932; l=59482; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=8Hb5H4vKR0NdWcesuU43bjOBcLuppR7GFSBarkVTO54=; b=Xp7iO+pCnewmKXkbmxwNrktY0Vmc8IxotatuAO0q7aF934d2I1ONAnbs8qvlPbyqMdnK2OFir j/VA82ArFD/BWZ7W/ebc9vYRkHxUFbN6Did5sWZsQC9joO75h5i161s X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: e31a1fa4-2ebc-4275-768b-08dc3c8941b3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ruSuP1RkRMpD+hw8vc+jbTAJlDI6rNBmjynsfOMtZ6yt0w5L+dr7oSpjMWZxGZtwJlBZjqLZ6bSvzmCyPXSd3opup5+ZznpLe1/MCe+8YWAn6k5NIFaTnsXOumMauVukC7xu9x1/mySsyuE7Pdjh9YaYthqec/WSI9EcinuUZttYPpt9VfkcXNTdN9p1XoRIYgafRwS0yJSiCo21puQgh8G6c/y2BjI/1Wkrc1q8LCw+LNhqhrHoiqkA6OLAZT3LXNQ5uLT/jiRvDwrxV2TnvEYdTuZYQtZuRMOAzDvNsWWF3ug4ExZ0ChZULHPLdHC8PzPp7mhL3EnP+0GBmG11kUrtz0TKlQzVHwki3F82tNtonGhm5Xpcd5kJQ8M2JqrepXB8w3xwthOvPq3tgq+YYvp+DQ1xXfYvAirNGSuYx7/m1ZY/cshzbhZqJpt2SD2FsRWMNk8wM4vXIDaSQqteZ4PmXYLLDp+tMtm0VMcLc6pacswIwry6xXovPQGdJk0ALqM2pK1uw5UR6jF/wcQfeKOCj1JaLv5R+Vrs7mzB7p/P1ISlnKU2W5kq7w54kkJmEhHr2p/OMX3/zh9MCYFUziqoHUnlfACKCMFtrzssOHUMZ9yEeEYgd360Nd2+2RunSg3Rg+us69ipdxJZOQxRcKGDqsRQ08+AXTg0FDiQcTFxjmhMfJTce7FDW2GL0QBqqzPbg6i+rDgLdAtQe6GKykyA0rUZo6Fuo1C7wABSiEA= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?7HywWglZ9E5y+GCHw0FcJ2qyLvDG?= =?utf-8?q?rpfLjrW2KGvd4dj3Y03uDJnehHG9eRUMqdt7Pu1BEVJzpQgPcATpb794TqPaNJmLV?= =?utf-8?q?0KFaIzbf+svYnLhMROgKSi9nhfcobHj/jymJ6YrDyJ5d7CSuIgDC16J3gu3fDViYP?= =?utf-8?q?4rTGnLTYIMhbBcd94uCiBsw9lBx8yB/adZ0dGugWedYelPKXpbbnPYIpB8N3jTFwV?= =?utf-8?q?UNLgZvS+yMxbXpemoHhv9iCTSAUU7i60QscjRxAmVUVcyzGTEyY7+oJ9TCFiNrrmQ?= =?utf-8?q?lne41UO6ccQuVk6+h73S4lxyFY+AW4mkYDk4O4NqkW4q6XGdGJqJtsf4GQL5AvWOn?= =?utf-8?q?KWTvk6QEBqTpGVEvHSlo9+NE895c+UlmXMOFUNzv42Ef7/TsTm/fKnGCDOhPTBF0X?= =?utf-8?q?1NZcfbqhNgILXczMy++cH8r2YjIwFt2ZmQjwJAwdIDM/eA1qTNOrJ+ve6UCB1vOFi?= =?utf-8?q?PnGEUywo8+LzXn2kxv0P03gCknm4Az+/DUxf57Kjrl5LBngHV3vjO52tOvelTNiAB?= =?utf-8?q?F7zW0U2zDS6l3BI03k6Z9Kn2yJFmq25I5vyKyvqDX6fkHsQhlDslS+jir0VmWoF/s?= =?utf-8?q?8whLh+zKctnzjiCrY5RBfKIndw8FlolD7QFTC4vJlgmTdrddDlYLroDc80a8fbIYQ?= =?utf-8?q?hFVKOHCqNieHsFKNrZFO0bOF9O8ICTMNsJd+fH8ByL/iVG/uA7PBuhw3xxO1Yc8cJ?= =?utf-8?q?YI9dSw60AAnQUkpLoOdYvUvlb888+O414Jshb4DSf5ITkn19iyoj4/CyULOdf8m8v?= =?utf-8?q?GoDDyDPk4Od39vvk8UQ9TbgBjOFg27IEjNoccfwTbZPnFWagBF+j7NWx0/GOR7w98?= =?utf-8?q?fIEA82W9m6dWDR+zc+3MpS/HkHHwPlWRk9ikqB3fwDZCA1bP3aG0BmB+0Xh5T5R8e?= =?utf-8?q?zuQs+I0BBCxIGKbzwrSWcWU32Jwytp/4Qj5pCh5Zd9X8c5dbBaSTZIqVlVcfG+alO?= =?utf-8?q?8NajkQ1So0GuZ+Ls06yHgLxJ/0FTgq1qyBBsJtgAJiVHzxPpbQWyUVS99rsBzXAub?= =?utf-8?q?g2X1EEXSlXnpoW4TNBOIh5hnvxMyLoB1kJsux08xmVcCrWoFycnd4UX6GiRSsyeJh?= =?utf-8?q?pOqevENgz5qPz/zAxY+7T0z0mypKyUMcfIy4DgJEaVf4vzMBNgfIAo03c217k2Q0K?= =?utf-8?q?gyvBrrRq9sMQDfZ37/lywPGfsksb0U4tp7jGZ7PSL+nu3/ev+O855Bvexr+0CoopD?= =?utf-8?q?vFu8fT7z0xaoPc079EEnt6c+V5wiZwuHDRrzRCe8a/TNPRUvCJ4o2YFuaYj+pu76+?= =?utf-8?q?L/AAblv0sZlEtx51MZS4PuKP3Ur+rBqPiPBWa15lINl/0vhoImspGxrmqh2P/LOdX?= =?utf-8?q?N6IyGj282cTcvTSZuY66o5XvAIH6yB12Rfq6XPS4IFO7snf9oQ9kHEuySLqj4xbpd?= =?utf-8?q?ZmMKYFfkDRDz61lNu+vKdwk+fbPxTNkaFP4U4HLVuE40R8FdLrNRxdy2iN8rp3F+Z?= =?utf-8?q?mG7pyb4S2ZJCVV83fnFSLVch42Okszw59BuV/OF4e/DqDmQBMkm/ulWprxjVWGKqi?= =?utf-8?q?ERH9YZqt7aNV?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e31a1fa4-2ebc-4275-768b-08dc3c8941b3 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:39.2545 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6FhcjqzMjrVqhfi7OL9OWphyKfUUZOcCX8ZDRpVBiE89pXJprDj6fxa2r0sOFiqSuWvK7jBCCfROSa23qFB5kg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 imx6_* actually mean for all imx chips (imx6x, imx7x, imx8x and imx9x). Rename imx6_* with imx_* to avoid confuse. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pci-imx6.c | 754 +++++++++++++++++----------------- 1 file changed, 377 insertions(+), 377 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 99a60270b26cd..4aa5f054d91c8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,9 +55,9 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) -#define to_imx6_pcie(x) dev_get_drvdata((x)->dev) +#define to_imx_pcie(x) dev_get_drvdata((x)->dev) -enum imx6_pcie_variants { +enum imx_pcie_variants { IMX6Q, IMX6SX, IMX6QP, @@ -72,25 +72,25 @@ enum imx6_pcie_variants { IMX95_EP, }; -#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) -#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1) -#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) -#define IMX6_PCIE_FLAG_HAS_PHYDRV BIT(3) -#define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) -#define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) -#define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) -#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_IMX_PHY BIT(0) +#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1) +#define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) +#define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) +#define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) +#define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) +#define IMX_PCIE_FLAG_HAS_SERDES BIT(6) +#define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) -#define imx6_check_flag(pci, val) (pci->drvdata->flags & val) +#define imx_check_flag(pci, val) (pci->drvdata->flags & val) -#define IMX6_PCIE_MAX_CLKS 6 +#define IMX_PCIE_MAX_CLKS 6 -#define IMX6_PCIE_MAX_INSTANCES 2 +#define IMX_PCIE_MAX_INSTANCES 2 -struct imx6_pcie; +struct imx_pcie; -struct imx6_pcie_drvdata { - enum imx6_pcie_variants variant; +struct imx_pcie_drvdata { + enum imx_pcie_variants variant; enum dw_pcie_device_mode mode; u32 flags; int dbi_length; @@ -99,18 +99,18 @@ struct imx6_pcie_drvdata { const u32 clks_cnt; const u32 ltssm_off; const u32 ltssm_mask; - const u32 mode_off[IMX6_PCIE_MAX_INSTANCES]; - const u32 mode_mask[IMX6_PCIE_MAX_INSTANCES]; + const u32 mode_off[IMX_PCIE_MAX_INSTANCES]; + const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; - int (*init_phy)(struct imx6_pcie *pcie); + int (*init_phy)(struct imx_pcie *pcie); }; -struct imx6_pcie { +struct imx_pcie { struct dw_pcie *pci; int reset_gpio; bool gpio_active_high; bool link_is_up; - struct clk_bulk_data clks[IMX6_PCIE_MAX_CLKS]; + struct clk_bulk_data clks[IMX_PCIE_MAX_CLKS]; struct regmap *iomuxc_gpr; u16 msi_ctrl; u32 controller_id; @@ -131,7 +131,7 @@ struct imx6_pcie { /* power domain for pcie phy */ struct device *pd_pcie_phy; struct phy *phy; - const struct imx6_pcie_drvdata *drvdata; + const struct imx_pcie_drvdata *drvdata; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -186,28 +186,28 @@ struct imx6_pcie { #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3) -static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie) +static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) { - WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ && - imx6_pcie->drvdata->variant != IMX8MQ_EP && - imx6_pcie->drvdata->variant != IMX8MM && - imx6_pcie->drvdata->variant != IMX8MM_EP && - imx6_pcie->drvdata->variant != IMX8MP && - imx6_pcie->drvdata->variant != IMX8MP_EP); - return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; + WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && + imx_pcie->drvdata->variant != IMX8MQ_EP && + imx_pcie->drvdata->variant != IMX8MM && + imx_pcie->drvdata->variant != IMX8MM_EP && + imx_pcie->drvdata->variant != IMX8MP && + imx_pcie->drvdata->variant != IMX8MP_EP); + return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; } -static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_PHY_CR_PARA_SEL, IMX95_PCIE_PHY_CR_PARA_SEL); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL, IMX95_PCIE_REF_USE_PAD, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0, IMX95_PCIE_REF_CLKEN, IMX95_PCIE_REF_CLKEN); @@ -215,9 +215,9 @@ static int imx95_pcie_init_phy(struct imx6_pcie *imx6_pcie) return 0; } -static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) +static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) { - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; unsigned int mask, val, mode, id; if (drvdata->mode == DW_PCIE_EP_TYPE) @@ -225,7 +225,7 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) else mode = PCI_EXP_TYPE_ROOT_PORT; - id = imx6_pcie->controller_id; + id = imx_pcie->controller_id; /* If mode_mask[id] is zero, means each controller have its individual gpr */ if (!drvdata->mode_mask[id]) @@ -234,12 +234,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie) mask = drvdata->mode_mask[id]; val = mode << (ffs(mask) - 1); - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); } -static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) +static int pcie_phy_poll_ack(struct imx_pcie *imx_pcie, bool exp_val) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; bool val; u32 max_iterations = 10; u32 wait_counter = 0; @@ -258,9 +258,9 @@ static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val) return -ETIMEDOUT; } -static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) +static int pcie_phy_wait_ack(struct imx_pcie *imx_pcie, int addr) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 val; int ret; @@ -270,24 +270,24 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) val |= PCIE_PHY_CTRL_CAP_ADR; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; val = PCIE_PHY_CTRL_DATA(addr); dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ -static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) +static int pcie_phy_read(struct imx_pcie *imx_pcie, int addr, u16 *data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 phy_ctl; int ret; - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -295,7 +295,7 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) phy_ctl = PCIE_PHY_CTRL_RD; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -304,18 +304,18 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data) /* deassert Read signal */ dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); - return pcie_phy_poll_ack(imx6_pcie, false); + return pcie_phy_poll_ack(imx_pcie, false); } -static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) +static int pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; u32 var; int ret; /* write addr */ /* cap addr */ - ret = pcie_phy_wait_ack(imx6_pcie, addr); + ret = pcie_phy_wait_ack(imx_pcie, addr); if (ret) return ret; @@ -326,7 +326,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) var |= PCIE_PHY_CTRL_CAP_DAT; dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -335,7 +335,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -344,7 +344,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack */ - ret = pcie_phy_poll_ack(imx6_pcie, true); + ret = pcie_phy_poll_ack(imx_pcie, true); if (ret) return ret; @@ -353,7 +353,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); /* wait for ack de-assertion */ - ret = pcie_phy_poll_ack(imx6_pcie, false); + ret = pcie_phy_poll_ack(imx_pcie, false); if (ret) return ret; @@ -362,74 +362,74 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data) return 0; } -static int imx8mq_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx8mq_pcie_init_phy(struct imx_pcie *imx_pcie) { /* TODO: Currently this code assumes external oscillator is being used */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_REF_USE_PAD, IMX8MQ_GPR_PCIE_REF_USE_PAD); /* * Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is * supplied by 3.3V, the VREG_BYPASS should be cleared to zero. */ - if (imx6_pcie->vph && regulator_get_voltage(imx6_pcie->vph) > 3000000) - regmap_update_bits(imx6_pcie->iomuxc_gpr, - imx6_pcie_grp_offset(imx6_pcie), + if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) + regmap_update_bits(imx_pcie->iomuxc_gpr, + imx_pcie_grp_offset(imx_pcie), IMX8MQ_GPR_PCIE_VREG_BYPASS, 0); return 0; } -static int imx7d_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx7d_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); return 0; } -static int imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); /* configure constant input signal to the pcie ctrl and phy */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_LOS_LEVEL, 9 << 4); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN1, - imx6_pcie->tx_deemph_gen1 << 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, - imx6_pcie->tx_deemph_gen2_3p5db << 6); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, - imx6_pcie->tx_deemph_gen2_6db << 12); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_FULL, - imx6_pcie->tx_swing_full << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, + imx_pcie->tx_swing_full << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, IMX6Q_GPR8_TX_SWING_LOW, - imx6_pcie->tx_swing_low << 25); + imx_pcie->tx_swing_low << 25); return 0; } -static int imx6sx_pcie_init_phy(struct imx6_pcie *imx6_pcie) +static int imx6sx_pcie_init_phy(struct imx_pcie *imx_pcie) { - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_RX_EQ_MASK, IMX6SX_GPR12_PCIE_RX_EQ_2); - return imx6_pcie_init_phy(imx6_pcie); + return imx_pcie_init_phy(imx_pcie); } -static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) +static void imx7d_pcie_wait_for_phy_pll_lock(struct imx_pcie *imx_pcie) { u32 val; - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; - if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, + if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, IOMUXC_GPR22, val, val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED, PHY_PLL_LOCK_WAIT_USLEEP_MAX, @@ -437,19 +437,19 @@ static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie) dev_err(dev, "PCIe PLL lock timeout\n"); } -static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) +static int imx_setup_phy_mpll(struct imx_pcie *imx_pcie) { unsigned long phy_rate = 0; int mult, div; u16 val; int i; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return 0; - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - if (strncmp(imx6_pcie->clks[i].id, "pcie_phy", 8) == 0) - phy_rate = clk_get_rate(imx6_pcie->clks[i].clk); + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + if (strncmp(imx_pcie->clks[i].id, "pcie_phy", 8) == 0) + phy_rate = clk_get_rate(imx_pcie->clks[i].clk); switch (phy_rate) { case 125000000: @@ -467,46 +467,46 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie) div = 1; break; default: - dev_err(imx6_pcie->pci->dev, + dev_err(imx_pcie->pci->dev, "Unsupported PHY reference clock rate %lu\n", phy_rate); return -EINVAL; } - pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val); val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK << PCIE_PHY_MPLL_MULTIPLIER_SHIFT); val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT; val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD; - pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); + pcie_phy_write(imx_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val); - pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val); + pcie_phy_read(imx_pcie, PCIE_PHY_ATEOVRD, &val); val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT); val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT; val |= PCIE_PHY_ATEOVRD_EN; - pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val); + pcie_phy_write(imx_pcie, PCIE_PHY_ATEOVRD, val); return 0; } -static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) +static void imx_pcie_reset_phy(struct imx_pcie *imx_pcie) { u16 tmp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) return; - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); usleep_range(2000, 3000); - pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); + pcie_phy_read(imx_pcie, PHY_RX_OVRD_IN_LO, &tmp); tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | PHY_RX_OVRD_IN_LO_RX_PLL_EN); - pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); + pcie_phy_write(imx_pcie, PHY_RX_OVRD_IN_LO, tmp); } #ifdef CONFIG_ARM @@ -545,22 +545,22 @@ static int imx6q_pcie_abort_handler(unsigned long addr, } #endif -static int imx6_pcie_attach_pd(struct device *dev) +static int imx_pcie_attach_pd(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); struct device_link *link; /* Do nothing when in a single power domain */ if (dev->pm_domain) return 0; - imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); - if (IS_ERR(imx6_pcie->pd_pcie)) - return PTR_ERR(imx6_pcie->pd_pcie); + imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); + if (IS_ERR(imx_pcie->pd_pcie)) + return PTR_ERR(imx_pcie->pd_pcie); /* Do nothing when power domain missing */ - if (!imx6_pcie->pd_pcie) + if (!imx_pcie->pd_pcie) return 0; - link = device_link_add(dev, imx6_pcie->pd_pcie, + link = device_link_add(dev, imx_pcie->pd_pcie, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -569,11 +569,11 @@ static int imx6_pcie_attach_pd(struct device *dev) return -EINVAL; } - imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); - if (IS_ERR(imx6_pcie->pd_pcie_phy)) - return PTR_ERR(imx6_pcie->pd_pcie_phy); + imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); + if (IS_ERR(imx_pcie->pd_pcie_phy)) + return PTR_ERR(imx_pcie->pd_pcie_phy); - link = device_link_add(dev, imx6_pcie->pd_pcie_phy, + link = device_link_add(dev, imx_pcie->pd_pcie_phy, DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); @@ -585,20 +585,20 @@ static int imx6_pcie_attach_pd(struct device *dev) return 0; } -static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) +static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) { unsigned int offset; int ret = 0; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); break; case IMX6QP: case IMX6Q: /* power up core phy and enable ref clock */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); /* * the async reset input need ref clock to sync internally, @@ -607,7 +607,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) * add one ~10us delay here. */ usleep_range(10, 100); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); break; case IMX7D: @@ -620,15 +620,15 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) case IMX8MQ_EP: case IMX8MP: case IMX8MP_EP: - offset = imx6_pcie_grp_offset(imx6_pcie); + offset = imx_pcie_grp_offset(imx_pcie); /* * Set the over ride low and enabled * make sure that REF_CLK is turned on. */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); break; @@ -637,19 +637,19 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) return ret; } -static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) +static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) { - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6QP: case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); break; case IMX7D: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); break; @@ -658,17 +658,17 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie) } } -static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) +static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; int ret; - ret = clk_bulk_prepare_enable(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = clk_bulk_prepare_enable(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - ret = imx6_pcie_enable_ref_clk(imx6_pcie); + ret = imx_pcie_enable_ref_clk(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie ref clock\n"); goto err_ref_clk; @@ -679,41 +679,41 @@ static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie) return 0; err_ref_clk: - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); return ret; } -static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie) +static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx6_pcie_disable_ref_clk(imx6_pcie); - clk_bulk_disable_unprepare(imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + imx_pcie_disable_ref_clk(imx_pcie); + clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } -static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) +static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { - reset_control_assert(imx6_pcie->pciephy_reset); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->pciephy_reset); + reset_control_assert(imx_pcie->apps_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, IMX6SX_GPR12_PCIE_TEST_POWERDOWN); /* Force PCIe PHY reset */ - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, IMX6SX_GPR5_PCIE_BTNRST_RESET); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, IMX6Q_GPR1_PCIE_SW_RST); break; case IMX6Q: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); break; default: @@ -721,47 +721,47 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) - gpio_set_value_cansleep(imx6_pcie->reset_gpio, - imx6_pcie->gpio_active_high); + if (gpio_is_valid(imx_pcie->reset_gpio)) + gpio_set_value_cansleep(imx_pcie->reset_gpio, + imx_pcie->gpio_active_high); } -static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) +static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; - reset_control_deassert(imx6_pcie->pciephy_reset); + reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX7D: /* Workaround for ERR010728, failure of PCI-e PLL VCO to * oscillate, especially when cold. This turns off "Duty-cycle * Corrector" and other mysterious undocumented things. */ - if (likely(imx6_pcie->phy_base)) { + if (likely(imx_pcie->phy_base)) { /* De-assert DCC_FB_EN */ writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); + imx_pcie->phy_base + PCIE_PHY_CMN_REG4); /* Assert RX_EQS and RX_EQS_SEL */ writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); /* Assert ATT_MODE */ writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); + imx_pcie->phy_base + PCIE_PHY_CMN_REG26); } else { dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); } - imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie); + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); break; case IMX6SX: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); break; case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, 0); usleep_range(200, 500); @@ -771,10 +771,10 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx6_pcie->reset_gpio)) { + if (gpio_is_valid(imx_pcie->reset_gpio)) { msleep(100); - gpio_set_value_cansleep(imx6_pcie->reset_gpio, - !imx6_pcie->gpio_active_high); + gpio_set_value_cansleep(imx_pcie->reset_gpio, + !imx_pcie->gpio_active_high); /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ msleep(100); } @@ -782,9 +782,9 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) return 0; } -static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) +static int imx_pcie_wait_for_speed_change(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct device *dev = pci->dev; u32 tmp; unsigned int retries; @@ -801,33 +801,33 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) return -ETIMEDOUT; } -static void imx6_pcie_ltssm_enable(struct device *dev) +static void imx_pcie_ltssm_enable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, drvdata->ltssm_mask); - reset_control_deassert(imx6_pcie->apps_reset); + reset_control_deassert(imx_pcie->apps_reset); } -static void imx6_pcie_ltssm_disable(struct device *dev) +static void imx_pcie_ltssm_disable(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - const struct imx6_pcie_drvdata *drvdata = imx6_pcie->drvdata; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; if (drvdata->ltssm_mask) - regmap_update_bits(imx6_pcie->iomuxc_gpr, drvdata->ltssm_off, + regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, 0); - reset_control_assert(imx6_pcie->apps_reset); + reset_control_assert(imx_pcie->apps_reset); } -static int imx6_pcie_start_link(struct dw_pcie *pci) +static int imx_pcie_start_link(struct dw_pcie *pci) { - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); struct device *dev = pci->dev; u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 tmp; @@ -846,7 +846,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_dbi_ro_wr_dis(pci); /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); ret = dw_pcie_wait_for_link(pci); if (ret) @@ -869,8 +869,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); dw_pcie_dbi_ro_wr_dis(pci); - if (imx6_pcie->drvdata->flags & - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) { + if (imx_pcie->drvdata->flags & + IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { /* * On i.MX7, DIRECT_SPEED_CHANGE behaves differently * from i.MX6 family when no link speed transition @@ -880,7 +880,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) * failure. */ - ret = imx6_pcie_wait_for_speed_change(imx6_pcie); + ret = imx_pcie_wait_for_speed_change(imx_pcie); if (ret) { dev_err(dev, "Failed to bring link up!\n"); goto err_reset_phy; @@ -895,37 +895,37 @@ static int imx6_pcie_start_link(struct dw_pcie *pci) dev_info(dev, "Link: Only Gen1 is enabled\n"); } - imx6_pcie->link_is_up = true; + imx_pcie->link_is_up = true; tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA); dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS); return 0; err_reset_phy: - imx6_pcie->link_is_up = false; + imx_pcie->link_is_up = false; dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0), dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1)); - imx6_pcie_reset_phy(imx6_pcie); + imx_pcie_reset_phy(imx_pcie); return 0; } -static void imx6_pcie_stop_link(struct dw_pcie *pci) +static void imx_pcie_stop_link(struct dw_pcie *pci) { struct device *dev = pci->dev; /* Turn off PCIe LTSSM */ - imx6_pcie_ltssm_disable(dev); + imx_pcie_ltssm_disable(dev); } -static int imx6_pcie_host_init(struct dw_pcie_rp *pp) +static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct device *dev = pci->dev; - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); int ret; - if (imx6_pcie->vpcie) { - ret = regulator_enable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) { + ret = regulator_enable(imx_pcie->vpcie); if (ret) { dev_err(dev, "failed to enable vpcie regulator: %d\n", ret); @@ -933,83 +933,83 @@ static int imx6_pcie_host_init(struct dw_pcie_rp *pp) } } - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); - if (imx6_pcie->drvdata->init_phy) - imx6_pcie->drvdata->init_phy(imx6_pcie); + if (imx_pcie->drvdata->init_phy) + imx_pcie->drvdata->init_phy(imx_pcie); - imx6_pcie_configure_type(imx6_pcie); + imx_pcie_configure_type(imx_pcie); - ret = imx6_pcie_clk_enable(imx6_pcie); + ret = imx_pcie_clk_enable(imx_pcie); if (ret) { dev_err(dev, "unable to enable pcie clocks: %d\n", ret); goto err_reg_disable; } - if (imx6_pcie->phy) { - ret = phy_init(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_init(imx_pcie->phy); if (ret) { dev_err(dev, "pcie PHY power up failed\n"); goto err_clk_disable; } } - if (imx6_pcie->phy) { - ret = phy_power_on(imx6_pcie->phy); + if (imx_pcie->phy) { + ret = phy_power_on(imx_pcie->phy); if (ret) { dev_err(dev, "waiting for PHY ready timeout!\n"); goto err_phy_off; } } - ret = imx6_pcie_deassert_core_reset(imx6_pcie); + ret = imx_pcie_deassert_core_reset(imx_pcie); if (ret < 0) { dev_err(dev, "pcie deassert core reset failed: %d\n", ret); goto err_phy_off; } - imx6_setup_phy_mpll(imx6_pcie); + imx_setup_phy_mpll(imx_pcie); return 0; err_phy_off: - if (imx6_pcie->phy) - phy_exit(imx6_pcie->phy); + if (imx_pcie->phy) + phy_exit(imx_pcie->phy); err_clk_disable: - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); err_reg_disable: - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); return ret; } -static void imx6_pcie_host_exit(struct dw_pcie_rp *pp) +static void imx_pcie_host_exit(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - if (imx6_pcie->phy) { - if (phy_power_off(imx6_pcie->phy)) + if (imx_pcie->phy) { + if (phy_power_off(imx_pcie->phy)) dev_err(pci->dev, "unable to power off PHY\n"); - phy_exit(imx6_pcie->phy); + phy_exit(imx_pcie->phy); } - imx6_pcie_clk_disable(imx6_pcie); + imx_pcie_clk_disable(imx_pcie); - if (imx6_pcie->vpcie) - regulator_disable(imx6_pcie->vpcie); + if (imx_pcie->vpcie) + regulator_disable(imx_pcie->vpcie); } -static const struct dw_pcie_host_ops imx6_pcie_host_ops = { - .init = imx6_pcie_host_init, - .deinit = imx6_pcie_host_exit, +static const struct dw_pcie_host_ops imx_pcie_host_ops = { + .init = imx_pcie_host_init, + .deinit = imx_pcie_host_exit, }; static const struct dw_pcie_ops dw_pcie_ops = { - .start_link = imx6_pcie_start_link, - .stop_link = imx6_pcie_stop_link, + .start_link = imx_pcie_start_link, + .stop_link = imx_pcie_stop_link, }; -static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) +static void imx_pcie_ep_init(struct dw_pcie_ep *ep) { enum pci_barno bar; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1018,7 +1018,7 @@ static void imx6_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_ep_reset_bar(pci, bar); } -static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, +static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, unsigned int type, u16 interrupt_num) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1065,35 +1065,35 @@ static const struct pci_epc_features imx95_pcie_epc_features = { }; static const struct pci_epc_features* -imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) +imx_pcie_ep_get_features(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); - return imx6_pcie->drvdata->epc_features; + return imx_pcie->drvdata->epc_features; } static const struct dw_pcie_ep_ops pcie_ep_ops = { - .init = imx6_pcie_ep_init, - .raise_irq = imx6_pcie_ep_raise_irq, - .get_features = imx6_pcie_ep_get_features, + .init = imx_pcie_ep_init, + .raise_irq = imx_pcie_ep_raise_irq, + .get_features = imx_pcie_ep_get_features, }; -static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, +static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct platform_device *pdev) { int ret; unsigned int pcie_dbi2_offset; struct dw_pcie_ep *ep; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; struct dw_pcie_rp *pp = &pci->pp; struct device *dev = pci->dev; - imx6_pcie_host_init(pp); + imx_pcie_host_init(pp); ep = &pci->ep; ep->ops = &pcie_ep_ops; - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ_EP: case IMX8MM_EP: case IMX8MP_EP: @@ -1115,7 +1115,7 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, if (device_property_match_string(dev, "reg-names", "dbi2") >= 0) pci->dbi_base2 = NULL; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_SUPPORT_64BIT)) dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); ret = dw_pcie_ep_init(ep); @@ -1124,30 +1124,30 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, return ret; } /* Start LTSSM. */ - imx6_pcie_ltssm_enable(dev); + imx_pcie_ltssm_enable(dev); return 0; } -static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) +static void imx_pcie_pm_turnoff(struct imx_pcie *imx_pcie) { - struct device *dev = imx6_pcie->pci->dev; + struct device *dev = imx_pcie->pci->dev; /* Some variants have a turnoff reset in DT */ - if (imx6_pcie->turnoff_reset) { - reset_control_assert(imx6_pcie->turnoff_reset); - reset_control_deassert(imx6_pcie->turnoff_reset); + if (imx_pcie->turnoff_reset) { + reset_control_assert(imx_pcie->turnoff_reset); + reset_control_deassert(imx_pcie->turnoff_reset); goto pm_turnoff_sleep; } /* Others poke directly at IOMUXC registers */ - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX6SX: case IMX6QP: - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, IMX6SX_GPR12_PCIE_PM_TURN_OFF); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0); break; default: @@ -1166,73 +1166,73 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie) usleep_range(1000, 10000); } -static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save) +static void imx_pcie_msi_save_restore(struct imx_pcie *imx_pcie, bool save) { u8 offset; u16 val; - struct dw_pcie *pci = imx6_pcie->pci; + struct dw_pcie *pci = imx_pcie->pci; if (pci_msi_enabled()) { offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI); if (save) { val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS); - imx6_pcie->msi_ctrl = val; + imx_pcie->msi_ctrl = val; } else { dw_pcie_dbi_ro_wr_en(pci); - val = imx6_pcie->msi_ctrl; + val = imx_pcie->msi_ctrl; dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); dw_pcie_dbi_ro_wr_dis(pci); } } } -static int imx6_pcie_suspend_noirq(struct device *dev) +static int imx_pcie_suspend_noirq(struct device *dev) { - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - imx6_pcie_msi_save_restore(imx6_pcie, true); - imx6_pcie_pm_turnoff(imx6_pcie); - imx6_pcie_stop_link(imx6_pcie->pci); - imx6_pcie_host_exit(pp); + imx_pcie_msi_save_restore(imx_pcie, true); + imx_pcie_pm_turnoff(imx_pcie); + imx_pcie_stop_link(imx_pcie->pci); + imx_pcie_host_exit(pp); return 0; } -static int imx6_pcie_resume_noirq(struct device *dev) +static int imx_pcie_resume_noirq(struct device *dev) { int ret; - struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev); - struct dw_pcie_rp *pp = &imx6_pcie->pci->pp; + struct imx_pcie *imx_pcie = dev_get_drvdata(dev); + struct dw_pcie_rp *pp = &imx_pcie->pci->pp; - if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) + if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; - ret = imx6_pcie_host_init(pp); + ret = imx_pcie_host_init(pp); if (ret) return ret; - imx6_pcie_msi_save_restore(imx6_pcie, false); + imx_pcie_msi_save_restore(imx_pcie, false); dw_pcie_setup_rc(pp); - if (imx6_pcie->link_is_up) - imx6_pcie_start_link(imx6_pcie->pci); + if (imx_pcie->link_is_up) + imx_pcie_start_link(imx_pcie->pci); return 0; } -static const struct dev_pm_ops imx6_pcie_pm_ops = { - NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq, - imx6_pcie_resume_noirq) +static const struct dev_pm_ops imx_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_pcie_suspend_noirq, + imx_pcie_resume_noirq) }; -static int imx6_pcie_probe(struct platform_device *pdev) +static int imx_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dw_pcie *pci; - struct imx6_pcie *imx6_pcie; + struct imx_pcie *imx_pcie; struct device_node *np; struct resource *dbi_base; struct device_node *node = dev->of_node; @@ -1240,8 +1240,8 @@ static int imx6_pcie_probe(struct platform_device *pdev) u16 val; int i; - imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); - if (!imx6_pcie) + imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL); + if (!imx_pcie) return -ENOMEM; pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); @@ -1250,10 +1250,10 @@ static int imx6_pcie_probe(struct platform_device *pdev) pci->dev = dev; pci->ops = &dw_pcie_ops; - pci->pp.ops = &imx6_pcie_host_ops; + pci->pp.ops = &imx_pcie_host_ops; - imx6_pcie->pci = pci; - imx6_pcie->drvdata = of_device_get_match_data(dev); + imx_pcie->pci = pci; + imx_pcie->drvdata = of_device_get_match_data(dev); /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); @@ -1265,9 +1265,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "Unable to map PCIe PHY\n"); return ret; } - imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); - if (IS_ERR(imx6_pcie->phy_base)) - return PTR_ERR(imx6_pcie->phy_base); + imx_pcie->phy_base = devm_ioremap_resource(dev, &res); + if (IS_ERR(imx_pcie->phy_base)) + return PTR_ERR(imx_pcie->phy_base); } pci->dbi_base = devm_platform_get_and_ioremap_resource(pdev, 0, &dbi_base); @@ -1275,12 +1275,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) return PTR_ERR(pci->dbi_base); /* Fetch GPIOs */ - imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); - imx6_pcie->gpio_active_high = of_property_read_bool(node, + imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); + imx_pcie->gpio_active_high = of_property_read_bool(node, "reset-gpio-active-high"); - if (gpio_is_valid(imx6_pcie->reset_gpio)) { - ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, - imx6_pcie->gpio_active_high ? + if (gpio_is_valid(imx_pcie->reset_gpio)) { + ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio, + imx_pcie->gpio_active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW, "PCIe reset"); @@ -1288,70 +1288,70 @@ static int imx6_pcie_probe(struct platform_device *pdev) dev_err(dev, "unable to get reset gpio\n"); return ret; } - } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { - return imx6_pcie->reset_gpio; + } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) { + return imx_pcie->reset_gpio; } - if (imx6_pcie->drvdata->clks_cnt >= IMX6_PCIE_MAX_CLKS) + if (imx_pcie->drvdata->clks_cnt >= IMX_PCIE_MAX_CLKS) return dev_err_probe(dev, -ENOMEM, "clks_cnt is too big\n"); - for (i = 0; i < imx6_pcie->drvdata->clks_cnt; i++) - imx6_pcie->clks[i].id = imx6_pcie->drvdata->clk_names[i]; + for (i = 0; i < imx_pcie->drvdata->clks_cnt; i++) + imx_pcie->clks[i].id = imx_pcie->drvdata->clk_names[i]; /* Fetch clocks */ - ret = devm_clk_bulk_get(dev, imx6_pcie->drvdata->clks_cnt, imx6_pcie->clks); + ret = devm_clk_bulk_get(dev, imx_pcie->drvdata->clks_cnt, imx_pcie->clks); if (ret) return ret; - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHYDRV)) { - imx6_pcie->phy = devm_phy_get(dev, "pcie-phy"); - if (IS_ERR(imx6_pcie->phy)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) { + imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); + if (IS_ERR(imx_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), "failed to get pcie phy\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_APP_RESET)) { - imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); - if (IS_ERR(imx6_pcie->apps_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_APP_RESET)) { + imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); + if (IS_ERR(imx_pcie->apps_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), "failed to get pcie apps reset control\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_PHY_RESET)) { - imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); - if (IS_ERR(imx6_pcie->pciephy_reset)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->pciephy_reset), + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHY_RESET)) { + imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx_pcie->pciephy_reset)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), "Failed to get PCIEPHY reset control\n"); } - switch (imx6_pcie->drvdata->variant) { + switch (imx_pcie->drvdata->variant) { case IMX8MQ: case IMX8MQ_EP: case IMX7D: if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) - imx6_pcie->controller_id = 1; + imx_pcie->controller_id = 1; break; default: break; } /* Grab turnoff reset */ - imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); - if (IS_ERR(imx6_pcie->turnoff_reset)) { + imx_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); + if (IS_ERR(imx_pcie->turnoff_reset)) { dev_err(dev, "Failed to get TURNOFF reset control\n"); - return PTR_ERR(imx6_pcie->turnoff_reset); + return PTR_ERR(imx_pcie->turnoff_reset); } - if (imx6_pcie->drvdata->gpr) { + if (imx_pcie->drvdata->gpr) { /* Grab GPR config register range */ - imx6_pcie->iomuxc_gpr = - syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = + syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } - if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_HAS_SERDES)) { + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_SERDES)) { void __iomem *off = devm_platform_ioremap_resource_byname(pdev, "app"); if (IS_ERR(off)) @@ -1364,59 +1364,59 @@ static int imx6_pcie_probe(struct platform_device *pdev) .reg_stride = 4, }; - imx6_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); - if (IS_ERR(imx6_pcie->iomuxc_gpr)) - return dev_err_probe(dev, PTR_ERR(imx6_pcie->iomuxc_gpr), + imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); + if (IS_ERR(imx_pcie->iomuxc_gpr)) + return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), "unable to find iomuxc registers\n"); } /* Grab PCIe PHY Tx Settings */ if (of_property_read_u32(node, "fsl,tx-deemph-gen1", - &imx6_pcie->tx_deemph_gen1)) - imx6_pcie->tx_deemph_gen1 = 0; + &imx_pcie->tx_deemph_gen1)) + imx_pcie->tx_deemph_gen1 = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", - &imx6_pcie->tx_deemph_gen2_3p5db)) - imx6_pcie->tx_deemph_gen2_3p5db = 0; + &imx_pcie->tx_deemph_gen2_3p5db)) + imx_pcie->tx_deemph_gen2_3p5db = 0; if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", - &imx6_pcie->tx_deemph_gen2_6db)) - imx6_pcie->tx_deemph_gen2_6db = 20; + &imx_pcie->tx_deemph_gen2_6db)) + imx_pcie->tx_deemph_gen2_6db = 20; if (of_property_read_u32(node, "fsl,tx-swing-full", - &imx6_pcie->tx_swing_full)) - imx6_pcie->tx_swing_full = 127; + &imx_pcie->tx_swing_full)) + imx_pcie->tx_swing_full = 127; if (of_property_read_u32(node, "fsl,tx-swing-low", - &imx6_pcie->tx_swing_low)) - imx6_pcie->tx_swing_low = 127; + &imx_pcie->tx_swing_low)) + imx_pcie->tx_swing_low = 127; /* Limit link speed */ pci->link_gen = 1; of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); - imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); - if (IS_ERR(imx6_pcie->vpcie)) { - if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) - return PTR_ERR(imx6_pcie->vpcie); - imx6_pcie->vpcie = NULL; + imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); + if (IS_ERR(imx_pcie->vpcie)) { + if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) + return PTR_ERR(imx_pcie->vpcie); + imx_pcie->vpcie = NULL; } - imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); - if (IS_ERR(imx6_pcie->vph)) { - if (PTR_ERR(imx6_pcie->vph) != -ENODEV) - return PTR_ERR(imx6_pcie->vph); - imx6_pcie->vph = NULL; + imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); + if (IS_ERR(imx_pcie->vph)) { + if (PTR_ERR(imx_pcie->vph) != -ENODEV) + return PTR_ERR(imx_pcie->vph); + imx_pcie->vph = NULL; } - platform_set_drvdata(pdev, imx6_pcie); + platform_set_drvdata(pdev, imx_pcie); - ret = imx6_pcie_attach_pd(dev); + ret = imx_pcie_attach_pd(dev); if (ret) return ret; - if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { - ret = imx6_add_pcie_ep(imx6_pcie, pdev); + if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { + ret = imx_add_pcie_ep(imx_pcie, pdev); if (ret < 0) return ret; } else { @@ -1436,12 +1436,12 @@ static int imx6_pcie_probe(struct platform_device *pdev) return 0; } -static void imx6_pcie_shutdown(struct platform_device *pdev) +static void imx_pcie_shutdown(struct platform_device *pdev) { - struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); + struct imx_pcie *imx_pcie = platform_get_drvdata(pdev); /* bring down link, so bootloader gets clean state in case of reboot */ - imx6_pcie_assert_core_reset(imx6_pcie); + imx_pcie_assert_core_reset(imx_pcie); } static const char * const imx6q_clks[] = {"pcie_bus", "pcie", "pcie_phy"}; @@ -1449,11 +1449,11 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; -static const struct imx6_pcie_drvdata drvdata[] = { +static const struct imx_pcie_drvdata drvdata[] = { [IMX6Q] = { .variant = IMX6Q, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1462,13 +1462,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX6SX] = { .variant = IMX6SX, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6sx_clks, .clks_cnt = ARRAY_SIZE(imx6sx_clks), @@ -1480,9 +1480,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX6QP] = { .variant = IMX6QP, - .flags = IMX6_PCIE_FLAG_IMX6_PHY | - IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE | - IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, + .flags = IMX_PCIE_FLAG_IMX_PHY | + IMX_PCIE_FLAG_IMX_SPEED_CHANGE | + IMX_PCIE_FLAG_SUPPORTS_SUSPEND, .dbi_length = 0x200, .gpr = "fsl,imx6q-iomuxc-gpr", .clk_names = imx6q_clks, @@ -1491,13 +1491,13 @@ static const struct imx6_pcie_drvdata drvdata[] = { .ltssm_mask = IMX6Q_GPR12_PCIE_CTL_2, .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, - .init_phy = imx6_pcie_init_phy, + .init_phy = imx_pcie_init_phy, }, [IMX7D] = { .variant = IMX7D, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx7d-iomuxc-gpr", .clk_names = imx6q_clks, .clks_cnt = ARRAY_SIZE(imx6q_clks), @@ -1507,8 +1507,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ] = { .variant = IMX8MQ, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), @@ -1520,9 +1520,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM] = { .variant = IMX8MM, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1531,9 +1531,9 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP] = { .variant = IMX8MP, - .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND | - IMX6_PCIE_FLAG_HAS_PHYDRV | - IMX6_PCIE_FLAG_HAS_APP_RESET, + .flags = IMX_PCIE_FLAG_SUPPORTS_SUSPEND | + IMX_PCIE_FLAG_HAS_PHYDRV | + IMX_PCIE_FLAG_HAS_APP_RESET, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, .clks_cnt = ARRAY_SIZE(imx8mm_clks), @@ -1542,7 +1542,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX6_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1553,8 +1553,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MQ_EP] = { .variant = IMX8MQ_EP, - .flags = IMX6_PCIE_FLAG_HAS_APP_RESET | - IMX6_PCIE_FLAG_HAS_PHY_RESET, + .flags = IMX_PCIE_FLAG_HAS_APP_RESET | + IMX_PCIE_FLAG_HAS_PHY_RESET, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mq-iomuxc-gpr", .clk_names = imx8mq_clks, @@ -1568,7 +1568,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MM_EP] = { .variant = IMX8MM_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mm-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1579,7 +1579,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX8MP_EP] = { .variant = IMX8MP_EP, - .flags = IMX6_PCIE_FLAG_HAS_PHYDRV, + .flags = IMX_PCIE_FLAG_HAS_PHYDRV, .mode = DW_PCIE_EP_TYPE, .gpr = "fsl,imx8mp-iomuxc-gpr", .clk_names = imx8mm_clks, @@ -1590,8 +1590,8 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, [IMX95_EP] = { .variant = IMX95_EP, - .flags = IMX6_PCIE_FLAG_HAS_SERDES | - IMX6_PCIE_FLAG_SUPPORT_64BIT, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_SUPPORT_64BIT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3, @@ -1604,7 +1604,7 @@ static const struct imx6_pcie_drvdata drvdata[] = { }, }; -static const struct of_device_id imx6_pcie_of_match[] = { +static const struct of_device_id imx_pcie_of_match[] = { { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], }, { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], }, { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], }, @@ -1620,19 +1620,19 @@ static const struct of_device_id imx6_pcie_of_match[] = { {}, }; -static struct platform_driver imx6_pcie_driver = { +static struct platform_driver imx_pcie_driver = { .driver = { .name = "imx6q-pcie", - .of_match_table = imx6_pcie_of_match, + .of_match_table = imx_pcie_of_match, .suppress_bind_attrs = true, - .pm = &imx6_pcie_pm_ops, + .pm = &imx_pcie_pm_ops, .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, - .probe = imx6_pcie_probe, - .shutdown = imx6_pcie_shutdown, + .probe = imx_pcie_probe, + .shutdown = imx_pcie_shutdown, }; -static void imx6_pcie_quirk(struct pci_dev *dev) +static void imx_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; struct dw_pcie_rp *pp = bus->sysdata; @@ -1642,33 +1642,33 @@ static void imx6_pcie_quirk(struct pci_dev *dev) return; /* Make sure we only quirk devices associated with this driver */ - if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) + if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) return; if (pci_is_root_bus(bus)) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); /* * Limit config length to avoid the kernel reading beyond * the register set and causing an abort on i.MX 6Quad */ - if (imx6_pcie->drvdata->dbi_length) { - dev->cfg_size = imx6_pcie->drvdata->dbi_length; + if (imx_pcie->drvdata->dbi_length) { + dev->cfg_size = imx_pcie->drvdata->dbi_length; dev_info(&dev->dev, "Limiting cfg_size to %d\n", dev->cfg_size); } } } DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd, - PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk); + PCI_CLASS_BRIDGE_PCI, 8, imx_pcie_quirk); -static int __init imx6_pcie_init(void) +static int __init imx_pcie_init(void) { #ifdef CONFIG_ARM struct device_node *np; - np = of_find_matching_node(NULL, imx6_pcie_of_match); + np = of_find_matching_node(NULL, imx_pcie_of_match); if (!np) return -ENODEV; of_node_put(np); @@ -1684,6 +1684,6 @@ static int __init imx6_pcie_init(void) "external abort on non-linefetch"); #endif - return platform_driver_register(&imx6_pcie_driver); + return platform_driver_register(&imx_pcie_driver); } -device_initcall(imx6_pcie_init); +device_initcall(imx_pcie_init); From patchwork Mon Mar 4 20:25:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581187 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C06D7BAF0; Mon, 4 Mar 2024 20:25:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583949; cv=fail; b=kzVHpv/Nv07xkGMvatRl6g28BV4SeHNCbtmxhkr4vxE45XbAku5dkWhc8jsEhGgP6ed/O5yUH/HziDcuWP8vBqlebZ7eFGgGb2cgpJWHqni6o2vCR9y1QM1KpLW4yYCI8yKJmatUijCndxDjhq8VZPqMbU24yXBiVW9A9Bjrr2Y= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583949; c=relaxed/simple; bh=1r2H1hqe2HsquQcW5xHXQOeJXeR6VzCgSFRI6Lw/PzM=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=tfEGT7v149kZEFCxe43ymKy/9D5hLhqO4hpLAaSktGXWYJ5tCAs/XJEiQnffFCJWBx0Zlf/xw+5W1tdDf84fWqQorj/5NySmmJftcOYfE4+B4P2XgKEfoSqOC8ckw0nqxvvHepRMj7k4iRPQOlR6JiX2kXkqAmdNwFhzq1EQmKI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=K9G7VuBn; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="K9G7VuBn" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=g0NaVPKsoaaYXfCW3hua0QZqeNf1dmI42XNUd1rnyXfJpLSIQMgpKb4rUVOnRRiiB6OOOMawxWGwl8hF75H+5Rqf9FqnGRvS2neIrYZDpxqYvKn2l0iahNTFzUhmEHyjgWNtpcMW/+U1nWxJUkXF/BhXm7Hh07Gf9ouasOHDnlKvIvMywfQSb5ifTXnjEeJcfAzfH8sJHmEcYcRuaHkrk8Xs+gVAtoSEWjSjyyaMeq/ePMixqgvaEc5GtFj7GXcoxObTIz3tPJEyLkivYmYqt3oOknXgrSvwOLvhnL0ESucFU7awB74BqDf/NSpYl8o/w8ZcLqHINZYobaFXtXbkGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BTPBXfAX1P6YHzKk8sQ6o3YDjVYk1m+DwbidtzQix0E=; b=gk8J4RHs6D/8agIdqbd60oLCAZzRiUGKLMxv4xmeBSN5bqUK38CFqR7/4RDpVI27naoFnjlEOTUTGx5gjWhCBTIJhoBCqoz0ZTDeLPIULQEp8kCuOlMoB6IC+a86UaiH/k+HcGOG+VWIQS4fQUFFGXl8BduPkNbV8CHuMYaNOXNLilnNWFRM/j9TN/WNHpxbV5QZzLxy9bUna0g2ofmVMUXyOhPV+z7fbJ7nD53E6DoDUKonuDhZwgTvu69BrLBk25kGjgHfJLyNTtP/TYhA9JhTZYkh6FEvcEXjRQsYtSe832hiw3E9Dgkkq+u+jg7HbZcsXCeej6xWVhJw/IK0gw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BTPBXfAX1P6YHzKk8sQ6o3YDjVYk1m+DwbidtzQix0E=; b=K9G7VuBn4eyxDXdS52CjEhB9se1DCYAy/spN3wC59SaSp2mrOwK3ruSqzTGWcuICw+NDkxh9YQ8xxpJQLTAH76yygMr+YOewQ57sr1N/2/Wcyc6MDjdGRzX27Z3hkLDSNacMJ1qFaOT+Py0doNNXJVN4Y+WXHZTIwtjUcOyl6FI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:42 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:42 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:07 -0500 Subject: [PATCH v2 2/6] PCI: imx6: Rename pci-imx6.c to pcie-imx.c Message-Id: <20240304-pci2_upstream-v2-2-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583933; l=1420; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=1r2H1hqe2HsquQcW5xHXQOeJXeR6VzCgSFRI6Lw/PzM=; b=1rYsnrMpwBTgURMdc1OsHoxLP7WF22aLHJH9UQyGqvvPuiAVvdNtJssV4o+lQkYXIsTNbhdej QOWhT12HNaBC3v6mwWJWHY+LFe/UhXpMKqcYSUTiLdxlrjg62638Z0y X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: 859e3365-af77-4b9c-94aa-08dc3c89439f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kfZ/D0CHQF8vfCsoJoWulhgtUWXb+eVzoIGV5LSZVDoueBcBrANQ/FaUZz2fXj9COmaoCFvQNrj861vGWH7iwRkFco80VSnuGywm9968eYcM9Z/PpKfy9+5CraPOswySZpe8TGUBVBEeQ5SKm0rsQRN+EsR0mLQSuLbamutzpAd1p2KgeQRV3OxUOLN1hG8ly//RbszFG4EA43U/pyl8gMyWyWZm5TJwG2+kjYr3eo5bbr+9zCNfYsLPCdODK+KtIN/9m5ZihRnMqbMNeCHh4JU/g4Z7wo7VuWhFcc5OiyMrKN/KBMMB6Kz5j+76p8Nyaj+Ze/w3bEDyspcknEmK8hVRHxnoIhiNC0ZOTKoaXag26cgJSmxF7etlhjVGhzF7TmXbNpM7kCZ5oBjki2LjEfqcFB7zzorOz+epmXvokYe/lkjzhFnRvBvNYxZAa5mKuo/pnop/0ApE+4JwTqfWpnVaVMLZPPkkIZowqnFDnaZdZ6vF1TxwwyKYzl7oGNezKIYBKKceSbLr+FWuO/cLiHbeRusL7e4EuCgKrIxLTwEIwi7uCdKGLUgPR5+97ndUfsfWd6wZgZt4Nh4CuyWGTtXA1GtoyEN8UMSmhedJ6XGrbJ30ZYs15ErYhgvQPFM0SD+Fn0d9bZ9EniYbHMdntL5bNbH4ULrJGzLlnrcx7FeVicWYYm1OdzS2t4jwiiExKA8cBsHNxClPyapJTXtLQcQUbM+ClgzoMxBR6kQVcI4= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?IXY0P4LJw4MBsXpv4GOLrkvMRhPQ?= =?utf-8?q?crcxzPA/wwq78Xr/P3vLFJ+dU/+Kv1bT5ql89IE+Aeo+7pg+6rmyTwF/AN1jnoBPi?= =?utf-8?q?YyGYT4e15A+eTtjhJBG+m6GDTU17Si4Do5ZGsC84iLuYQv+8XAdaFGDYXtH/XUdro?= =?utf-8?q?JupTy0Z92EJHRC/mJfFAsv0/V/2hIcbTgMW9OVb8q7ADlNod18WXe2w/sphEh+lll?= =?utf-8?q?zPoaois9PCSy/7uht+ty4zJaIiX+xFd1Ed7Wpw/yS8z6RCbR9HO3+ScJlK2SndqHB?= =?utf-8?q?x5o33aX39gwCRejN6uFytsgvlMMDlrYQL17KkJn8mNMINgK0zDI6QvfPfqUvQN62A?= =?utf-8?q?F7lz//WRyPuXct03IbSPfl+tvIm2l3trNs2MqpwOpM/QKsnWVsl0MouR7VNFAnoNP?= =?utf-8?q?du8emLNRcQgc6BhFJlyeZIj5XUJ6Kd6q/Fr41rj32tZZcbsi3jka6CXiDWCAwAMOb?= =?utf-8?q?ZDLFOjxMkpPFg8lyPv9CdJVf8lJGmGpoOQZ7K+uybSUHo7FvvfJxEkHG3ZE1cVGK7?= =?utf-8?q?xpnRBd8ByY6mI62AJXGM0fPcF6J3Gr8pU6ZOHCv2E8bSPGz538WFOaGdU0nzzXUtB?= =?utf-8?q?nRqv/fhOLAFIxwFLuyh+joJDrjA1G2ZWU7Af3tEHo5pFYAAr8ZHZuzQtZ9KHRZb5G?= =?utf-8?q?1ZcQ2urUqWGBeJrxjeEFZFvoYvCKLGIR9lxjd3ls3MNovyOzgFs3PggKosmAGSq59?= =?utf-8?q?vx5++yhlCKOTRgIAlU+uP06J2TKlwO0D8ao7Mf8nFfB7+Jy5oyTxK5DOwnURqRuq0?= =?utf-8?q?p3m9tsIej7FtcwnoQFKFpbkP7b+yKj71SmJA1cUqyZ5hlk/niEAv4IZExpIvuivpO?= =?utf-8?q?gMR3d8ktMMtTG6eppH8bp8C6g/UATKS407wnjXhEb0sXzu2NGHaMXLYmMkVv8B9iU?= =?utf-8?q?ZSBcjubUbb8ZMSRA2+nzTBT3hDaBBVcPDm+OnzdnY5BYFOPnGsUVFvieiz4j1bups?= =?utf-8?q?mU6vIij8yXbOksHNAEzEAuUkhPV/1x0Zqub58RpiBJKhJiWf6EBASJnRReitEZcal?= =?utf-8?q?boOGjUJgRiCoAGozZWS2gb7XeV6xzBTkNA/WbKIKeCa/H4VJ7vVRWUb1DR4uHe/9l?= =?utf-8?q?8xMiP+YUl/d0ABB6oWkQm2L95NXSV5CdAEUkXRhlISwnQdk6H7E0+r+BGVVc0ydYM?= =?utf-8?q?Sk71YdvKym3j7UzFTSvWdCef0Me59yMFaRFZZruuK74fSz0MANyuy2owxl+NZEyp6?= =?utf-8?q?ZkP445CPnOdSPmK7nbhlRoO4H0GnSVK8TJv7DnnIkR9YiIGF2ISHui1ODPEr7NwHu?= =?utf-8?q?DorzkBR9m/Ire5d6xPXigzSXrowxFR2f1lccOU9otcoZLLRgA1hRRoIp7LP2PBUek?= =?utf-8?q?VDh/J64f3WkAqiywMAiXicKbbe043u6tpJIa7J6Zmjs5NsBXqRncUczBPf4nyfNIu?= =?utf-8?q?49zIAAGXwOaL8wYdfA3Mf3hfJLctnjcOtOM/xaX38NtQQcX/jOg5hQWpBUbzQHbxy?= =?utf-8?q?UlNUcIRBSPJQ6rm7r9O//BE609LsHGaDqW4WBY1lqZAfN34ZSoA/TMrb0l42AyS3T?= =?utf-8?q?7AQ42sqP84r9?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 859e3365-af77-4b9c-94aa-08dc3c89439f X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:42.3255 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q/s1FyvFhYRW3PNVKzpSuhTvzCSF48i0o7W06iG4UEKyMuH8GdyQgzxxwGzeHUJmA1XW5uDm9P6+gV3EmdMYgA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 Update the filename from 'pci-imx6.c' to 'pcie-imx.c' to accurately reflect its applicability to all i.MX chips (i.MX6x, i.MX7x, i.MX8x, i.MX9x). Eliminate the '6' to prevent confusion. Additionally, correct the prefix from 'pci-' to 'pcie-'. Retain the previous configuration CONFIG_PCI_IMX6 unchanged to maintain compatibility. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/Makefile | 2 +- drivers/pci/controller/dwc/{pci-imx6.c => pcie-imx.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index bac103faa5237..eaea7abbabc2c 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -7,7 +7,7 @@ obj-$(CONFIG_PCIE_BT1) += pcie-bt1.o obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o -obj-$(CONFIG_PCI_IMX6) += pci-imx6.o +obj-$(CONFIG_PCI_IMX6) += pcie-imx.o obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pcie-imx.c similarity index 100% rename from drivers/pci/controller/dwc/pci-imx6.c rename to drivers/pci/controller/dwc/pcie-imx.c From patchwork Mon Mar 4 20:25:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581188 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D8607BB04; Mon, 4 Mar 2024 20:25:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583951; cv=fail; b=P5IIEFtMijesPGfZjlOtqZkW0Elrt6HNrJQtmcdY/GJrVc4ezj0DqMnhQlMWHXtitXh9/oss/nuLWH/uSOulGBpYABLjf80kuGnMjVMybXoYirtnYGZmnfgcqU7l6iwR+CIFRzgfEKCD2JgCygyyPs4Ov6DRmnzuDAUzAfFSMrA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583951; c=relaxed/simple; bh=7LEmma9asVcc2UpABKTIPCze0Rfq/WnOrCDirUI9M1s=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=s/NtdjXZY/FF+M6/hbjoVcogKYfmfAIXx9HlLHRIiWaaxibiZcCHXsYl3yN2FlRSZWb/Ln8+w1+Qm+Z1rzB5Qb+GbR2N2Fd2kgc9Tr4A0c0Nd09Il+blaM2VuHu1cLOqeEDeHjZ2Ut3kqSKAASHlCPZcLSHdl9HcEPhLDZinHvo= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=s4qi1hdD; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="s4qi1hdD" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=AX5LDRgubqUwWA6jttaeeX2uAxBsiZSfMlqw0WMM4cjcupms3gUP0JYTL2QGisZxs4En2CXx5i03kSN+/3eJi8gh1oLd7uPZKTWfMKE41UxDIQtjl3BjWZzNh6wEJsY1Y4KdMcPPHBl0l+b1asJ2ruUZMq7GJjMKLlt03lODYLTXqxUha3k/atKv1Hjh11vnSIskrOFwa/KshDDSbrySXBCCceddfzZSOvYwMNCqcETjZmItcHcLhf2QhexQRGWyZcGzAEN8+U3vlFued3JkqGN2bRjHAGhHFbIzPCuTH0nXTynyrtnRpQXShNMdvMFydv1QKt3ZRM/pjmAsGRUlEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bYoXCN2Cg7BevWD2QEgj8BjNP6h0jRB2sBiityVf9KU=; b=YbORUbHmdTFYUHda8tORRd7naRNHZCTloIct924/SziZrIn+AC0hrqo+HSGrvwdWOClEkTDPBAwjHwa+zXY3ZnTU+fcMD0Ln528/6qMMfjPW1OxANs+ZCRS+Z4m45Hu7FaESeucA5SiJnGzDJkeFdckSPhrmrtAauEwLDjdQjIP8MDZfObKsQh7AR+Q/tL+/IOJXPTHw/7tD81SmSShceoGc2TVouRNG62UBul3VWpv8KTSmojpYOftmU5JB5AeqbJaef+jRiTytVkPNfBepAyrPKHApRz50E/yzBikWA0lSy8A6HhJ20enVnAiyZ6YE8mTPMcsH+3FPfR6WG3Vq2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bYoXCN2Cg7BevWD2QEgj8BjNP6h0jRB2sBiityVf9KU=; b=s4qi1hdDvSlNDmXm7XQEEbEdLUcY0JNMAcUQ/wUOc/xFZUOomCnoMw8HbsTmhmVnGICKQboheBde+AdbwWMGVxX4UYzQFVNKIH/zR8ZSQ3pjLtguZZ2g/hRqAoskATCGM+Lm+wK+xhRsQ42sVjC+12vbd8BSiLaTNTkMy91lYaA= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:45 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:45 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:08 -0500 Subject: [PATCH v2 3/6] MAINTAINERS: pci: imx: update imx6* to imx* since rename driver file Message-Id: <20240304-pci2_upstream-v2-3-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583933; l=1049; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=7LEmma9asVcc2UpABKTIPCze0Rfq/WnOrCDirUI9M1s=; b=6vxP3+92740+jYD/IDmpYE8t9jY7e9aKX4CS1qrQ9g2HaUAmaQC6rNrZz1qnhxLgZ/aL3uI0m ncpeR9fRDOGC8VtmFWAUqAKurhRi/IsVlbncCdspbZu7mpliM1gdkfQ X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: 20d3ff15-42dd-442b-ea6f-08dc3c894575 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2+LyMCnvGeFDO1Ya7+BXE36e5SU6A6QTs8UpxhC4XtJNJx5tUDEjKJTOjBeGS+gpNGj+hCROo2iF8geZ7dPjqEjqEGKNoMLIO0L9WG/ZJMyiJkMDpeNsyK+16DQQ4viXZGp12eeAV10OUSEfjRxWPUuE00gzyPY6v+VS32SHm3B67nkBu71mU0CuooCA7s0z/0hjpZwcshWII5L48oZvcNGJTN31lHdd2Xm859afjY54lWzTcU5BqcfRClhDvj0f6xaMH87oQ1C+ImR7XlreyMiIyCrRUc1/W0whxOpQnzTbXNqZ+2YmMY5R3+TgtYqmEN7LBdWjFqjw/7A65Y2ztkmShY/eNqB5f+pPaL5gHzW0tU4VyxPUbE79cvq/NQw8SGRIj88pznAZH2c91dEBCGdSlU38lBJpNzh6amXxbeLdNr3yESug9SwaDp2yJkc3Jkpa9QqNxaTpHKDfy1rtXXHktjusubdoAq2vyCnnlrzDvxFhgVY+MXIGByp0PnPB/SwVP+lHzufYlwPuDdnwNMxI1GWmt3QLhkmPzfLa13c+up8I2Gf3f0HPRDVezAGJTLX6aVMnhcsDYIlbYGkJCMMAmrI8CP6R2F2UR5l/OuCftuaPXMtKMnpnu/ew8dFYqZTra6gzp6/gy5NVFSAf5wc5EhsQe5K5GZiO454seywarfa4NBtlczYZ7jZ2JqMc4TTYP38PH3n0FoJqWQEVnh8LbWpoGa9Hs8kjiyip2/I= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?JQZnjnAV+iIRxlFoNVTkctGcAlo8?= =?utf-8?q?mv9AifLhmP9QPZqT+5qkK2rF34JGOUnaMYs1BVB11TXj2OYXnb28ag97TFnG6lW8y?= =?utf-8?q?gZpvMHbsLQK4qnPwNqTX2QP47kDbFaQeKDE2ycDN8ZEYjY2cQTzurjvCdRLg2Httf?= =?utf-8?q?QluW2Nqlu/TdF+sP7mSVPQSCraAogD6MwohazKzmqeRYswXY1wKEd06DmJDWKH/ty?= =?utf-8?q?CKVTMX97mm32mspDK6BfixP1Kk5yVlF+VUeYRAaflNCfF8ftfAi97M7SG/ztIRtmE?= =?utf-8?q?TdtFLdvYJb0udu/cAS+zwBoy/gwfRyw5gFy1wQ//RyR4EG3DBDnSSefXy/3tDMYoO?= =?utf-8?q?oosR4uuok2nN/4KYMFRUctGA0xRhv8EaHMHSCjX7FClHiR6GI4Bp3c+IZsp/nJwHm?= =?utf-8?q?p7ECwnLLQNJNspuXz/FOcVg9f+cIm138XomN0RI2L2G71tbvQ5KnwYDRYB0Vbhg3M?= =?utf-8?q?UbQAb7qWiyQ8qw9W+qux5ABZEvYji4niCfHbqgpf8Tg/vLlbgp4GqXNo7cLLNVtJ1?= =?utf-8?q?czqcaenBEGPOyqWWJ0+CIZzS33kZqvCDLq1kHIvCh/SzYyFsJh6rc/yIqldZUuDOK?= =?utf-8?q?Grfz2dpVDMu+zigMc+GhE3bpc98Earx24Yt7VxwHr3NGfCCGytm75CmDRyJv1PK89?= =?utf-8?q?VSVDANFVeDrAlII1K/3ytMmzmak3LFDuSDjld7HLqk2WiAloHtR3mXS/J6b9q7J2L?= =?utf-8?q?5i62cJGeQdEdULiZQO97F6PpCPPl9SrtOJQ83+7lblCT0lQPBQbrPh+87ZSBRSbtr?= =?utf-8?q?ViiKOmxPFA/LyglT8JRa20k0Rx5TwKobZNqp2vkNvnIxZ9poT3QZe2JYqbflfE9dL?= =?utf-8?q?vORu8gyHABRbtiYoQ5YBUeFoNS0Dn16fN4QslYYRXHw/S4jEeSN1DLcxwigJefu9b?= =?utf-8?q?cVmOPbLo3OBkGqq/vrjgf51Hm3Z0Y6qMR2bae/QGqjnW1ntHQC3Py8twsIAa3leeJ?= =?utf-8?q?XhxGm+mUBJUFIszEdsuaNY07ZZ4YDjWNSWKM3DpNF6ASg5StUyEH8MbrHBeUw1hbp?= =?utf-8?q?uv5Pdqi6NRo+woQohXzqJt/b9uR8IGw/kG8ytIG/nE3MjpT01iDSuQha3RCkha1Ei?= =?utf-8?q?g1I5F48gHzDC7I+5qfyCpDALFw2shgLXMdkB6RXizeUl/cPIac0IqBEDfeqCanmRk?= =?utf-8?q?9azC5uDKKupvPNrO2TQTUl/3JeGdCbsea4OK9bs8JK+mtF1VNTsYqSpJOmVAi6hP/?= =?utf-8?q?WVG5O5tX77FvoHqlMjkG0evOjuagpGKRynxeOXJ6sy2ktC8KgIfYMOzZVdWRYTz4p?= =?utf-8?q?x+utmi5RXOu7Unp09SpoDGTtW5ntKfaK6ahhSZ5MIWKYQZ2feeSe97+AmZAfaQIw8?= =?utf-8?q?mTvXTbHyqOjwgq5nmSaf8e0ZpekFv2AdnKWCWc9DH0e2+NHmk7BbuitklV6BfGMEo?= =?utf-8?q?2HoFORr64J/kmYdOzHmysIXWf6LEoM1uy6q3DD2WNXUDHhimRifM27GM8mJIsXrOV?= =?utf-8?q?xyi5d2GW7RwixYsE9KogNmw8QkZaIiadQv62Kgwf9OvOyjO9S04gg0tfTXdlzB+RS?= =?utf-8?q?OS0Cnd1NS3df?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 20d3ff15-42dd-442b-ea6f-08dc3c894575 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:45.4131 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: g9PMB/xlWxmsa9B7IDBIjSm5gqIeUpukHiD7dMYIVHHqvjDgfLAWdpQHbD1rL1IsfqTFmG74IGBj+OP87PEUHA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 Add me to imx pcie driver maintainer. Add mail list imx@lists.linux.dev. Signed-off-by: Frank Li --- MAINTAINERS | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8d1052fa6a692..59a409dd604d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16736,14 +16736,16 @@ F: drivers/pci/controller/pci-host-generic.c PCI DRIVER FOR IMX6 M: Richard Zhu +M: Frank Li M: Lucas Stach L: linux-pci@vger.kernel.org +L: imx@lists.linux.dev L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml -F: drivers/pci/controller/dwc/*imx6* +F: drivers/pci/controller/dwc/*imx* PCI DRIVER FOR INTEL IXP4XX M: Linus Walleij From patchwork Mon Mar 4 20:25:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581189 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 887B27AE5F; Mon, 4 Mar 2024 20:25:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583953; cv=fail; b=J9BN61aZgu2biqzT4M2iLeZKn7fIeupoUzk36WjA1dIuP1/lvLuKQK8TnACYio3E0HaDV59Ft77zG5MOECrYKL7aAE1LUaSlqObebWEorSL8XAuhBRmZAUSc4qatnJFgvF6NuNcEJ9P6N1NEsLFjDyLGL6nuXPxvxvcwYxpRelg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583953; c=relaxed/simple; bh=/5c2VQCQcdB8et6O4zhPC3Aakqqkv58KXa7+2gRtnao=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=KnKDsdadi0zMylKuKVLzMcA/Rr75iUw9aG6t1f9l7ECWXRKsik9NarahCHZ2lHWfXtXdNKnjuubq2eOmCVxDmL3dpMs62MdMn26X2KgAMtaRYyIf70sH9Z+5H93Y6+YocefdoZSeEOulWAlUBA2kfRn6b3ygdlMc1+o1sB1Rxic= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=n5Tl/qB8; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="n5Tl/qB8" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dwP/IztcOGJVMKBVU4ai97IqQaCs5pnWS/WA74JoxhbmvRxOuc4puM41TrTOwKN+X2Lue1QMfSyGkUL1tccbv/GmWhIlOcKqreAiYoFNOJACz9EeKPJPOu0OzF1SaYecR8nn1C9B+NSIhjzIfm1PyA/dJJ+3OoXL/WhQx84qYUQoJ3p3mdjYniVipkeeHPue5sEnlQwKNRIFGZtP5T/fcqSEskSwkcqVHehpvjwFEB6DC65KnS3HExUMVctU1f9RD50TtMfElHJOsl4P8jUTvewHYtqXapNAbanYdC9e1I8yIm7j42KrU9WucIsirjpReEO2mb12SE8Rk2VqK+w32A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=pJBOqXkoXm13e6CnPKvx4fKUG1nCA27kudK6IL/V1SM=; b=lxSh2fmdmsJ3Dm5Lp/9SNc+0/sOOHVklOV57uw5KPKBGGXUNO40dUFHrDXyj412Ud/eZHFE/TQop03SzbrzSBGKyMQTU1VXbOL9Mly1fPs+VMp0ptNeuszVoo3hv0zstwxpyIcRutcRYq1iSh2DfYPeafHnyf++ltYdT53HFuwy9K5za3unpLz52eeYOU4brUUuMBL1ELoJ+ovWQ5qCLNJFaUhjOlwnNsvM4uWTP7rg+QSh/RDQ1bdI7Hdq3o2ZZEkGlwy7gBCDo0Zz1lZXDQaQphyTAbbDDoHlFtJAsnjyFRokeMJ5A85S9xuMFjPjq0GwVNPqB2/6lHhKfw/pvlA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=pJBOqXkoXm13e6CnPKvx4fKUG1nCA27kudK6IL/V1SM=; b=n5Tl/qB8sMCzbSsIDPI7bnVDW1apxnKErYC7A/C34rkJM1dt9iVrrijZ6xGLTAdNIdVTHZp/dOYufm9JpAewncnU2A9qd22a2bRdvSLyv4nCEYTscpNg4B5ESignp9OTFwesln67V8QeCTiudskMfS2Od463K1sjoOWSjtjuXhs= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:48 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:48 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:09 -0500 Subject: [PATCH v2 4/6] PCI: imx: Simplify switch-case logic by involve set_ref_clk callback Message-Id: <20240304-pci2_upstream-v2-4-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583933; l=8518; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=/5c2VQCQcdB8et6O4zhPC3Aakqqkv58KXa7+2gRtnao=; b=zvcFMjJigUHrSsI6TyzDEHHuBsh16AncOohY95viCD66ijVzClHvmuegMoyTKmr4VlT6FF7Ln MMnc/j/2TLiCf6h3NATZXq7ux1rCSmkQr9y8nFar7TuqFwQUF/pONg6 X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: e3ac895f-95d4-4979-932b-08dc3c89474c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hgBMVMnNQd26L9CQKgXqK0RqUI8SkalS36VwY41ik1Daef13No3s1/lCStqxxO+bIT3iHjSNwyxtsS0nSqBR7LMs4CyQJ90y8/EuwLRIiA2i23CeCCTS7+ymPM6Yt53cCggAlDkrgAE8UU0WmlzHgcVVs0eOJckjH9aNvEMxzoNZ8tUHRqYBN4MggtyNzkGpY180rl3vzEd4/7W1QX3QE1HO/KIA7Bq+cgW/p/eyvr3ZPDIh6S5Thp5ki+vxBWvLDZ2bxYNKTzACIFLQAU+vJglioP5eVv82XfqSJYVaXVGXDzBHaz8nMdwR/M1pmUpGIVRbRTzLUNhyTuJqhcUkyjTVG3dxgP7f5pD1wvnpR6I9nmwFHADTMkvAkMBAoJNgyn5caFNkFTiCncxmxeOLN6LatnVyZJoBw3LiiOZiGLWOgjI4PkK7BhDep8DW81pzzOgR7a9sUNNeFszImSoxfcBQ7bruPl7PSwru6XWYafhXqf3ji1k5v796B8J8lUNEFei+2I90iJdjW18/jXK01RVWnyVo10hi1Ca6K/BgcBACAxv/FTgtTw2y0CtCSUXxATdCfCdWe6Tx8Sj1jm38REGTpJKeLG7TmO4rYlAbbM+mVLuzRpgE4xtJlV87HaYcXnW2VG3L6jYE+g9QSTkuKT2DVPFOaNEUKOZdfya/O0rV0282M68Y1In8l53O6Ovhi3kWet3AVhUpW0EwKxVsVgsH5hBXrYXFpYCLnKI0M+Q= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?c70SM59ETRpMg2GD5VGtJXLmQnqW?= =?utf-8?q?xAv80KjOfgVn88G5JqTgBkSK5Z6MTZb55Sfr2/3vuqzSoClIEMG8ZRupUbSJY4iqa?= =?utf-8?q?mfOzCY9r5s5AOG9k5g/0LAKYABQ91aHVdkMNbOzj7wEAyMzPmk5UBfyBoKQqGh6gM?= =?utf-8?q?OkFYR53MSiFCCHJ5qfA6ZnOIL6hJZ4tBd9eaDqIbuvnsUIZ8KDUCEZZimK7vyTQGW?= =?utf-8?q?Ia5fmvAl4ul4YojLs8hqTdVTLfEzU8EhqW11P6aEiyst3GOw0cIYheeHUeq4MjQ53?= =?utf-8?q?ZHjpy3RrwbTzS8Ju0I2FnKdt3CStrrlhYSY2IxeWpRIiRw2dlGtECjiKQOXw23eEy?= =?utf-8?q?eOIPJSlK/SrKpX858dSme6iJU36f9skRRTTz7TuChDb5iUXSLOL7rygYaFOyvZIR8?= =?utf-8?q?wo2PveCE7WH8FYaO2lVnf8qNyYAhmxIvGmhtJzvhjQf4ZBR1sI/1Z6LXuOK/nxCSR?= =?utf-8?q?c6yJkcexgFA1yWWMr7f8q1UcnwrtlQuB387zgkF0bU17uNYttjozMXQpvJ2Iq6exw?= =?utf-8?q?7hPkFyOzo4P5HBPMkIgbeLX2kY16C5Xzsh1aw+1grpD0i8G/K/Fr4XveX8uPPQCQY?= =?utf-8?q?kcs5yvZxUf//kjHLFkWi6Df1YS8RZY5XLs+tHeTIG1POlKkXBlWj6W7Tn2lGPvJjF?= =?utf-8?q?e3zH/9uAu03zHw6epHN856bR7zV4LTZoaUZBjEwsxwAGuzwT26LxoBNtgKhfdieuh?= =?utf-8?q?KGO53hgL2nr1GC9jBkEwbI65CjsC+fmfRq73Tha67tnmDCmahi8GZZidvnCBUuOc/?= =?utf-8?q?AzIH0tICWbHo4g6AfLrxVvxChju0785RfsKwlRz0sr+uXU4U6P/m7XwgEToT1WlHF?= =?utf-8?q?0DMJ7a5ddWEzfP7Il21iPNuSRkUZBHVOreHaA7huf5bvP9qE3kT8wUpAoslthgY9t?= =?utf-8?q?n152Ukqdk5Ah9vV7H4TC5+50gT+rtyWxYrgO6CW0ufVeZ0GsN4Q6KFADFD85u4r5k?= =?utf-8?q?WaVtLFsZ6UH2gb5cyVMwa4sJj2/ii2wqvyWSKIH5GNh0hDFredQh/NyDr2tQCxoku?= =?utf-8?q?RVA95JqA+Y7W+APjzwbiHfGVkhzmMfhL9HqMcXoc0mkv4kGL76edqWTYGZkV7iVqj?= =?utf-8?q?9BJT/jOfDpQfsM+PHf1+2j9tEO+bu6TN7YIlnmuustGNbAvnmjMRK0REc/ibvmnMA?= =?utf-8?q?CG+r92X4xEBLjMgP3w84UXDl6lBFbNsNDT4HeF7ubVxz4YxSAlSHqShVnyVJAAErQ?= =?utf-8?q?8NK8DfRXkpZlfOoocfzwQnUQ+5kZGjKng1ZeBLyvU5qJRvUHHJ0egmyI9jqkNsYC2?= =?utf-8?q?w1RNv89n7+20w9xyEbYtVP06UGpZwtxcSJDuH+Ft2p82H8c7fjv/DRa7521VGupBR?= =?utf-8?q?rSvCmZlbUZZobLG7LeXmWrkJEEAUnkyzWLrZT9n8WsPfab0Lj/1nvjpqREPfYmVOU?= =?utf-8?q?+/2aNSFkkcCGzCxXxshJtQHzjfIVqcRkFHI6TnOnDvbCpsnYwXUSVVVfmZlwmgdq/?= =?utf-8?q?SYNdUzTCyE+9GXl8OmBZ4H+dwtoLn6px1cdR3WUSJrJ0/GHGXgjzvXAjAA6ZK0+3o?= =?utf-8?q?67+VRwzDUOCn?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3ac895f-95d4-4979-932b-08dc3c89474c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:48.5028 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lw53+BLpO8tBROvtUoaZxsW3Gb5cUrWKzAYYAvBpCGvrZpyEUW2C/9+LAepmLNNwjj3JEW9/UjtOguL+6K8RVA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 Instead of using the switch case statement to enable/disable the reference clock handled by this driver itself, let's introduce a new callback set_ref_clk() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-imx.c | 119 ++++++++++++++++------------------ 1 file changed, 55 insertions(+), 64 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c index 4aa5f054d91c8..bff6212c617b7 100644 --- a/drivers/pci/controller/dwc/pcie-imx.c +++ b/drivers/pci/controller/dwc/pcie-imx.c @@ -103,6 +103,7 @@ struct imx_pcie_drvdata { const u32 mode_mask[IMX_PCIE_MAX_INSTANCES]; const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); + int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); }; struct imx_pcie { @@ -585,77 +586,54 @@ static int imx_pcie_attach_pd(struct device *dev) return 0; } -static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) +static int imx6sx_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - unsigned int offset; - int ret = 0; + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + enable ? 0 : IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); - break; - case IMX6QP: - case IMX6Q: + return 0; +} + +static int imx6q_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + if (enable) { /* power up core phy and enable ref clock */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); /* - * the async reset input need ref clock to sync internally, - * when the ref clock comes after reset, internal synced - * reset time is too short, cannot meet the requirement. - * add one ~10us delay here. + * the async reset input need ref clock to sync internally, when the ref clock comes + * after reset, internal synced reset time is too short, cannot meet the + * requirement.add one ~10us delay here. */ usleep_range(10, 100); regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - break; - case IMX7D: - case IMX95: - case IMX95_EP: - break; - case IMX8MM: - case IMX8MM_EP: - case IMX8MQ: - case IMX8MQ_EP: - case IMX8MP: - case IMX8MP_EP: - offset = imx_pcie_grp_offset(imx_pcie); - /* - * Set the over ride low and enabled - * make sure that REF_CLK is turned on. - */ - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, - 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, offset, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, - IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN); - break; + IMX6Q_GPR1_PCIE_REF_CLK_EN, IMX6Q_GPR1_PCIE_REF_CLK_EN); + } else { + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); } - return ret; + return 0; } -static void imx_pcie_disable_ref_clk(struct imx_pcie *imx_pcie) +static int imx8mm_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) { - switch (imx_pcie->drvdata->variant) { - case IMX6QP: - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, - IMX6Q_GPR1_PCIE_TEST_PD); - break; - case IMX7D: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); - break; - default: - break; - } + int offset = imx_pcie_grp_offset(imx_pcie); + + /* Set the over ride low and enabled make sure that REF_CLK is turned on.*/ + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE, + enable ? 0 : IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE); + regmap_update_bits(imx_pcie->iomuxc_gpr, offset, IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, + enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); + return 0; +} + +static int imx7d_pcie_set_ref_clk(struct imx_pcie *imx_pcie, bool enable) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + enable ? 0 : IMX7D_GPR12_PCIE_PHY_REFCLK_SEL); + return 0; } static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) @@ -668,10 +646,12 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) if (ret) return ret; - ret = imx_pcie_enable_ref_clk(imx_pcie); - if (ret) { - dev_err(dev, "unable to enable pcie ref clock\n"); - goto err_ref_clk; + if (imx_pcie->drvdata->set_ref_clk) { + ret = imx_pcie->drvdata->set_ref_clk(imx_pcie, true); + if (ret) { + dev_err(dev, "unable to enable pcie ref clock\n"); + goto err_ref_clk; + } } /* allow the clocks to stabilize */ @@ -686,7 +666,8 @@ static int imx_pcie_clk_enable(struct imx_pcie *imx_pcie) static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) { - imx_pcie_disable_ref_clk(imx_pcie); + if (imx_pcie->drvdata->set_ref_clk) + imx_pcie->drvdata->set_ref_clk(imx_pcie, false); clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } @@ -1463,6 +1444,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX6SX] = { .variant = IMX6SX, @@ -1477,6 +1459,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, + .set_ref_clk = imx6sx_pcie_set_ref_clk, }, [IMX6QP] = { .variant = IMX6QP, @@ -1492,6 +1475,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, + .set_ref_clk = imx6q_pcie_set_ref_clk, }, [IMX7D] = { .variant = IMX7D, @@ -1504,6 +1488,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, + .set_ref_clk = imx7d_pcie_set_ref_clk, }, [IMX8MQ] = { .variant = IMX8MQ, @@ -1517,6 +1502,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[1] = IOMUXC_GPR12, .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM] = { .variant = IMX8MM, @@ -1528,6 +1514,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP] = { .variant = IMX8MP, @@ -1539,6 +1526,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .clks_cnt = ARRAY_SIZE(imx8mm_clks), .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95] = { .variant = IMX95, @@ -1565,6 +1553,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, .init_phy = imx8mq_pcie_init_phy, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MM_EP] = { .variant = IMX8MM_EP, @@ -1576,6 +1565,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX8MP_EP] = { .variant = IMX8MP_EP, @@ -1587,6 +1577,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_off[0] = IOMUXC_GPR12, .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .epc_features = &imx8m_pcie_epc_features, + .set_ref_clk = imx8mm_pcie_set_ref_clk, }, [IMX95_EP] = { .variant = IMX95_EP, From patchwork Mon Mar 4 20:25:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581190 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE6AA7C0BA; Mon, 4 Mar 2024 20:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583956; cv=fail; b=TXnRV+hxtbImjmucR7VW6I9/gxJcF8Jqcx/uJ3AH08guzWSjM8Ic2NjTmQozFlKFF3uNZL1WJehXeeaWl0F05Pes9NVLwsN41bnfqHiFHxsAxcy6+YVhtd0vEiyOo9mOa/IfhZf5cvfQ3R/qi3EpsoeKVJOYPll3FAEkh67XHLM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583956; c=relaxed/simple; bh=yxG7AGjBMuePy4Pbyyz5wGDbAp0MgjoJQfLnxXmdHok=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=EWTYiKhxQEHyvuke+Yz97+r9QUgeoLIYb225KhtYh4EBR1HdxRnAL9T791iNYpXgs0W9PVehHcCrcAHJnQmolYZa9igP7FRZ4sGxx5KRqEH6P+iH/V49q0GSUOnbalfHfQMt2pb/kuLND9nT12cIqS3U0WEoy62MLPWJt8HlBEI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=D1rYGIEH; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="D1rYGIEH" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=PHwjtoiYfVr0nTXpVvLJ7qO20dM/sriTm8JHKbjNnsHP5RQzv/axqNpYem+2A2sMBMQeYlx+0/lZ5eSjQkl9dEqliB24FXsxA5oswYm0FEBZDSPF9kEtnaVzo+7YC9QTCXJy88ZjOu8sPxgeQqAJisQznAsj4uwP74b+SXf+4c2pLBj2UKYUkZ2FyoLtJ2raDN9tscB+i7NQslfAggZOJ5TxcLyVcdFuao3+Wkdm10kIxIOgE1YC+uZikDPEcxYt3KhffHIMDYF84Z+7NvKWC4QkwiD0GEsstiEj24HHmaEfE4FJzIMe0coBrWVnq1tcRudZWMtJVblKlaM9MAfRfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Fr23l1BE/BC2PYVi1QqvOfijpDuQUmU1u/gTjcILKq0=; b=ZMOZMmYUQYqZBI7RnTgtw7f/mQHj7XMI8cCvMtodrB5n+fLssZ6KEU4T0b69osHAJa6mmV4RLS+zlJ96EixgUgI6Qx4s7ErDf/kVh5Obyh2evTlqKbY8y4fk7jQ2KVxm2SoGqhDtXJ2MIj69sOaiBWtpbcqHIAUJZIv2K5fZbhN7adDyJEPRYQRKvA0ybljzTJBneks/hBAHDC/WoNr7YkUuWTeFt7HKddo05lToNJwIvMRhvVgks9Y4sefga3GgtzNmR6IHFgYPGar7Tc/58cgUkQtQaq4pRcCscFb/BDC1hOuafAoSDypYffmdLyuPNjP/jlI56q8Ow+ge4A1upg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fr23l1BE/BC2PYVi1QqvOfijpDuQUmU1u/gTjcILKq0=; b=D1rYGIEHOkJVyYsCz11BqG0XP6h2xBnsFCnVnO94VY/JU/PpLej1kyj0aGi7b5VMracN/Ler0VlJvQxxroEu47Q3IW8opM+NJSvimx9A3xD+nSkIWBoV/GUHru+Gr19T1fxWiDXFKuQYJ07qhsFcpGyEW+aero/qkgwolLqI0ZU= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:51 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:51 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:10 -0500 Subject: [PATCH v2 5/6] PCI: imx: Simplify switch-case logic by involve core_reset callback Message-Id: <20240304-pci2_upstream-v2-5-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583933; l=7125; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=yxG7AGjBMuePy4Pbyyz5wGDbAp0MgjoJQfLnxXmdHok=; b=Yhxo7qU9NIeBNHL5u9S02A03ulsLVGdz/YlmW0HF82CElxMuXvoQ99C0ae+8myqTrWiVHOwGF 2/Vo1EB930yCCiocYULnh8ATzDX2VlTh6SSQJq68jwPlrlyXgcf54N1 X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: f92244c0-e2d6-4b4a-458f-08dc3c894923 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3f3odW/9d6sLKvkUidyI2hMKTzxIQbkeWiL2Tl2qMb35HLR+RL009fYPmw1KqNT6F0LJOhou0yHnDvHrwqIx6tZOSvHFuHfNiY0fFFSDAx3WSSAWJ7Vo9lvCUDIRH8Gg6Y/Ahtp/7Zzj87JO1pbkUA+f1DLQXAYTFMEJ+MJ389C0yjS7K+K4LA8DRb7jtfZIY2oQttXwf+Cf7NQN73Uf8Qtr3+Q+FCEYA1giCNM1gs1zy6qBmUfcb7Lhp4OWoeO6Xg1oK4tkP8ZTj0a0Pwy/zrf4Bc+cWXHGITK38rKE0x3qMYVScYTnjjInK1sV6liSNg2RMhn3oTUoc1XJBXDn0OEW5gnQuAuZK/fsfYLjlLxvzt4gFDohQ8YpbjpjU18d+Ab+jHPEZHd2fT8u+GwxLRm6jHAuTLF4jyNmJJl4QRDsU37zZv480WZHTDgCnDaWU5r1sU1NDau1WKx1yN0QdS+y7SMMXYTNyskHBtEIHN+QQeti5p7eeF79dMkW+LG7gsxCCDCeaVd95yC5c+EgAes+RcSThKRuSKlyQgsu2AkIl6zifNlobjM1jBh7OClqS8eT/KZ2gC0dExT4XNybFhjyYMzQmyW/81UrmBtSobFZ5YEVks2cCPAsqNenqsVOzxQDN7gCOm66DxVHXe8CvFkUmf47Gd9hJhQC/JXJWMJaX4rAfm4RIQP4M3POW2mewJtS7cgMM9SN/3Jhlua1QqZDqgXrnMpi8y/b9A3a49o= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?8ooVIjUklhQWEWH83f4WUsqw1arY?= =?utf-8?q?zOHNBuuWSMsKGqgih7jrRfy2AXnf7KBwHx4QexaqbvBiYepEoLA5CI4Hc2dS6QKXj?= =?utf-8?q?ggCoatJUUZFia6PSFxGDI7FwBLRyWSNgFiimj8mEuPlfZFgEgUpq9F+2n/1pByUgl?= =?utf-8?q?FsTvhcT8lWUUftWwZfe2bigLiSWDYdYA+rJkom54QB9Sd7SHC5oJfnQHh+laK4Zzj?= =?utf-8?q?fiiEUaY8yAo/zte23Sm5pXNlWZXdYnSIlaY/TLSTUBrxYSiYG8WFtnmXRENxoZK6P?= =?utf-8?q?Fpja8BcxD6r8HokpH4seF9PHpv8h8MAhN717djTx7MUJXlZOuVP9VS2HBhtautq4a?= =?utf-8?q?qxnjCIebErfX4Q6GgRjR69aWHasnRYdU6vq1mCgMxSAaRQZ3cOjFWu5ktE3cppFoO?= =?utf-8?q?hJ1kvXDuu+kIDtg4kSZYrXagonVqD1VwAoGnQG336V29RZqqZHJNNpqMj4FznsCfa?= =?utf-8?q?HIe4za71UMWQzjDMrxK5whZ9hnuOXn8zG/ZjBfy342f3QjigUbJPEYQgrrhxVM/ZK?= =?utf-8?q?Hol/a6hdbt1REneyPWj8HarEynDzZW6Iga7gpSN3vsHeJRn+dq56yFUVv3mmwQ/CR?= =?utf-8?q?LnI4bexbPV0ty0SZ62iZkItPI7JNJkfUUCHl0cf3xU6u/g5swTGzd26O+vFDGImry?= =?utf-8?q?y92SG76hYt4tXxTAol0SW5VCN1kL4LcJOdTQHD6gwfkiiNAI10YGUybuOFE58KBYg?= =?utf-8?q?/NacxVNs5k5kvemnKGDkGgFMomAzWyvkAUZ22FVKmktaKV2uBcACNJGQSAN6skS6E?= =?utf-8?q?AJb6hE+nNlxxXZyX61OF4S/iDb/zFntujW1DrYGGPMFugL/CCS4EMpeff1oBVJT+M?= =?utf-8?q?0Q4t4XqS5O3njX8EvFWuHPTTxHPt21uHMDbvXhdChGrU6CjkPyK3Z6NlWmIhscntG?= =?utf-8?q?5A6wsWgPMTPYmtzQK5Lr5eTrtkAnwufZP050oFGVyOWXV/hwf5QsrzZd/PObtzNHP?= =?utf-8?q?ba+z9oI3v6xx3FbpncvRufK/zPcV2GkT7w0Sm5njpSI5WBIgNnudlWbm5OfG0aMir?= =?utf-8?q?yFv9kV84baX6IMvfjtsA7nZ4aJoSzwT8+H1X5quD3hTwj74EpchNxAwo70tCMJDva?= =?utf-8?q?4178tdpH6uP3VRfvSBjOjyntXnwKAbkmpHYUJv33hwSUZM0vhCEoweO7/Ylqi4Ks2?= =?utf-8?q?fp/Y8ysBUbn/urJRn2/6RYWD6irrpmdMQdJT0q1lijMsC022XOs4v3d4YsrfZiTxS?= =?utf-8?q?Fk8MqT6YMbLbZb2oho9YU6py453M4agwB9vBHlbViAkHdmv6fm6r381/VAKH+iH5S?= =?utf-8?q?PFWfoPBMxAuwQfHOcT23u7igRNfNgaDs3o9Vt5YIE7PhRpu9cvzKf1wp+6NZTjnKC?= =?utf-8?q?m7IU1RJgRSH2DbSY6lyKrkFnOQoS/MkD4UJ4HBu+DSPq9MCEYppEwDDWJNUdp+i/g?= =?utf-8?q?5SQXStzwFJNsfMEy0p4xl4lvtaH+M2CQo0IOYCh2lb82zCtETJA976FFG2ywBCPPj?= =?utf-8?q?1XANSMVZmRZUqOEUI5z7BPeKwvhIweK8SShEtmUSbea8JatLxowG8uifKUwrdEyXm?= =?utf-8?q?0tc+PBbviPA9?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: f92244c0-e2d6-4b4a-458f-08dc3c894923 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:51.5763 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: O7eEujS444VtoXPhcKOMBAqlxEx/MaA3JbHVXtgjvTPagUA+FbqPfkTVav8Zv+5kebQu+qwADsEhmXRqLIg7tQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 Instead of using the switch case statement to assert/dassert the core reset handled by this driver itself, let's introduce a new callback core_reset() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-imx.c | 131 ++++++++++++++++++---------------- 1 file changed, 68 insertions(+), 63 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c index bff6212c617b7..922bbc0bc1bcd 100644 --- a/drivers/pci/controller/dwc/pcie-imx.c +++ b/drivers/pci/controller/dwc/pcie-imx.c @@ -104,6 +104,7 @@ struct imx_pcie_drvdata { const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); + int (*core_reset)(struct imx_pcie *pcie, bool assert); }; struct imx_pcie { @@ -671,35 +672,72 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_TEST_POWERDOWN, + assert ? IMX6SX_GPR12_PCIE_TEST_POWERDOWN : 0); + /* Force PCIe PHY reset */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); + return 0; +} + +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); + if (!assert) + usleep_range(200, 500); + + return 0; +} + +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, + assert ? IMX6Q_GPR1_PCIE_TEST_PD : 0); + + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN, + assert ? 0 : IMX6Q_GPR1_PCIE_REF_CLK_EN); + + return 0; +} + +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + if (assert) + return 0; + + /* + * Workaround for ERR010728, failure of PCI-e PLL VCO to oscillate, especially when cold. + * This turns off "Duty-cycle Corrector" and other mysterious undocumented things. + */ + + if (likely(imx_pcie->phy_base)) { + /* De-assert DCC_FB_EN */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); + } else { + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); + } + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); reset_control_assert(imx_pcie->apps_reset); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, - IMX6SX_GPR5_PCIE_BTNRST_RESET); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, - IMX6Q_GPR1_PCIE_SW_RST); - break; - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, true); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) @@ -709,47 +747,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx_pcie->pci; - struct device *dev = pci->dev; - reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx_pcie->drvdata->variant) { - case IMX7D: - /* Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. - */ - if (likely(imx_pcie->phy_base)) { - /* De-assert DCC_FB_EN */ - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); - /* Assert RX_EQS and RX_EQS_SEL */ - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL - | PCIE_PHY_CMN_REG24_RX_EQ, - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); - /* Assert ATT_MODE */ - writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); - } else { - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); - } - - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); - break; - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, 0); - - usleep_range(200, 500); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, false); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) { @@ -1445,6 +1446,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6q_pcie_core_reset, }, [IMX6SX] = { .variant = IMX6SX, @@ -1460,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, .set_ref_clk = imx6sx_pcie_set_ref_clk, + .core_reset = imx6sx_pcie_core_reset, }, [IMX6QP] = { .variant = IMX6QP, @@ -1476,6 +1479,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6qp_pcie_core_reset, }, [IMX7D] = { .variant = IMX7D, @@ -1489,6 +1493,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, .set_ref_clk = imx7d_pcie_set_ref_clk, + .core_reset = imx7d_pcie_core_reset, }, [IMX8MQ] = { .variant = IMX8MQ, From patchwork Mon Mar 4 20:25:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13581191 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2076.outbound.protection.outlook.com [40.107.6.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B5727CF37; Mon, 4 Mar 2024 20:25:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.6.76 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583959; cv=fail; b=coY26wFtwCjQLyY2nMCuW0oeKgfp50iG6ZPDtCDQbMIznKRJ4eRETGcMh4BphjJ5X+Mor8s37RySZdJGFKdD6Hgqyb1aXPHfOBrtmN+CLDo78sWetwtZ4dceOI1mcay57C+R3TFLW+xIN19QuxixW5YWnk35Gpuwrf4WiXRYRlY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709583959; c=relaxed/simple; bh=GXfso8sA5qp7WQ2bfpwfigNswIhAFh8mC0bwdOHPDh0=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=pLI9y6BL35iwk67Wz/1Y3FyxbgL/3WELblOKknmX+WcZdZCJcNz2c2H0TX7FKLKra9Yl2SctGFUCrUEcQqdO6SjHf2dRgasE9yxY841j76pIc9CZafRsrc7ghJtN4CzFot7+CEdswIx2nOwE2Ovc3sXrZScFDzQkvdDiNq5A7f4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=djbE8XSy; arc=fail smtp.client-ip=40.107.6.76 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="djbE8XSy" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=NBtnZ94t3VtfSfmPb+/a9s+oNEKYbd5tevxaJkKp13kBWUcIjepgXAjLtj+A26DzXFOasurICv1BKtuh8QkGQ51O+JbvGHFJVU5QCf4KkRRSNLaNInWfOGzZsTIoVw39CiZkxU1aK/nF1Lqg5HB8L7YteZw6LGXiWz68tsaahTixhV5vnjDBK1YC0n+BeFwYvbztJDw3g5jQt4BbKcEvM4yxWa6Dv8Nu2+pCJRA12nIXL4Xo6uRwrk5hZzz2MOls0Q7on9a1uvFywfNJjSOSqr6/TgIn5nGzlQAlgUJiS9h47lhU6QMxKYL0mX5FGdMXVHEYJYlCUc2phw/4MTo4Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KFC612DWNogn7Jxn6vEo/HiXWDydVNWP/fr24H5+PKs=; b=aVPnqQ9i893UAqJEyIZLL40c5XnF53DODScXlDQGvb85XqaNsyTEh5okQjATt5voPFXZiEuidaoctMhWCGruSKVOOb7JXfSTvEDIlQD3MCjnTL2u7Xi2DuWI7noDW7ru3wjCynqjS6lmi/fOqjVtFG6fbN9gl4XyioV0heV4gqKJg0GR4znTD5X9iIio5v5YE5z91n6oVPuUSu0jWsps6zYSOPDAX8llJK5cHdPx4T2RWllV+DPpRurSZnU1mtfV9MYMRJsAC/PLUsf+g+Xl/ntncKNRnY8nNzqRz5i2TqJtrsJKNL5rUG7gMTDg6/kPbEcaxT8kZIa4PHUqFzDXhA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KFC612DWNogn7Jxn6vEo/HiXWDydVNWP/fr24H5+PKs=; b=djbE8XSy40VuDlSqSACS39+KynmI5BNEI1RmckrXa8Wh8yBuoG1qjlY9yeR6VoHQ6n2qWw3GqN4iSGm0lW6owBXX+mUChkkz96XxvbpmdEOHbF9bre2zWHP5mszRgBQdMwCUlQT2K6mLeI1opM46wnOBrcIvK+TboV2RwKGh+5o= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DU2PR04MB9083.eurprd04.prod.outlook.com (2603:10a6:10:2f2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Mon, 4 Mar 2024 20:25:54 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::3168:91:27c6:edf6%3]) with mapi id 15.20.7339.033; Mon, 4 Mar 2024 20:25:54 +0000 From: Frank Li Date: Mon, 04 Mar 2024 15:25:11 -0500 Subject: [PATCH v2 6/6] PCI: imx: Config look up table(LUT) to support MSI ITS and IOMMU for i.MX95 Message-Id: <20240304-pci2_upstream-v2-6-ad07c5eb6d67@nxp.com> References: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> In-Reply-To: <20240304-pci2_upstream-v2-0-ad07c5eb6d67@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-c87ef X-Developer-Signature: v=1; a=ed25519-sha256; t=1709583933; l=5959; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=GXfso8sA5qp7WQ2bfpwfigNswIhAFh8mC0bwdOHPDh0=; b=/BODBiAWSltekFpoApfBqVCVfOyvMVODknBBkZE2LfnIoq2XL4uc3x4pvCOMXWd2Qg4zNNBg8 RltNGi77heTBZf/D3HxaTODEZauteSs1LOoLUKAbXe7UhHWFjrZsZom X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SN7PR04CA0118.namprd04.prod.outlook.com (2603:10b6:806:122::33) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DU2PR04MB9083:EE_ X-MS-Office365-Filtering-Correlation-Id: 21d08db6-f48f-42ce-ca71-08dc3c894af8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Sve3JJI8SmnqG8wtlA4FrcwX8CTBGKIUSRL3uW+gBhvw19k5Gt9+1MW3UoIMsz7e8QTELyLqRYg2osl5OrjGHZHM1YGFCZ3AvwoCLy/VW7oqQcuNJ0+es4sjeqbrEMmXBlcOrdjYR1/g2JysH//q/xYUq+F1M9noE3Ny6TmI67o+nr0TdDYkZSRFP0iZ3Ra08rvebCX04gfYKAEv/R0fZy0D/N0cNW54edOf/IuVieIyrvl6w4dLC1qxpq3Vv2Bkgmmw1XWfRc8QCo/1v99rknGJmDW35ipxa8rCoWepctKBWhndR0QRgJH0JTSed/4f2Tl/B8lx/XlD63nWacnyf1aaR9DEByf7cWtCt7NCPjF0yByCr4xCWoaGo8uZtj9t10GOnbWtF0ATi4NAs4ScfYgsEZwA2QP+zC4rR7M1M2HtSTdkDKOWsbrOM6Lx1qZpY/4q22KceGU2GSSdvyQbbi50GNEXuHneUFzTnDZgujsLxyCA4jBgZxPlGPauOjZRIGIkUsGBzRB5Q2Nmz+Gr2GgPzviwYAiNt2UTM+7odLuNAVz6xH/MtYkEEH9wkjBQq8pgBRm+UUg1qEL9dXyKSoS0X80a0PZWubefivSxGGJgp7r8aiStPyeS50exEj+HcOyqq/aog4o4cmc6oiNYTvWDZezXJBq+0YunNoBbbCt5YjVXDqQVLdOBlvwyiQOPEGYN2uTkRleF1ZBHu1IOKvKhF9udl/AOJBiL/uJfslw= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(376005)(921011)(38350700005);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?qpTkspNu9lgCzqo3XUNCFoDkt7Nn?= =?utf-8?q?QSqNMarsuwF+U609+g5Auv1lbQMzeO8mIrgx6PcB9OHK4c5tyy8NlbV+ccCsZh1xT?= =?utf-8?q?nmChdrFfVXik5KTNgMXkhSC04x1mTJhLbwWko3JI2g4uI6iCPagdNWpiNmJE0aq4K?= =?utf-8?q?irq1sfr0gPFohrtrG2zBjOHRPdT9nU5G3kH8A9USDxhp+5deeD0Am/BpItxQN1zg4?= =?utf-8?q?KPuGZSplDicHwRzizJOU70cKniyb09n8ghPRCy6PgAa6XZ23utW577mCeF11ptXuT?= =?utf-8?q?knXOfCn6kYaCBKLr41/ppDLFiF1++GvKPdHQD56I2ubSg5mQpaWoLZ9PMckoYYJih?= =?utf-8?q?5oPjNJ9ZnrYoW2CfkOhIABst0jgmvGMxbr+1Qt95uwn3mfB9Qgm+UPevt1B1MqVB3?= =?utf-8?q?JGRmJ9BIsw2PsuZJ8VvAQ0IqOF4CUd0fdBht9+VfhD7RAP0Re4Uqhp/yRrNhslH7V?= =?utf-8?q?FuNmI15OL9Tq5Ii6sEORZRhITyyb6z9KFCimJa0bL3jXB3H9fbCnrfGNoGd7u1SmS?= =?utf-8?q?vg94MxyQ4omn6BFwJupeFQeGfFmS0x0dDUFHZHFv16PuydTNE3hHNVydgR8u9e3mo?= =?utf-8?q?QqiFCDV6asnsm3KBlTOdH8Wxx7pY5MwqM7JDH0hyoTqsmYTVDUbCjjSzivbOhqKe3?= =?utf-8?q?pBMQ07lctGihh8/Zy4aBrGPOnHakp412NUtGHx58n8NYqPgumS4jRvS989VDvJ3Kn?= =?utf-8?q?w+lAKRT7k4R1iVKhOwstXT8rzSHssNmevsF7+1BsyW43T957s3USXak8ulLgte/gC?= =?utf-8?q?74i5iTyQ5fbQMSEbuQ3kvxI77DDmfBaWDi/jM267gmmmBFSqyX/HhuiKp1hq2bwsm?= =?utf-8?q?dPimIZoU7W+lr+WAYiU+p76iU+ErE5lBPOoEkIKqABHPyHWvc1OEf6X3GmQGhbdIq?= =?utf-8?q?mcYechJRtQ/fC0QAy1LtLCk9e97gDjBLtyLYiHh/hlT+NedlyFzF9+s8H3N6m67OD?= =?utf-8?q?POOe6KgZoPvsrakLOwF9BDlQOo9idfUIUEzsOLx/wN6EdqSza+TZw3qZ1Mmmlxw23?= =?utf-8?q?kl3XXDP3mRwoUBUbwtF5jvBTYHJrd48shYV5fsVp/ToKK1/uVqdmjpc+r0xTuC8Ji?= =?utf-8?q?vvjSAdCNlh+cfkrEUnhvJnSJ/0fol9yYMYeMiVD5L7k5rWNDF7EkknzG+4vUVH9tc?= =?utf-8?q?JfVYoy2elJ0jJC6CGzpMFErzau+YSClXXgaRJIoY00al2u/8ysDLV2qZsgzuoAvJV?= =?utf-8?q?vNFr8G1hHm4lxfqB1l8b0U+1Ps9aDIMx5FoBRSjs8maL1Z6/cGpiNLNr6uPa9N6IY?= =?utf-8?q?lonl2bC43i5POdHy1esH7SiUQqAs2FoW1eodC9FvKzqhZmQnTywP65XMgOGWsLw3B?= =?utf-8?q?DplT/OFpwvfaLXoflzRcVr+pUzQAdFKdcWnT8ABAWb+VBK1pvz+BWO29hjmflMb7i?= =?utf-8?q?gn4P7PXembfH0jmirvs/J3JFBYgOPO/G89O9+gwMV2rzeGhtB3nb85kSIDCG2dR2/?= =?utf-8?q?TaVeZhB476aJAg6ZtI2b6+TIrcDkXJFl5amWodJ1KNz4UpUrbBYaMXQc7OkIyiuz5?= =?utf-8?q?zHFkIRORKAv2?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 21d08db6-f48f-42ce-ca71-08dc3c894af8 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2024 20:25:54.6478 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lYTqjvqi3PiTgQ2qcZ6P93PGaAGAGRPiClz7bGKcNRyziTxKI3GsAYduOUlOxGT4zpXHJh2tLgEjJ7H8oznNvA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB9083 i.MX95 need config LUT to convert bpf to stream id. IOMMU and ITS use the same stream id. Check msi-map and smmu-map and make sure the same PCI bpf map to the same stream id. Then config LUT related registers. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-imx.c | 175 ++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-imx.c b/drivers/pci/controller/dwc/pcie-imx.c index 922bbc0bc1bcd..8b698e1ec3c9e 100644 --- a/drivers/pci/controller/dwc/pcie-imx.c +++ b/drivers/pci/controller/dwc/pcie-imx.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -217,6 +233,159 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) return 0; } +static int imx_pcie_update_lut(struct imx_pcie *imx_pcie, int index, u16 reqid, u16 mask, u8 sid) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 data1, data2; + + if (sid >= 64) { + dev_err(dev, "Too big stream id: %d\n", sid); + return -EINVAL; + } + + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |= IMX95_PE0_LUT_VLD; + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 = mask; + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, reqid); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, index); + + return 0; +} + +struct imx_of_map { + u32 bdf; + u32 phandle; + u32 sid; + u32 sid_len; +}; + +static int imx_check_msi_and_smmmu(struct imx_pcie *imx_pcie, + struct imx_of_map *msi_map, u32 msi_size, u32 msi_map_mask, + struct imx_of_map *smmu_map, u32 smmu_size, u32 smmu_map_mask) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + int i; + + if (msi_map && smmu_map) { + if (msi_size != smmu_size) + return -EINVAL; + if (msi_map_mask != smmu_map_mask) + return -EINVAL; + + for (i = 0; i < msi_size / sizeof(*msi_map); i++) { + if (msi_map->bdf != smmu_map->bdf) { + dev_err(dev, "bdf setting is not match\n"); + return -EINVAL; + } + if ((msi_map->sid & IMX95_SID_MASK) != smmu_map->sid) { + dev_err(dev, "sid setting is not match\n"); + return -EINVAL; + } + if ((msi_map->sid_len & IMX95_SID_MASK) != smmu_map->sid_len) { + dev_err(dev, "sid_len setting is not match\n"); + return -EINVAL; + } + } + } + + return 0; +} + +/* + * Simple static config lut according to dts settings DAC index and stream ID used as a match result + * of LUT pre-allocated and used by PCIes. + * + * Currently stream ID from 32-64 for PCIe. + * 32-40: first PCI bus. + * 40-48: second PCI bus. + * + * DAC_ID is index of TRDC.DAC index, start from 2 at iMX95. + * ITS [pci(2bit): streamid(6bits)] + * pci 0 is 0 + * pci 1 is 3 + */ +static int imx_pcie_config_sid(struct imx_pcie *imx_pcie) +{ + struct imx_of_map *msi_map = NULL, *smmu_map = NULL, *cur; + int i, j, lut_index, nr_map, msi_size = 0, smmu_size = 0; + u32 msi_map_mask = 0xffff, smmu_map_mask = 0xffff; + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 mask; + int size; + + of_get_property(dev->of_node, "msi-map", &msi_size); + if (msi_size) { + msi_map = devm_kzalloc(dev, msi_size, GFP_KERNEL); + if (!msi_map) + return -ENOMEM; + + if (of_property_read_u32_array(dev->of_node, "msi-map", (u32 *)msi_map, + msi_size / sizeof(u32))) + return -EINVAL; + + of_property_read_u32(dev->of_node, "msi-map-mask", &msi_map_mask); + } + + cur = msi_map; + size = msi_size; + mask = msi_map_mask; + + of_get_property(dev->of_node, "iommu-map", &smmu_size); + if (smmu_size) { + smmu_map = devm_kzalloc(dev, smmu_size, GFP_KERNEL); + if (!smmu_map) + return -ENOMEM; + + if (of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)smmu_map, + smmu_size / sizeof(u32))) + return -EINVAL; + + of_property_read_u32(dev->of_node, "smmu_map_mask", &smmu_map_mask); + } + + if (imx_check_msi_and_smmmu(imx_pcie, msi_map, msi_size, msi_map_mask, + smmu_map, smmu_size, smmu_map_mask)) + return -EINVAL; + + if (!cur) { + cur = smmu_map; + size = smmu_size; + mask = smmu_map_mask; + } + + nr_map = size / (sizeof(*cur)); + + lut_index = 0; + for (i = 0; i < nr_map; i++) { + for (j = 0; j < cur->sid_len; j++) { + imx_pcie_update_lut(imx_pcie, lut_index, cur->bdf + j, mask, + (cur->sid + j) & IMX95_SID_MASK); + lut_index++; + } + cur++; + + if (lut_index >= IMX95_MAX_LUT) { + dev_err(dev, "its-map/iommu-map exceed HW limiation\n"); + return -EINVAL; + } + } + + devm_kfree(dev, smmu_map); + devm_kfree(dev, msi_map); + + return 0; +} + static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) { const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; @@ -950,6 +1119,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) goto err_phy_off; } + ret = imx_pcie_config_sid(imx_pcie); + if (ret < 0) { + dev_err(dev, "failed to config sid:%d\n", ret); + goto err_phy_off; + } + imx_setup_phy_mpll(imx_pcie); return 0;