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Tue, 5 Mar 2024 10:52:34 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 414AC18009DB; Tue, 5 Mar 2024 11:52:33 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Tom Lendacky , Marcelo Tosatti , kvm@vger.kernel.org, Gerd Hoffmann Subject: [PATCH v2 1/2] [debug] log kvm supported cpuid Date: Tue, 5 Mar 2024 11:52:32 +0100 Message-ID: <20240305105233.617131-2-kraxel@redhat.com> In-Reply-To: <20240305105233.617131-1-kraxel@redhat.com> References: <20240305105233.617131-1-kraxel@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.8 --- target/i386/kvm/kvm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 42970ab046fa..7298822cb511 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -276,6 +276,20 @@ static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) exit(1); } } + + { + int i; + + for (i = 0; i < cpuid->nent; i++) { + fprintf(stderr, "cpuid: %8x/%d - %8x %8x %8x %8x\n", + cpuid->entries[i].function, + cpuid->entries[i].index, + cpuid->entries[i].eax, + cpuid->entries[i].ebx, + cpuid->entries[i].ecx, + cpuid->entries[i].edx); + } + } return cpuid; } From patchwork Tue Mar 5 10:52:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 13582087 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 718625C5E6 for ; Tue, 5 Mar 2024 10:52:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709635964; cv=none; b=ROMHP2SvMLq/0j+4k3HefUyng9hu38xz+Gj1hLshnU2oTI/NadoeJ+GPovugR5eFYDKuqCuJG8bQmreA5LmEm2Kp0bljClmwyHK3pBALWQM4WW9NgyNByTcfXd0qqtZJe6IGqUeTiLBuppH1z+r3yS4m2WHkCRIbrx25JPRnQ40= ARC-Message-Signature: i=1; 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Tue, 5 Mar 2024 10:52:36 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.193.36]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E34CF8173; Tue, 5 Mar 2024 10:52:35 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 530091800D5B; Tue, 5 Mar 2024 11:52:33 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Tom Lendacky , Marcelo Tosatti , kvm@vger.kernel.org, Gerd Hoffmann Subject: [PATCH v2 2/2] kvm: add support for guest physical bits Date: Tue, 5 Mar 2024 11:52:33 +0100 Message-ID: <20240305105233.617131-3-kraxel@redhat.com> In-Reply-To: <20240305105233.617131-1-kraxel@redhat.com> References: <20240305105233.617131-1-kraxel@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.5 Query kvm for supported guest physical address bits, in cpuid function 80000008, eax[23:16]. Usually this is identical to host physical address bits. With NPT or EPT being used this might be restricted to 48 (max 4-level paging address space size) even if the host cpu supports more physical address bits. When set pass this to the guest, using cpuid too. Guest firmware can use this to figure how big the usable guest physical address space is, so PCI bar mapping are actually reachable. Signed-off-by: Gerd Hoffmann --- target/i386/cpu.h | 1 + target/i386/cpu.c | 1 + target/i386/kvm/kvm.c | 17 +++++++++++++++++ 3 files changed, 19 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 952174bb6f52..d427218827f6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2026,6 +2026,7 @@ struct ArchCPU { /* Number of physical address bits supported */ uint32_t phys_bits; + uint32_t guest_phys_bits; /* in order to simplify APIC support, we leave this pointer to the user */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2666ef380891..1a6cfc75951e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { /* 64 bit processor */ *eax |= (cpu_x86_virtual_addr_width(env) << 8); + *eax |= (cpu->guest_phys_bits << 16); } *ebx = env->features[FEAT_8000_0008_EBX]; if (cs->nr_cores * cs->nr_threads > 1) { diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7298822cb511..ce22dfcaa661 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -238,6 +238,15 @@ static int kvm_get_tsc(CPUState *cs) return 0; } +/* return cpuid fn 8000_0008 eax[23:16] aka GuestPhysBits */ +static int kvm_get_guest_phys_bits(KVMState *s) +{ + uint32_t eax; + + eax = kvm_arch_get_supported_cpuid(s, 0x80000008, 0, R_EAX); + return (eax >> 16) & 0xff; +} + static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg) { kvm_get_tsc(cpu); @@ -1730,6 +1739,7 @@ int kvm_arch_init_vcpu(CPUState *cs) X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; uint32_t limit, i, j, cpuid_i; + uint32_t guest_phys_bits; uint32_t unused; struct kvm_cpuid_entry2 *c; uint32_t signature[3]; @@ -1765,6 +1775,13 @@ int kvm_arch_init_vcpu(CPUState *cs) env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; + guest_phys_bits = kvm_get_guest_phys_bits(cs->kvm_state); + if (guest_phys_bits && + (cpu->guest_phys_bits == 0 || + cpu->guest_phys_bits > guest_phys_bits)) { + cpu->guest_phys_bits = guest_phys_bits; + } + /* * kvm_hyperv_expand_features() is called here for the second time in case * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle