From patchwork Wed Mar 6 02:20:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kuro X-Patchwork-Id: 13583212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4F81C54798 for ; Wed, 6 Mar 2024 02:09:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0ACED112E0C; Wed, 6 Mar 2024 02:09:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=ite.com.tw header.i=@ite.com.tw header.b="iECa9yxT"; dkim-atps=neutral Received: from ironport.ite.com.tw (60-251-196-230.hinet-ip.hinet.net [60.251.196.230]) by gabe.freedesktop.org (Postfix) with ESMTPS id 63718112DE9 for ; Wed, 6 Mar 2024 02:09:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ite.com.tw; s=dkim; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZGM4CTvY0+d25ts8P1XACik2JTlfRT4G4KiIsDIO+0o=; b=iECa9yxTcR1CiuFx2MY4zxPYso0/S4KmXwNCr6EKMQx04aGuMw/DCCza NPJYV3VSMKhWqqHf4DgAXGzi9jOJC4SO2aepsnjqADzNX6+lJ6kxE7TiR k/JXkJKdWiAoqv2KSh3pT6YYONKVWlfsT/1EHXK23ofBY7XHRZUxLosCt dj0M7fzh9lODhDm/3jufe1JSHtt4LfKsPfuLxIWClwpVOw5k/GeU4K+Hr hmqwt3lCXcggeBR1gnP9jpDmzn2KH46Hq6L7YGW3cEjo85IApyrfa/VLt cpyj1dBbpJ1tbGc3HvN0JK0DyGttrbyEuT6QHfb5jyNHCDCbtHQ59i8dR A==; Received: from unknown (HELO mse.ite.com.tw) ([192.168.35.30]) by ironport.ite.com.tw with ESMTP; 06 Mar 2024 10:09:45 +0800 Received: from CSBMAIL1.internal.ite.com.tw (CSBMAIL1.internal.ite.com.tw [192.168.65.58]) by mse.ite.com.tw with ESMTP id 42629eri035636; Wed, 6 Mar 2024 10:09:40 +0800 (GMT-8) (envelope-from kuro.chung@ite.com.tw) Received: from ite-XPS-13-9360.internal.ite.com.tw (192.168.72.42) by CSBMAIL1.internal.ite.com.tw (192.168.65.58) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 6 Mar 2024 10:09:40 +0800 From: kuro To: CC: Allen Chen , Pin-yen Lin , Kuro Chung , Kenneth Haung , Allen Chen , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , "open list:DRM DRIVERS" , open list Subject: [PATCH v3 1/1] UPSTREAM: drm/bridge: it6505: fix hibernate to resume no display issue Date: Wed, 6 Mar 2024 10:20:03 +0800 Message-ID: <20240306022003.259245-2-kuro.chung@ite.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240306022003.259245-1-kuro.chung@ite.com.tw> References: <20240306022003.259245-1-kuro.chung@ite.com.tw> MIME-Version: 1.0 X-Originating-IP: [192.168.72.42] X-ClientProxiedBy: CSBMAIL1.internal.ite.com.tw (192.168.65.58) To CSBMAIL1.internal.ite.com.tw (192.168.65.58) X-TM-SNTS-SMTP: AB1182823ED4183B2573C8A499561AD63DC9946A6777A5F025F3089B587BDBE82002:8 X-MAIL: mse.ite.com.tw 42629eri035636 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: kuro chung ITE added a FIFO reset bit for input video. When system power resume, the TTL input of it6505 may get some noise before video signal stable and the hardware function reset is required. But the input FIFO reset will also trigger error interrupts of output module rising. Thus, it6505 have to wait a period can clear those expected error interrupts caused by manual hardware reset in one interrupt handler calling to avoid interrupt looping. Signed-off-by: Allen Chen --- drivers/gpu/drm/bridge/ite-it6505.c | 54 ++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index b53da9bb65a16..e592e14a48578 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -1318,6 +1318,8 @@ static void it6505_video_reset(struct it6505 *it6505) it6505_set_bits(it6505, REG_DATA_MUTE_CTRL, EN_VID_MUTE, EN_VID_MUTE); it6505_set_bits(it6505, REG_INFOFRAME_CTRL, EN_VID_CTRL_PKT, 0x00); it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, VIDEO_RESET); + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x02); + it6505_set_bits(it6505, REG_VID_BUS_CTRL1, TX_FIFO_RESET, 0x00); it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, RST_501_FIFO); it6505_set_bits(it6505, REG_501_FIFO_CTRL, RST_501_FIFO, 0x00); it6505_set_bits(it6505, REG_RESET_CTRL, VIDEO_RESET, 0x00); @@ -2480,10 +2482,6 @@ static void it6505_irq_video_fifo_error(struct it6505 *it6505) struct device *dev = &it6505->client->dev; DRM_DEV_DEBUG_DRIVER(dev, "video fifo overflow interrupt"); - it6505->auto_train_retry = AUTO_TRAIN_RETRY; - flush_work(&it6505->link_works); - it6505_stop_hdcp(it6505); - it6505_video_reset(it6505); } static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) @@ -2491,10 +2489,6 @@ static void it6505_irq_io_latch_fifo_overflow(struct it6505 *it6505) struct device *dev = &it6505->client->dev; DRM_DEV_DEBUG_DRIVER(dev, "IO latch fifo overflow interrupt"); - it6505->auto_train_retry = AUTO_TRAIN_RETRY; - flush_work(&it6505->link_works); - it6505_stop_hdcp(it6505); - it6505_video_reset(it6505); } static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) @@ -2502,6 +2496,46 @@ static bool it6505_test_bit(unsigned int bit, const unsigned int *addr) return 1 & (addr[bit / BITS_PER_BYTE] >> (bit % BITS_PER_BYTE)); } +static bool it6505_is_video_error_int(const int *int_status) +{ + if ((it6505_test_bit(BIT_INT_VID_FIFO_ERROR, (unsigned int *)int_status)) || (it6505_test_bit(BIT_INT_IO_FIFO_OVERFLOW, (unsigned int *)int_status))) + return 1; + return 0; +} + +static void it6505_irq_video_error_handler(struct it6505 *it6505) +{ + struct device *dev = &it6505->client->dev; + int int_status[3] = {0}; + int reg_0d; + int i; + + it6505->auto_train_retry = AUTO_TRAIN_RETRY; + flush_work(&it6505->link_works); + it6505_stop_hdcp(it6505); + it6505_video_reset(it6505); + + DRM_DEV_DEBUG_DRIVER(dev, "Video Error reset wait video..."); + + for (i = 0; i < 10; i++) { + usleep_range(10000, 11000); + int_status[2] = it6505_read(it6505, INT_STATUS_03); + reg_0d = it6505_read(it6505, REG_SYSTEM_STS); + it6505_write(it6505, INT_STATUS_03, int_status[2]); + + DRM_DEV_DEBUG_DRIVER(dev, "reg08 = 0x%02x", int_status[2]); + DRM_DEV_DEBUG_DRIVER(dev, "reg0D = 0x%02x", reg_0d); + + if ((reg_0d & VIDEO_STB) && (reg_0d >= 0)) + break; + + if (it6505_is_video_error_int(int_status)) { + it6505_video_reset(it6505); + DRM_DEV_DEBUG_DRIVER(dev, "Video Error reset wait video (%d)", i); + } + } +} + static irqreturn_t it6505_int_threaded_handler(int unused, void *data) { struct it6505 *it6505 = data; @@ -2522,7 +2556,7 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) { BIT_INT_VID_FIFO_ERROR, it6505_irq_video_fifo_error }, { BIT_INT_IO_FIFO_OVERFLOW, it6505_irq_io_latch_fifo_overflow }, }; - int int_status[3], i; + int int_status[3], i, reg_0d; if (it6505->enable_drv_hold || !it6505->powered) return IRQ_HANDLED; @@ -2550,6 +2584,8 @@ static irqreturn_t it6505_int_threaded_handler(int unused, void *data) if (it6505_test_bit(irq_vec[i].bit, (unsigned int *)int_status)) irq_vec[i].handler(it6505); } + if (it6505_is_video_error_int(int_status)) + it6505_irq_video_error_handler(it6505); } pm_runtime_put_sync(dev);