From patchwork Wed Mar 6 08:10:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umang Jain X-Patchwork-Id: 13583472 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6590D5D8EF; Wed, 6 Mar 2024 08:10:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712659; cv=none; b=hZeKdIVg6q0Kh8gDBudg5klVu4WXd4+XvOrwq1GAU42bXirhP4ZSP7g1uOiYQr4rstuOQbdjeszO8/aHuFzbMm9kVr2X6LDm/MzRp6ct9rGVGDmxxi41b3rBRdxP406Nv7MKGGzj8l+UsP0g7MtGA1QtC7xx84WZFQNzk9UpxxQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712659; c=relaxed/simple; bh=wGmZeS95RXhE+ygELn87/BTnIoLY5pTdpYLkP/kMeYs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XGJtx67Pqhh8zpfKSOoexJFbsSO9O0cLX2s+PXjpWG/PT6a5JDbAGTU6qRzOOrbVX8IqlsiUoWZqwn9z3MWPf8+zR6t5QJcoIlPl96AOXEUfAduk4nU7EvcFFezJMBFyFP2uyOFUHeQgV6+2AIc2qQGdBTUr4jQ4h0ZG4SLFLTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=wYfmOFp1; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="wYfmOFp1" Received: from umang.jain (unknown [103.251.226.70]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 931A5C8A; Wed, 6 Mar 2024 09:10:34 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1709712637; bh=wGmZeS95RXhE+ygELn87/BTnIoLY5pTdpYLkP/kMeYs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wYfmOFp1Te7eYw/yXN+YbtC+m6DiePD5Z+WToh80sM3ONsheBqopD0KeeeoUAQZKp WQdIAcx75dh6cVz/WaTRRsYyHLPD0SY0nK4HWkw9JpxJ0Ts7EYDdkTgZfaSlhz5gsZ hNnE43sYuyGqxzOD8u6gTOpHsyMk+Z337m8icfvs= From: Umang Jain To: linux-media@vger.kernel.org Cc: Alexander Shiyan , Kieran Bingham , Mauro Carvalho Chehab , Sakari Ailus , open list , Umang Jain Subject: [PATCH 1/5] media: imx335: Support 2 or 4 lane operation modes Date: Wed, 6 Mar 2024 13:40:34 +0530 Message-ID: <20240306081038.212412-2-umang.jain@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306081038.212412-1-umang.jain@ideasonboard.com> References: <20240306081038.212412-1-umang.jain@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Kieran Bingham The IMX335 can support both 2 and 4 lane configurations. Extend the driver to configure the lane mode accordingly. Update the pixel rate depending on the number of lanes in use. Signed-off-by: Kieran Bingham Signed-off-by: Umang Jain --- drivers/media/i2c/imx335.c | 46 +++++++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index dab6d080bc4c..a42f48823515 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -21,6 +21,11 @@ #define IMX335_MODE_STANDBY 0x01 #define IMX335_MODE_STREAMING 0x00 +/* Data Lanes */ +#define IMX335_LANEMODE 0x3a01 +#define IMX335_2LANE 1 +#define IMX335_4LANE 3 + /* Lines per frame */ #define IMX335_REG_LPFR 0x3030 @@ -67,8 +72,6 @@ #define IMX335_LINK_FREQ_594MHz 594000000LL #define IMX335_LINK_FREQ_445MHz 445500000LL -#define IMX335_NUM_DATA_LANES 4 - #define IMX335_REG_MIN 0x00 #define IMX335_REG_MAX 0xfffff @@ -115,7 +118,6 @@ static const char * const imx335_supply_name[] = { * @vblank: Vertical blanking in lines * @vblank_min: Minimum vertical blanking in lines * @vblank_max: Maximum vertical blanking in lines - * @pclk: Sensor pixel clock * @reg_list: Register list for sensor mode */ struct imx335_mode { @@ -126,7 +128,6 @@ struct imx335_mode { u32 vblank; u32 vblank_min; u32 vblank_max; - u64 pclk; struct imx335_reg_list reg_list; }; @@ -147,6 +148,7 @@ struct imx335_mode { * @exp_ctrl: Pointer to exposure control * @again_ctrl: Pointer to analog gain control * @vblank: Vertical blanking in lines + * @lane_mode Mode for number of connected data lanes * @cur_mode: Pointer to current selected sensor mode * @mutex: Mutex for serializing sensor controls * @link_freq_bitmap: Menu bitmap for link_freq_ctrl @@ -171,6 +173,7 @@ struct imx335 { struct v4l2_ctrl *again_ctrl; }; u32 vblank; + u32 lane_mode; const struct imx335_mode *cur_mode; struct mutex mutex; unsigned long link_freq_bitmap; @@ -377,7 +380,6 @@ static const struct imx335_mode supported_mode = { .vblank = 2560, .vblank_min = 2560, .vblank_max = 133060, - .pclk = 396000000, .reg_list = { .num_of_regs = ARRAY_SIZE(mode_2592x1940_regs), .regs = mode_2592x1940_regs, @@ -936,6 +938,11 @@ static int imx335_start_streaming(struct imx335 *imx335) return ret; } + /* Configure lanes */ + ret = imx335_write_reg(imx335, IMX335_LANEMODE, 1, imx335->lane_mode); + if (ret) + return ret; + /* Setup handler will write actual exposure and gain */ ret = __v4l2_ctrl_handler_setup(imx335->sd.ctrl_handler); if (ret) { @@ -1096,7 +1103,14 @@ static int imx335_parse_hw_config(struct imx335 *imx335) if (ret) return ret; - if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX335_NUM_DATA_LANES) { + switch (bus_cfg.bus.mipi_csi2.num_data_lanes) { + case 2: + imx335->lane_mode = IMX335_2LANE; + break; + case 4: + imx335->lane_mode = IMX335_4LANE; + break; + default: dev_err(imx335->dev, "number of CSI2 data lanes %d is not supported\n", bus_cfg.bus.mipi_csi2.num_data_lanes); @@ -1209,6 +1223,9 @@ static int imx335_init_controls(struct imx335 *imx335) struct v4l2_ctrl_handler *ctrl_hdlr = &imx335->ctrl_handler; const struct imx335_mode *mode = imx335->cur_mode; u32 lpfr; + u64 pclk; + s64 link_freq_in_use; + u8 bpp; int ret; ret = v4l2_ctrl_handler_init(ctrl_hdlr, 7); @@ -1252,11 +1269,24 @@ static int imx335_init_controls(struct imx335 *imx335) 0, 0, imx335_tpg_menu); /* Read only controls */ + + /* pixel rate = link frequency * lanes * 2 / bits_per_pixel */ + switch (imx335->cur_mbus_code) { + case MEDIA_BUS_FMT_SRGGB10_1X10: + bpp = 10; + break; + case MEDIA_BUS_FMT_SRGGB12_1X12: + bpp = 12; + break; + } + + link_freq_in_use = link_freq[__ffs(imx335->link_freq_bitmap)]; + pclk = link_freq_in_use * (imx335->lane_mode + 1) * 2 / bpp; imx335->pclk_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &imx335_ctrl_ops, V4L2_CID_PIXEL_RATE, - mode->pclk, mode->pclk, - 1, mode->pclk); + pclk, pclk, + 1, pclk); imx335->link_freq_ctrl = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx335_ctrl_ops, From patchwork Wed Mar 6 08:10:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umang Jain X-Patchwork-Id: 13583473 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 155565CDC9; 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arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="bU3xHkUh" Received: from umang.jain (unknown [103.251.226.70]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id CB89AFAD; Wed, 6 Mar 2024 09:10:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1709712642; bh=eGi/asiE2T7+c3wnXbY4y7w7m3h3dlY60L0/uI3eZV4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bU3xHkUh5Ce5AMZYe+761JpiwDI2oWM3wuA3h+SUzAImZLIiAqg6TWk1NSnhnggqb 8j6gk6SRI32cPcdXGuwHwotWmwmtPtQBr0RLSYMCHVabff8JBQwaFix+GOqZX02xTd ZMRNWxL1opE+bbaW9f7ExvL5aje86LTG5p117K8Q= From: Umang Jain To: linux-media@vger.kernel.org Cc: Alexander Shiyan , Kieran Bingham , Mauro Carvalho Chehab , Sakari Ailus , open list , Umang Jain Subject: [PATCH 2/5] media: imx335: Parse fwnode properties Date: Wed, 6 Mar 2024 13:40:35 +0530 Message-ID: <20240306081038.212412-3-umang.jain@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306081038.212412-1-umang.jain@ideasonboard.com> References: <20240306081038.212412-1-umang.jain@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Kieran Bingham Call the V4L2 fwnode device parser to handle controls that are standardised by the framework. Signed-off-by: Kieran Bingham Signed-off-by: Umang Jain --- drivers/media/i2c/imx335.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index a42f48823515..7f3f74240cd0 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -1222,13 +1222,15 @@ static int imx335_init_controls(struct imx335 *imx335) { struct v4l2_ctrl_handler *ctrl_hdlr = &imx335->ctrl_handler; const struct imx335_mode *mode = imx335->cur_mode; + struct v4l2_fwnode_device_properties props; u32 lpfr; u64 pclk; s64 link_freq_in_use; u8 bpp; int ret; - ret = v4l2_ctrl_handler_init(ctrl_hdlr, 7); + /* v4l2_fwnode_device_properties can add two more controls */ + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 9); if (ret) return ret; @@ -1313,6 +1315,15 @@ static int imx335_init_controls(struct imx335 *imx335) return ctrl_hdlr->error; } + ret = v4l2_fwnode_device_parse(imx335->dev, &props); + if (ret) + return ret; + + ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx335_ctrl_ops, + &props); + if (ret) + return ret; + imx335->sd.ctrl_handler = ctrl_hdlr; return 0; From patchwork Wed Mar 6 08:10:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umang Jain X-Patchwork-Id: 13583474 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF96E5DF06; Wed, 6 Mar 2024 08:11:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712668; cv=none; b=iO3Y7MRVjoIFcm/9BNuj8ACdb8vm0pZi5DiGoegqcUfa6z9v/oNzb1eCun6r8MZ/9NFfk1Co0wB0iOQB5lNBbjMyyYa/ADOMXmLwo8bHf+3hbxr2RbLtUUvK3n2sRwvUm1e3hQRGA6umIi7YBDBhgCA2WxlBXHI64Mo19bMwO9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712668; c=relaxed/simple; bh=pvJZWFFLzhOG0Hi/nMnuqBnApsdEn7iAE33m9J65yeE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DTxAQesvEcBeyaX+25L8kfNzF0WSAslARuaFh6WBRrroygeYxStwfbS6Mu49EfSEg6L4g4RV8GEQlll41CYlBjqkKmUjFUGvILk26uO0NQYyuA1uOoS+dXi3uGtua7L3vDV3yNbhlYvJN8gWNGpKi/Tmv2RxUe3F5kXytFVXIoo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=eYiktdRn; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="eYiktdRn" Received: from umang.jain (unknown [103.251.226.70]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 47CA8BD1; Wed, 6 Mar 2024 09:10:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1709712646; bh=pvJZWFFLzhOG0Hi/nMnuqBnApsdEn7iAE33m9J65yeE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eYiktdRnf1IZ6s0bnPQ23lbpFCPamP2/dIfmgGhD31qxJwf/VAhZagJu6RVlpwKk4 0GLa83mp6T17X8r3j02QHre8ynmAUgBvVcOUx3vdjxa8D+jgXy0yqMctFDC6aaRhb8 LWIiOx4kxVvr2McnHTitxY/0CCmNXZVe4WW3uASI= From: Umang Jain To: linux-media@vger.kernel.org Cc: Alexander Shiyan , Kieran Bingham , Mauro Carvalho Chehab , Sakari Ailus , open list , Umang Jain Subject: [PATCH 3/5] media: imx335: Use V4L2 CCI for accessing sensor registers Date: Wed, 6 Mar 2024 13:40:36 +0530 Message-ID: <20240306081038.212412-4-umang.jain@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306081038.212412-1-umang.jain@ideasonboard.com> References: <20240306081038.212412-1-umang.jain@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use the new comon CCI register access helpers to replace the private register access helpers in the imx335 driver. Select V4L2_CCI_I2C Kconfig option which the imx335 driver now depends on. Signed-off-by: Umang Jain --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/imx335.c | 521 ++++++++++++++++--------------------- 2 files changed, 225 insertions(+), 297 deletions(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 56f276b920ab..8d248b9c9562 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -195,6 +195,7 @@ config VIDEO_IMX334 config VIDEO_IMX335 tristate "Sony IMX335 sensor support" depends on OF_GPIO + select V4L2_CCI_I2C help This is a Video4Linux2 sensor driver for the Sony IMX335 camera. diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index 7f3f74240cd0..6ea09933e47b 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -11,47 +11,49 @@ #include #include #include +#include +#include #include #include #include /* Streaming Mode */ -#define IMX335_REG_MODE_SELECT 0x3000 +#define IMX335_REG_MODE_SELECT CCI_REG8(0x3000) #define IMX335_MODE_STANDBY 0x01 #define IMX335_MODE_STREAMING 0x00 /* Data Lanes */ -#define IMX335_LANEMODE 0x3a01 +#define IMX335_REG_LANEMODE CCI_REG8(0x3a01) #define IMX335_2LANE 1 #define IMX335_4LANE 3 /* Lines per frame */ -#define IMX335_REG_LPFR 0x3030 +#define IMX335_REG_VMAX CCI_REG24_LE(0x3030) /* Chip ID */ -#define IMX335_REG_ID 0x3912 +#define IMX335_REG_ID CCI_REG8(0x3912) #define IMX335_ID 0x00 /* Exposure control */ -#define IMX335_REG_SHUTTER 0x3058 +#define IMX335_REG_SHUTTER CCI_REG24_LE(0x3058) #define IMX335_EXPOSURE_MIN 1 #define IMX335_EXPOSURE_OFFSET 9 #define IMX335_EXPOSURE_STEP 1 #define IMX335_EXPOSURE_DEFAULT 0x0648 /* Analog gain control */ -#define IMX335_REG_AGAIN 0x30e8 +#define IMX335_REG_AGAIN CCI_REG8(0x30e8) #define IMX335_AGAIN_MIN 0 #define IMX335_AGAIN_MAX 240 #define IMX335_AGAIN_STEP 1 #define IMX335_AGAIN_DEFAULT 0 /* Group hold register */ -#define IMX335_REG_HOLD 0x3001 +#define IMX335_REG_HOLD CCI_REG8(0x3001) /* Test pattern generator */ -#define IMX335_REG_TPG 0x329e +#define IMX335_REG_TPG CCI_REG8(0x329e) #define IMX335_TPG_ALL_000 0 #define IMX335_TPG_ALL_FFF 1 #define IMX335_TPG_ALL_555 2 @@ -65,6 +67,46 @@ #define IMX335_TPG_H_COLOR_BARS 10 #define IMX335_TPG_V_COLOR_BARS 11 +#define IMX335_REG_MASTER_MODE CCI_REG8(0x3002) +#define IMX335_REG_WINMODE CCI_REG8(0x3018) +#define IMX335_REG_HTRIMMING_START CCI_REG16_LE(0x302c) +#define IMX335_REG_HNUM CCI_REG8(0x302e) +#define IMX335_REG_XVS_XHS_DRV CCI_REG8(0x31a1) +#define IMX335_REG_Y_OUT_SIZE CCI_REG16_LE(0x3056) +#define IMX335_REG_VCROP_POS CCI_REG16_LE(0x3074) +#define IMX335_REG_VCROP_SIZE CCI_REG16_LE(0x3076) +#define IMX335_REG_OPB_SIZE_V CCI_REG8(0x304c) + +#define IMX335_REG_ADBIT CCI_REG8(0x3050) +#define IMX335_REG_MDBIT CCI_REG8(0x319d) +#define IMX335_REG_ADBIT1 CCI_REG16_LE(0x341c) + +#define IMX335_REG_BCWAIT_TIME CCI_REG8(0x300c) +#define IMX335_REG_CPWAIT_TIME CCI_REG8(0x300d) +#define IMX335_REG_INCLKSEL1 CCI_REG16_LE(0x314c) +#define IMX335_REG_INCLKSEL2 CCI_REG8(0x315a) +#define IMX335_REG_INCLKSEL3 CCI_REG8(0x3168) +#define IMX335_REG_INCLKSEL4 CCI_REG8(0x316a) +#define IMX335_REG_SYSMODE CCI_REG8(0x319e) + +#define IMX335_REG_TCLKPOST CCI_REG16_LE(0x3a18) +#define IMX335_REG_TCLKPREPARE CCI_REG16_LE(0x3a1a) +#define IMX335_REG_TCLK_TRAIL CCI_REG16_LE(0x3a1c) +#define IMX335_REG_TCLK_ZERO CCI_REG16_LE(0x3a1e) +#define IMX335_REG_THS_PREPARE CCI_REG16_LE(0x3a20) +#define IMX335_REG_THS_ZERO CCI_REG16_LE(0x3a22) +#define IMX335_REG_THS_TRAIL CCI_REG16_LE(0x3a24) +#define IMX335_REG_THS_EXIT CCI_REG16_LE(0x3a26) +#define IMX335_REG_TPLX CCI_REG16_LE(0x3a28) + + +#define IMX335_REG_TPG_TESTCLKEN CCI_REG8(0x3148) +#define IMX335_REG_TPG_DIG_CLP_MODE CCI_REG8(0x3280) +#define IMX335_REG_TPG_EN_DUOUT CCI_REG8(0x329c) +#define IMX335_REG_TPG_COLORWIDTH CCI_REG8(0x32a0) +#define IMX335_REG_TPG_BLKLEVEL CCI_REG16_LE(0x3302) +#define IMX335_REG_TPG_WRJ_OPEN CCI_REG8(0x336c) + /* Input clock rate */ #define IMX335_INCLK_RATE 24000000 @@ -83,16 +125,6 @@ #define IMX335_PIXEL_ARRAY_WIDTH 2592U #define IMX335_PIXEL_ARRAY_HEIGHT 1944U -/** - * struct imx335_reg - imx335 sensor register - * @address: Register address - * @val: Register value - */ -struct imx335_reg { - u16 address; - u8 val; -}; - /** * struct imx335_reg_list - imx335 sensor register list * @num_of_regs: Number of registers in the list @@ -100,7 +132,7 @@ struct imx335_reg { */ struct imx335_reg_list { u32 num_of_regs; - const struct imx335_reg *regs; + const struct cci_reg_sequence *regs; }; static const char * const imx335_supply_name[] = { @@ -161,6 +193,7 @@ struct imx335 { struct media_pad pad; struct gpio_desc *reset_gpio; struct regulator_bulk_data supplies[ARRAY_SIZE(imx335_supply_name)]; + struct regmap *cci; struct clk *inclk; struct v4l2_ctrl_handler ctrl_handler; @@ -213,140 +246,135 @@ static const int imx335_tpg_val[] = { }; /* Sensor mode registers */ -static const struct imx335_reg mode_2592x1940_regs[] = { - {0x3000, 0x01}, - {0x3002, 0x00}, - {0x3018, 0x04}, - {0x302c, 0x3c}, - {0x302e, 0x20}, - {0x3056, 0x94}, - {0x3074, 0xc8}, - {0x3076, 0x28}, - {0x304c, 0x00}, - {0x31a1, 0x00}, - {0x3288, 0x21}, - {0x328a, 0x02}, - {0x3414, 0x05}, - {0x3416, 0x18}, - {0x3648, 0x01}, - {0x364a, 0x04}, - {0x364c, 0x04}, - {0x3678, 0x01}, - {0x367c, 0x31}, - {0x367e, 0x31}, - {0x3706, 0x10}, - {0x3708, 0x03}, - {0x3714, 0x02}, - {0x3715, 0x02}, - {0x3716, 0x01}, - {0x3717, 0x03}, - {0x371c, 0x3d}, - {0x371d, 0x3f}, - {0x372c, 0x00}, - {0x372d, 0x00}, - {0x372e, 0x46}, - {0x372f, 0x00}, - {0x3730, 0x89}, - {0x3731, 0x00}, - {0x3732, 0x08}, - {0x3733, 0x01}, - {0x3734, 0xfe}, - {0x3735, 0x05}, - {0x3740, 0x02}, - {0x375d, 0x00}, - {0x375e, 0x00}, - {0x375f, 0x11}, - {0x3760, 0x01}, - {0x3768, 0x1b}, - {0x3769, 0x1b}, - {0x376a, 0x1b}, - {0x376b, 0x1b}, - {0x376c, 0x1a}, - {0x376d, 0x17}, - {0x376e, 0x0f}, - {0x3776, 0x00}, - {0x3777, 0x00}, - {0x3778, 0x46}, - {0x3779, 0x00}, - {0x377a, 0x89}, - {0x377b, 0x00}, - {0x377c, 0x08}, - {0x377d, 0x01}, - {0x377e, 0x23}, - {0x377f, 0x02}, - {0x3780, 0xd9}, - {0x3781, 0x03}, - {0x3782, 0xf5}, - {0x3783, 0x06}, - {0x3784, 0xa5}, - {0x3788, 0x0f}, - {0x378a, 0xd9}, - {0x378b, 0x03}, - {0x378c, 0xeb}, - {0x378d, 0x05}, - {0x378e, 0x87}, - {0x378f, 0x06}, - {0x3790, 0xf5}, - {0x3792, 0x43}, - {0x3794, 0x7a}, - {0x3796, 0xa1}, - {0x37b0, 0x36}, - {0x3a00, 0x00}, +static const struct cci_reg_sequence mode_2592x1940_regs[] = { + {IMX335_REG_MODE_SELECT, 0x01}, + {IMX335_REG_MASTER_MODE, 0x00}, + {IMX335_REG_WINMODE, 0x04}, + {IMX335_REG_HTRIMMING_START, 0x0180}, + {IMX335_REG_HNUM, 0x0a20}, + {IMX335_REG_Y_OUT_SIZE, 0x0794}, + {IMX335_REG_VCROP_POS, 0x00b0}, + {IMX335_REG_VCROP_SIZE, 0x0f58}, + {IMX335_REG_OPB_SIZE_V, 0x00}, + {IMX335_REG_XVS_XHS_DRV, 0x00}, + {CCI_REG8(0x3288), 0x21}, /* undocumented */ + {CCI_REG8(0x328a), 0x02}, /* undocumented */ + {CCI_REG8(0x3414), 0x05}, /* undocumented */ + {CCI_REG8(0x3416), 0x18}, /* undocumented */ + {CCI_REG8(0x3648), 0x01}, /* undocumented */ + {CCI_REG8(0x364a), 0x04}, /* undocumented */ + {CCI_REG8(0x364c), 0x04}, /* undocumented */ + {CCI_REG8(0x3678), 0x01}, /* undocumented */ + {CCI_REG8(0x367c), 0x31}, /* undocumented */ + {CCI_REG8(0x367e), 0x31}, /* undocumented */ + {CCI_REG8(0x3706), 0x10}, /* undocumented */ + {CCI_REG8(0x3708), 0x03}, /* undocumented */ + {CCI_REG8(0x3714), 0x02}, /* undocumented */ + {CCI_REG8(0x3715), 0x02}, /* undocumented */ + {CCI_REG8(0x3716), 0x01}, /* undocumented */ + {CCI_REG8(0x3717), 0x03}, /* undocumented */ + {CCI_REG8(0x371c), 0x3d}, /* undocumented */ + {CCI_REG8(0x371d), 0x3f}, /* undocumented */ + {CCI_REG8(0x372c), 0x00}, /* undocumented */ + {CCI_REG8(0x372d), 0x00}, /* undocumented */ + {CCI_REG8(0x372e), 0x46}, /* undocumented */ + {CCI_REG8(0x372f), 0x00}, /* undocumented */ + {CCI_REG8(0x3730), 0x89}, /* undocumented */ + {CCI_REG8(0x3731), 0x00}, /* undocumented */ + {CCI_REG8(0x3732), 0x08}, /* undocumented */ + {CCI_REG8(0x3733), 0x01}, /* undocumented */ + {CCI_REG8(0x3734), 0xfe}, /* undocumented */ + {CCI_REG8(0x3735), 0x05}, /* undocumented */ + {CCI_REG8(0x3740), 0x02}, /* undocumented */ + {CCI_REG8(0x375d), 0x00}, /* undocumented */ + {CCI_REG8(0x375e), 0x00}, /* undocumented */ + {CCI_REG8(0x375f), 0x11}, /* undocumented */ + {CCI_REG8(0x3760), 0x01}, /* undocumented */ + {CCI_REG8(0x3768), 0x1b}, /* undocumented */ + {CCI_REG8(0x3769), 0x1b}, /* undocumented */ + {CCI_REG8(0x376a), 0x1b}, /* undocumented */ + {CCI_REG8(0x376b), 0x1b}, /* undocumented */ + {CCI_REG8(0x376c), 0x1a}, /* undocumented */ + {CCI_REG8(0x376d), 0x17}, /* undocumented */ + {CCI_REG8(0x376e), 0x0f}, /* undocumented */ + {CCI_REG8(0x3776), 0x00}, /* undocumented */ + {CCI_REG8(0x3777), 0x00}, /* undocumented */ + {CCI_REG8(0x3778), 0x46}, /* undocumented */ + {CCI_REG8(0x3779), 0x00}, /* undocumented */ + {CCI_REG8(0x377a), 0x89}, /* undocumented */ + {CCI_REG8(0x377b), 0x00}, /* undocumented */ + {CCI_REG8(0x377c), 0x08}, /* undocumented */ + {CCI_REG8(0x377d), 0x01}, /* undocumented */ + {CCI_REG8(0x377e), 0x23}, /* undocumented */ + {CCI_REG8(0x377f), 0x02}, /* undocumented */ + {CCI_REG8(0x3780), 0xd9}, /* undocumented */ + {CCI_REG8(0x3781), 0x03}, /* undocumented */ + {CCI_REG8(0x3782), 0xf5}, /* undocumented */ + {CCI_REG8(0x3783), 0x06}, /* undocumented */ + {CCI_REG8(0x3784), 0xa5}, /* undocumented */ + {CCI_REG8(0x3788), 0x0f}, /* undocumented */ + {CCI_REG8(0x378a), 0xd9}, /* undocumented */ + {CCI_REG8(0x378b), 0x03}, /* undocumented */ + {CCI_REG8(0x378c), 0xeb}, /* undocumented */ + {CCI_REG8(0x378d), 0x05}, /* undocumented */ + {CCI_REG8(0x378e), 0x87}, /* undocumented */ + {CCI_REG8(0x378f), 0x06}, /* undocumented */ + {CCI_REG8(0x3790), 0xf5}, /* undocumented */ + {CCI_REG8(0x3792), 0x43}, /* undocumented */ + {CCI_REG8(0x3794), 0x7a}, /* undocumented */ + {CCI_REG8(0x3796), 0xa1}, /* undocumented */ + {CCI_REG8(0x37b0), 0x36}, /* undocumented */ + {CCI_REG8(0x3a00), 0x00}, /* undocumented */ }; -static const struct imx335_reg raw10_framefmt_regs[] = { - {0x3050, 0x00}, - {0x319d, 0x00}, - {0x341c, 0xff}, - {0x341d, 0x01}, +static const struct cci_reg_sequence raw10_framefmt_regs[] = { + {IMX335_REG_ADBIT, 0x00}, + {IMX335_REG_MDBIT, 0x00}, + {IMX335_REG_ADBIT1, 0x1ff}, }; -static const struct imx335_reg raw12_framefmt_regs[] = { - {0x3050, 0x01}, - {0x319d, 0x01}, - {0x341c, 0x47}, - {0x341d, 0x00}, +static const struct cci_reg_sequence raw12_framefmt_regs[] = { + {IMX335_REG_ADBIT, 0x01}, + {IMX335_REG_MDBIT, 0x01}, + {IMX335_REG_ADBIT1, 0x47}, }; -static const struct imx335_reg mipi_data_rate_1188Mbps[] = { - {0x300c, 0x3b}, - {0x300d, 0x2a}, - {0x314c, 0xc6}, - {0x314d, 0x00}, - {0x315a, 0x02}, - {0x3168, 0xa0}, - {0x316a, 0x7e}, - {0x319e, 0x01}, - {0x3a18, 0x8f}, - {0x3a1a, 0x4f}, - {0x3a1c, 0x47}, - {0x3a1e, 0x37}, - {0x3a1f, 0x01}, - {0x3a20, 0x4f}, - {0x3a22, 0x87}, - {0x3a24, 0x4f}, - {0x3a26, 0x7f}, - {0x3a28, 0x3f}, +static const struct cci_reg_sequence mipi_data_rate_1188Mbps[] = { + {IMX335_REG_BCWAIT_TIME, 0x3b}, + {IMX335_REG_CPWAIT_TIME, 0x2a}, + {IMX335_REG_INCLKSEL1, 0x00c6}, + {IMX335_REG_INCLKSEL2, 0x02}, + {IMX335_REG_INCLKSEL3, 0xa0}, + {IMX335_REG_INCLKSEL4, 0x7e}, + {IMX335_REG_SYSMODE, 0x01}, + {IMX335_REG_TCLKPOST, 0x8f}, + {IMX335_REG_TCLKPREPARE, 0x4f}, + {IMX335_REG_TCLK_TRAIL, 0x47}, + {IMX335_REG_TCLK_ZERO, 0x0137}, + {IMX335_REG_THS_PREPARE, 0x4f}, + {IMX335_REG_THS_ZERO, 0x87}, + {IMX335_REG_THS_TRAIL, 0x4f}, + {IMX335_REG_THS_EXIT, 0x7f}, + {IMX335_REG_TPLX, 0x3f}, }; -static const struct imx335_reg mipi_data_rate_891Mbps[] = { - {0x300c, 0x3b}, - {0x300d, 0x2a}, - {0x314c, 0x29}, - {0x314d, 0x01}, - {0x315a, 0x06}, - {0x3168, 0xa0}, - {0x316a, 0x7e}, - {0x319e, 0x02}, - {0x3a18, 0x7f}, - {0x3a1a, 0x37}, - {0x3a1c, 0x37}, - {0x3a1e, 0xf7}, - {0x3a20, 0x3f}, - {0x3a22, 0x6f}, - {0x3a24, 0x3f}, - {0x3a26, 0x5f}, - {0x3a28, 0x2f}, +static const struct cci_reg_sequence mipi_data_rate_891Mbps[] = { + {IMX335_REG_BCWAIT_TIME, 0x3b}, + {IMX335_REG_CPWAIT_TIME, 0x2a}, + {IMX335_REG_INCLKSEL1, 0x0129}, + {IMX335_REG_INCLKSEL2, 0x06}, + {IMX335_REG_INCLKSEL3, 0xa0}, + {IMX335_REG_INCLKSEL4, 0x7e}, + {IMX335_REG_SYSMODE, 0x02}, + {IMX335_REG_TCLKPOST, 0x7f}, + {IMX335_REG_TCLKPREPARE, 0x37}, + {IMX335_REG_TCLK_TRAIL, 0x37}, + {IMX335_REG_TCLK_ZERO, 0xf7}, + {IMX335_REG_THS_PREPARE, 0x3f}, + {IMX335_REG_THS_ZERO, 0x6f}, + {IMX335_REG_THS_TRAIL, 0x3f}, + {IMX335_REG_THS_EXIT, 0x5f}, + {IMX335_REG_TPLX, 0x2f}, }; static const s64 link_freq[] = { @@ -397,101 +425,6 @@ static inline struct imx335 *to_imx335(struct v4l2_subdev *subdev) return container_of(subdev, struct imx335, sd); } -/** - * imx335_read_reg() - Read registers. - * @imx335: pointer to imx335 device - * @reg: register address - * @len: length of bytes to read. Max supported bytes is 4 - * @val: pointer to register value to be filled. - * - * Big endian register addresses with little endian values. - * - * Return: 0 if successful, error code otherwise. - */ -static int imx335_read_reg(struct imx335 *imx335, u16 reg, u32 len, u32 *val) -{ - struct i2c_client *client = v4l2_get_subdevdata(&imx335->sd); - struct i2c_msg msgs[2] = {0}; - u8 addr_buf[2] = {0}; - u8 data_buf[4] = {0}; - int ret; - - if (WARN_ON(len > 4)) - return -EINVAL; - - put_unaligned_be16(reg, addr_buf); - - /* Write register address */ - msgs[0].addr = client->addr; - msgs[0].flags = 0; - msgs[0].len = ARRAY_SIZE(addr_buf); - msgs[0].buf = addr_buf; - - /* Read data from register */ - msgs[1].addr = client->addr; - msgs[1].flags = I2C_M_RD; - msgs[1].len = len; - msgs[1].buf = data_buf; - - ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); - if (ret != ARRAY_SIZE(msgs)) - return -EIO; - - *val = get_unaligned_le32(data_buf); - - return 0; -} - -/** - * imx335_write_reg() - Write register - * @imx335: pointer to imx335 device - * @reg: register address - * @len: length of bytes. Max supported bytes is 4 - * @val: register value - * - * Big endian register addresses with little endian values. - * - * Return: 0 if successful, error code otherwise. - */ -static int imx335_write_reg(struct imx335 *imx335, u16 reg, u32 len, u32 val) -{ - struct i2c_client *client = v4l2_get_subdevdata(&imx335->sd); - u8 buf[6] = {0}; - - if (WARN_ON(len > 4)) - return -EINVAL; - - put_unaligned_be16(reg, buf); - put_unaligned_le32(val, buf + 2); - if (i2c_master_send(client, buf, len + 2) != len + 2) - return -EIO; - - return 0; -} - -/** - * imx335_write_regs() - Write a list of registers - * @imx335: pointer to imx335 device - * @regs: list of registers to be written - * @len: length of registers array - * - * Return: 0 if successful. error code otherwise. - */ -static int imx335_write_regs(struct imx335 *imx335, - const struct imx335_reg *regs, u32 len) -{ - unsigned int i; - int ret; - - for (i = 0; i < len; i++) { - ret = imx335_write_reg(imx335, regs[i].address, 1, regs[i].val); - if (ret) - return ret; - } - - return 0; -} - /** * imx335_update_controls() - Update control ranges based on streaming mode * @imx335: pointer to imx335 device @@ -528,7 +461,7 @@ static int imx335_update_controls(struct imx335 *imx335, static int imx335_update_exp_gain(struct imx335 *imx335, u32 exposure, u32 gain) { u32 lpfr, shutter; - int ret; + int ret = 0; lpfr = imx335->vblank + imx335->cur_mode->height; shutter = lpfr - exposure; @@ -536,64 +469,49 @@ static int imx335_update_exp_gain(struct imx335 *imx335, u32 exposure, u32 gain) dev_dbg(imx335->dev, "Set exp %u, analog gain %u, shutter %u, lpfr %u\n", exposure, gain, shutter, lpfr); - ret = imx335_write_reg(imx335, IMX335_REG_HOLD, 1, 1); - if (ret) - return ret; - - ret = imx335_write_reg(imx335, IMX335_REG_LPFR, 3, lpfr); - if (ret) - goto error_release_group_hold; - - ret = imx335_write_reg(imx335, IMX335_REG_SHUTTER, 3, shutter); - if (ret) - goto error_release_group_hold; - - ret = imx335_write_reg(imx335, IMX335_REG_AGAIN, 2, gain); - -error_release_group_hold: - imx335_write_reg(imx335, IMX335_REG_HOLD, 1, 0); + cci_write(imx335->cci, IMX335_REG_HOLD, 1, &ret); + cci_write(imx335->cci, IMX335_REG_VMAX, lpfr, &ret); + cci_write(imx335->cci, IMX335_REG_SHUTTER, shutter, &ret); + cci_write(imx335->cci, IMX335_REG_AGAIN, gain, &ret); + cci_write(imx335->cci, IMX335_REG_HOLD, 0, &ret); return ret; } static int imx335_update_test_pattern(struct imx335 *imx335, u32 pattern_index) { - int ret; + int ret = 0; if (pattern_index >= ARRAY_SIZE(imx335_tpg_val)) return -EINVAL; if (pattern_index) { - const struct imx335_reg tpg_enable_regs[] = { - { 0x3148, 0x10 }, - { 0x3280, 0x00 }, - { 0x329c, 0x01 }, - { 0x32a0, 0x11 }, - { 0x3302, 0x00 }, - { 0x3303, 0x00 }, - { 0x336c, 0x00 }, + const struct cci_reg_sequence tpg_enable_regs[] = { + {IMX335_REG_TPG_TESTCLKEN, 0x10}, + {IMX335_REG_TPG_DIG_CLP_MODE, 0x00}, + {IMX335_REG_TPG_EN_DUOUT, 0x01}, + {IMX335_REG_TPG_COLORWIDTH, 0x11}, + {IMX335_REG_TPG_BLKLEVEL, 0x00}, + {IMX335_REG_TPG_WRJ_OPEN, 0x00}, }; - ret = imx335_write_reg(imx335, IMX335_REG_TPG, 1, - imx335_tpg_val[pattern_index]); - if (ret) - return ret; + cci_write(imx335->cci, IMX335_REG_TPG, + imx335_tpg_val[pattern_index], &ret); - ret = imx335_write_regs(imx335, tpg_enable_regs, - ARRAY_SIZE(tpg_enable_regs)); + cci_multi_reg_write(imx335->cci, tpg_enable_regs, + ARRAY_SIZE(tpg_enable_regs), &ret); } else { - const struct imx335_reg tpg_disable_regs[] = { - { 0x3148, 0x00 }, - { 0x3280, 0x01 }, - { 0x329c, 0x00 }, - { 0x32a0, 0x10 }, - { 0x3302, 0x32 }, - { 0x3303, 0x00 }, - { 0x336c, 0x01 }, + const struct cci_reg_sequence tpg_disable_regs[] = { + {IMX335_REG_TPG_TESTCLKEN, 0x00}, + {IMX335_REG_TPG_DIG_CLP_MODE, 0x01}, + {IMX335_REG_TPG_EN_DUOUT, 0x00}, + {IMX335_REG_TPG_COLORWIDTH, 0x10}, + {IMX335_REG_TPG_BLKLEVEL, 0x32}, + {IMX335_REG_TPG_WRJ_OPEN, 0x01}, }; - ret = imx335_write_regs(imx335, tpg_disable_regs, - ARRAY_SIZE(tpg_disable_regs)); + cci_multi_reg_write(imx335->cci, tpg_disable_regs, + ARRAY_SIZE(tpg_disable_regs), &ret); } return ret; @@ -892,12 +810,14 @@ static int imx335_set_framefmt(struct imx335 *imx335) { switch (imx335->cur_mbus_code) { case MEDIA_BUS_FMT_SRGGB10_1X10: - return imx335_write_regs(imx335, raw10_framefmt_regs, - ARRAY_SIZE(raw10_framefmt_regs)); + return cci_multi_reg_write(imx335->cci, raw10_framefmt_regs, + ARRAY_SIZE(raw10_framefmt_regs), + NULL); case MEDIA_BUS_FMT_SRGGB12_1X12: - return imx335_write_regs(imx335, raw12_framefmt_regs, - ARRAY_SIZE(raw12_framefmt_regs)); + return cci_multi_reg_write(imx335->cci, raw12_framefmt_regs, + ARRAY_SIZE(raw12_framefmt_regs), + NULL); } return -EINVAL; @@ -916,7 +836,8 @@ static int imx335_start_streaming(struct imx335 *imx335) /* Setup PLL */ reg_list = &link_freq_reglist[__ffs(imx335->link_freq_bitmap)]; - ret = imx335_write_regs(imx335, reg_list->regs, reg_list->num_of_regs); + ret = cci_multi_reg_write(imx335->cci, reg_list->regs, + reg_list->num_of_regs, NULL); if (ret) { dev_err(imx335->dev, "%s failed to set plls\n", __func__); return ret; @@ -924,8 +845,8 @@ static int imx335_start_streaming(struct imx335 *imx335) /* Write sensor mode registers */ reg_list = &imx335->cur_mode->reg_list; - ret = imx335_write_regs(imx335, reg_list->regs, - reg_list->num_of_regs); + ret = cci_multi_reg_write(imx335->cci, reg_list->regs, + reg_list->num_of_regs, NULL); if (ret) { dev_err(imx335->dev, "fail to write initial registers\n"); return ret; @@ -939,7 +860,8 @@ static int imx335_start_streaming(struct imx335 *imx335) } /* Configure lanes */ - ret = imx335_write_reg(imx335, IMX335_LANEMODE, 1, imx335->lane_mode); + ret = cci_write(imx335->cci, IMX335_REG_LANEMODE, + imx335->lane_mode, NULL); if (ret) return ret; @@ -951,8 +873,8 @@ static int imx335_start_streaming(struct imx335 *imx335) } /* Start streaming */ - ret = imx335_write_reg(imx335, IMX335_REG_MODE_SELECT, - 1, IMX335_MODE_STREAMING); + ret = cci_write(imx335->cci, IMX335_REG_MODE_SELECT, + IMX335_MODE_STREAMING, NULL); if (ret) { dev_err(imx335->dev, "fail to start streaming\n"); return ret; @@ -972,8 +894,8 @@ static int imx335_start_streaming(struct imx335 *imx335) */ static int imx335_stop_streaming(struct imx335 *imx335) { - return imx335_write_reg(imx335, IMX335_REG_MODE_SELECT, - 1, IMX335_MODE_STANDBY); + return cci_write(imx335->cci, IMX335_REG_MODE_SELECT, + IMX335_MODE_STANDBY, NULL); } /** @@ -1024,14 +946,14 @@ static int imx335_set_stream(struct v4l2_subdev *sd, int enable) static int imx335_detect(struct imx335 *imx335) { int ret; - u32 val; + u64 val; - ret = imx335_read_reg(imx335, IMX335_REG_ID, 2, &val); + ret = cci_read(imx335->cci, IMX335_REG_ID, &val, NULL); if (ret) return ret; if (val != IMX335_ID) { - dev_err(imx335->dev, "chip id mismatch: %x!=%x\n", + dev_err(imx335->dev, "chip id mismatch: %x!=%llx\n", IMX335_ID, val); return -ENXIO; } @@ -1345,6 +1267,11 @@ static int imx335_probe(struct i2c_client *client) return -ENOMEM; imx335->dev = &client->dev; + imx335->cci = devm_cci_regmap_init_i2c(client, 16); + if (IS_ERR(imx335->cci)) { + dev_err(imx335->dev, "Unable to initialize I2C\n"); + return -ENODEV; + } /* Initialize subdev */ v4l2_i2c_subdev_init(&imx335->sd, client, &imx335_subdev_ops); From patchwork Wed Mar 6 08:10:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umang Jain X-Patchwork-Id: 13583475 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 013C15CDFF; Wed, 6 Mar 2024 08:11:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712672; cv=none; b=MjtrLzUTcgrV5f2OvtoqRkr1QHquGpJ9AR0K4MgtDd8dkMvvCdKlY8lYu9Zzp1c1p/wZyGIl0yxm6lzcySqmmpNXbmqpDyr6JevommyO6s/0GBHI1T1SBrhMWmN3JUiAxw40n909YSvNORC1iHLL3ma5cjT++iO75GJOdCAoapw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 6 Mar 2024 09:10:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1709712651; bh=qhSfwgByJCp2UJ9Lmg9P2YciIUlKkzafGTiPwMse0eg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VGypEzCqD/L6eiGXH49W8rn9xZDVP0ph03UIdrwG76T1ktoj6b4RhWoka0LBw05dz 9OiqM9ZTn3JGvV7RmOwgaA2Nef1aiG0q2UtsJDzyOTsstERg5HDIL1UQC93NQZZoNJ an1XYhg5pjXM4oRUTUAFrTug1npWa+APJo7yAbz0= From: Umang Jain To: linux-media@vger.kernel.org Cc: Alexander Shiyan , Kieran Bingham , Mauro Carvalho Chehab , Sakari Ailus , open list , Umang Jain Subject: [PATCH 4/5] media: imx335: Fix active area height discrepency Date: Wed, 6 Mar 2024 13:40:37 +0530 Message-ID: <20240306081038.212412-5-umang.jain@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306081038.212412-1-umang.jain@ideasonboard.com> References: <20240306081038.212412-1-umang.jain@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The imx335 reports a recommended pixel area of - 2592x1944. The driver supported mode however limits it to height=1940. Fix the height discrepency by correctly the value of height (with updates to vblank and mode registers). Signed-off-by: Umang Jain --- drivers/media/i2c/imx335.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index 6ea09933e47b..c00e0c2be3f3 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -246,13 +246,13 @@ static const int imx335_tpg_val[] = { }; /* Sensor mode registers */ -static const struct cci_reg_sequence mode_2592x1940_regs[] = { +static const struct cci_reg_sequence mode_2592x1944_regs[] = { {IMX335_REG_MODE_SELECT, 0x01}, {IMX335_REG_MASTER_MODE, 0x00}, - {IMX335_REG_WINMODE, 0x04}, - {IMX335_REG_HTRIMMING_START, 0x0180}, + {IMX335_REG_WINMODE, 0x00}, + {IMX335_REG_HTRIMMING_START, 0x30}, {IMX335_REG_HNUM, 0x0a20}, - {IMX335_REG_Y_OUT_SIZE, 0x0794}, + {IMX335_REG_Y_OUT_SIZE, 0x0798}, {IMX335_REG_VCROP_POS, 0x00b0}, {IMX335_REG_VCROP_SIZE, 0x0f58}, {IMX335_REG_OPB_SIZE_V, 0x00}, @@ -403,14 +403,14 @@ static const u32 imx335_mbus_codes[] = { /* Supported sensor mode configurations */ static const struct imx335_mode supported_mode = { .width = 2592, - .height = 1940, + .height = 1944, .hblank = 342, - .vblank = 2560, - .vblank_min = 2560, + .vblank = 2556, + .vblank_min = 2556, .vblank_max = 133060, .reg_list = { - .num_of_regs = ARRAY_SIZE(mode_2592x1940_regs), - .regs = mode_2592x1940_regs, + .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs), + .regs = mode_2592x1944_regs, }, }; From patchwork Wed Mar 6 08:10:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Umang Jain X-Patchwork-Id: 13583476 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5973B5EE6A; Wed, 6 Mar 2024 08:11:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712675; cv=none; b=qB7eOxoNffofd4n5fkoj+ZQS7S1evE28qXgfVqj+UURMoTZbTj1KthbPZupKBFCZ2CsCiE/eW0l/gmk0HCB10mPpsRqzyiDa06UHhxDVlmDVpKRaD+Ed2LPMKYvjrCclI2HdRQ+qG7PJ2j1VzwaPSwhicy4c2vmqlX88B2YvC7k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709712675; c=relaxed/simple; bh=PDUP7rsaMivjiJCXl3vEQPR3PB4cpDd0COkDHIEJVcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jU9WVmnF1sV8VK9ReFdBlfnzgiGkKNyHUNAn2+x9DDwC0IIQ+JxzPiCrpv62Q35fnLUTO1pm7TDi3hSmq3MN5vECKoAYTfnKZ2zjRyoe2SnIb7dBTwJCfddebzB6A1FiDNYNUPoDMZr8QEFZFqSG0gsoxL0bbdxR/ob7jbGlK6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=q52+p6yx; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="q52+p6yx" Received: from umang.jain (unknown [103.251.226.70]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 343E5BD1; Wed, 6 Mar 2024 09:10:51 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1709712655; bh=PDUP7rsaMivjiJCXl3vEQPR3PB4cpDd0COkDHIEJVcA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=q52+p6yxBTWErRWqmI3++QU0P6LlDUQxPEtjakg4GopBE+zXifdMJR8hV5YBEtfAA QXnMWe11D5A6YUDk8Jk79jKTHvkLTijgSvX7mDKPPlfDkLzaS+i7A0RLhorgnHN2+i /sdoFeBQ4hjeQHfA5gQU04Bp6/Iq/w+6PaimnVR0= From: Umang Jain To: linux-media@vger.kernel.org Cc: Alexander Shiyan , Kieran Bingham , Mauro Carvalho Chehab , Sakari Ailus , open list , Umang Jain Subject: [PATCH 5/5] media: imx335: Limit analogue gain value Date: Wed, 6 Mar 2024 13:40:38 +0530 Message-ID: <20240306081038.212412-6-umang.jain@ideasonboard.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306081038.212412-1-umang.jain@ideasonboard.com> References: <20240306081038.212412-1-umang.jain@ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The sensor gain (both analog and digital) are controlled by a single gain value where: - 0dB to 30dB correspond to analog gain - 30.3dB to 72dB correspond to digital gain (with 0.3dB step) Hence, limit the analogue gain value to 100. For digital gain, support can be added later if needed. Signed-off-by: Umang Jain Reviewed-by: Kieran Bingham --- drivers/media/i2c/imx335.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/imx335.c b/drivers/media/i2c/imx335.c index c00e0c2be3f3..701bd5318b45 100644 --- a/drivers/media/i2c/imx335.c +++ b/drivers/media/i2c/imx335.c @@ -45,7 +45,7 @@ /* Analog gain control */ #define IMX335_REG_AGAIN CCI_REG8(0x30e8) #define IMX335_AGAIN_MIN 0 -#define IMX335_AGAIN_MAX 240 +#define IMX335_AGAIN_MAX 100 #define IMX335_AGAIN_STEP 1 #define IMX335_AGAIN_DEFAULT 0 @@ -1169,6 +1169,14 @@ static int imx335_init_controls(struct imx335 *imx335) IMX335_EXPOSURE_STEP, IMX335_EXPOSURE_DEFAULT); + /* + * The sensor has an analog gain and a digital gain, both controlled + * through a single gain value, expressed in 0.3dB increments. Values + * from 0.0dB (0) to 30.0dB (100) apply analog gain only, higher values + * up to 72.0dB (240) add further digital gain. Limit the range to + * analog gain only, support for digital gain can be added separately + * if needed. + */ imx335->again_ctrl = v4l2_ctrl_new_std(ctrl_hdlr, &imx335_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,