From patchwork Wed Mar 6 09:56:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13583725 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C21C5DF29; Wed, 6 Mar 2024 09:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; cv=none; b=XDiipXs9jZqA43ENuWW/pwR+Y1ukiVDtZvyjqgGZRscFB1TUUZo3a91cIymMoJtr1JnRT/TRAMGwb/9DTFahaAjJnYfVGzHo7kdN0u99I4stKcUxW78+07Sh42XA1hSxBwZUyelgnY+c1xuMaTz3EJDG/ujONLLNPzhOtXZx/do= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; c=relaxed/simple; bh=DQk9lCKuHSluKcrPQ1v0+lTVtvnpI7fwkC/si6tMhYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tKGD2u8gP3Gc3HNswEf1JmDJbJqJ1jFa56A1xWoLpIsJze3BBdSfykQeB2HFB39oIbZcyXbz6LnaPIwGXVvJy0VEd+g8Io2WIY+6q3cMqJCIASsluTNxVvXajE1cbnqOhMeBBzSymYcytumeLbwxtrqIrga80+Oo/SGSDmazUe8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=am7F77xP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="am7F77xP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8F96C43399; Wed, 6 Mar 2024 09:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709719189; bh=DQk9lCKuHSluKcrPQ1v0+lTVtvnpI7fwkC/si6tMhYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=am7F77xPfomHxwZCurqDdtuJ7q/YpklXZOPXXxNskzrquKhKKdhxyebSmfhXKwxly UR9p7nLIucCkLeQBpAI848TY4YoZp6oLniZ7P8LgOsiERpaV7j9zyjJWBnHAqY0lcO vXmbdE5zB5FbvYZMXvr6sw1bhyNzKHiy/N6Jg2XbgtkOWtbW1GWQ3p9IqSImAIFNVv Zc6ql6Du7lVvI7BzIPui7VW7dnDJ5vY3kewUljnyUpKEM+npRuj7+AC8WwHgsaiQC2 XOuiaB9j4BP8j/IUOiioRptLDfHLjrAGV7z5fMzoKKH/DpoxYLk/JuDTj4hpJCUMZ3 FHLbCDLnGChZw== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rho44-000000001az-2U32; Wed, 06 Mar 2024 10:59:56 +0100 From: Johan Hovold To: Bjorn Helgaas , Bjorn Andersson Cc: Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v4 1/5] dt-bindings: PCI: qcom: Allow 'required-opps' Date: Wed, 6 Mar 2024 10:56:47 +0100 Message-ID: <20240306095651.4551-2-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306095651.4551-1-johan+linaro@kernel.org> References: <20240306095651.4551-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some Qualcomm SoCs require a minimum performance level for the power domain so add 'required-opps' to the binding. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 3 +++ Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 125136176f93..8d570669650a 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -59,6 +59,9 @@ properties: power-domains: maxItems: 1 + required-opps: + maxItems: 1 + resets: minItems: 1 maxItems: 12 diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index c8f36978a94c..1d7a6a520fef 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -111,6 +111,9 @@ properties: description: GPIO controlled connection to PERST# signal maxItems: 1 + required-opps: + maxItems: 1 + wake-gpios: description: GPIO controlled connection to WAKE# signal maxItems: 1 From patchwork Wed Mar 6 09:56:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13583727 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50F295F481; Wed, 6 Mar 2024 09:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; cv=none; b=YRX0m1BzQZgBbr8hS+sJXSATHDcOKHhn5XqNxdvqNd4D54HVH5sw8yy4kcX6FOrcauF+r2RDG2lAhs5WyNhMTggHrlQ3WzixvLc0KY1HMewx6mPkz3N0/T1UoBxb9NBvaqU7gBx7DfgGP5F9rJnTwpGJmuei0ApkJorn4J2HHoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; c=relaxed/simple; bh=LG9qzAt51k9B0led/p2cn23iSKOm/jB6p41538MCRnk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bxPpOPYybgCGy4lz8I125deC8GCPPne+Bj4JQHInNRLqGRYWT18kP6EUGqFX9Z/pcMBTYvWxxeRmfuNyEZQ38xrQkk9LrjQerpRA5DGvwiZ8QKQObJR2lVCrO/XliCAB165+0hmDXH33Qh/mI/pV6puVFzHqpkwg1jMBwjH40G4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CSDDBmgg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CSDDBmgg" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5F24C43390; Wed, 6 Mar 2024 09:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709719189; bh=LG9qzAt51k9B0led/p2cn23iSKOm/jB6p41538MCRnk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CSDDBmggTyiVIlQmCe6H0SVuUIUkts6lV2ttygne7UjuVdaWOg9UfQ0c+9kPfCmvl BE4po2Ra9QTcBdMwqqYMDKUiSU4vkdXXbsnT8S1b9/zkOXK379rzslASZxMuvLnCNy 5gXC4zYKA7ZKRpFmryovhGOM2nz+gOibKkmL1otkVvnqWPSYdLtaWIrskwK42hx6EW OjZZSM7SmMG/syoIrkh7rl+R/D+bsfq9WdMI9v9MEkBtRowjATJr4tDl3NV3/KZ9iz ohvHfcR2nVswdN/LUnL0Y/Drgu0jZa2D0Lsnzeb5mVTR0S+sIkZ3TBqNOHCE/a++1S aPBmaStZzo0Tg== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rho44-000000001b1-2sbR; Wed, 06 Mar 2024 10:59:56 +0100 From: Johan Hovold To: Bjorn Helgaas , Bjorn Andersson Cc: Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , Krzysztof Kozlowski Subject: [PATCH v4 2/5] dt-bindings: PCI: qcom: Do not require 'msi-map-mask' Date: Wed, 6 Mar 2024 10:56:48 +0100 Message-ID: <20240306095651.4551-3-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306095651.4551-1-johan+linaro@kernel.org> References: <20240306095651.4551-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Whether the 'msi-map-mask' property is needed or not depends on how the MSI interrupts are mapped and it should therefore not be described as required. Note that the current schema fails to detect omissions of the mask property if the internal MSI controller properties are also present. Acked-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold --- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 1 - Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 1 - 2 files changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 8d570669650a..0d1b23523f62 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -93,7 +93,6 @@ anyOf: - "#interrupt-cells" - required: - msi-map - - msi-map-mask allOf: - $ref: /schemas/pci/pci-bus.yaml# diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 1d7a6a520fef..efaab5f82b47 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -134,7 +134,6 @@ anyOf: - "#interrupt-cells" - required: - msi-map - - msi-map-mask allOf: - $ref: /schemas/pci/pci-bus.yaml# From patchwork Wed Mar 6 09:56:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13583728 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5392C5F48E; Wed, 6 Mar 2024 09:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; cv=none; b=JqdcaGappzO1eW8bO20CZMhuGKPryxfwx0kecU0o2HT4+nF2dmvPXOnGx+tOj7cHWuAc132gxFiAJifAkdUCgnqihNCglXBvSgV6IZ/fDAx5XqqMsN7nXAmkbXvQs0YZGyna8xR+HePyLLuMpAN6YOrrk2L9xSZOr6PCAH8jR9w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; c=relaxed/simple; bh=t19IiT6RWlcBi2EkLmBwm6R0bOy4AN3yK/qdKvg3904=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qW24b2l+TiLKyJc1Q9miWs4d9P7ZXQIUmf9AqjAvPKYlFSDij271p6R7k0eQAwZo+T4FX3UZX3qDSJj1yckYUwfIgfqQpe6lcXwvGFEHZNpAzTGiWSAeJERlrYez+o/W5TEnIL63y4C7nE42gQ1frbQPD+LJxdN5/PtIsD10IPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=N2QhzLzv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="N2QhzLzv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E26B8C433C7; Wed, 6 Mar 2024 09:59:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709719189; bh=t19IiT6RWlcBi2EkLmBwm6R0bOy4AN3yK/qdKvg3904=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N2QhzLzv/eqvbYADTBQNp8scNPrLxqJc3iHNS48UYL02mXSsQWM7MSvJcGGHSmHzW eVVuIzp9luJPJ6b179mzWpLxNecALAkAb/0CziPjiznWozJxRiqijdPruzwJGk9qrj fXojX0xB+jz4yfmsRzHJy130nXQ6uxWzfYVho8+Km7DqVjyyzMaIlpxtOpQOypLIYO mRH274NRnh7YTcV+dRAZ1GOP3G9DfKC8tb84d+35UT12lhT0hh/ANNdDl+0XxdEikf PAhnMsTzFs1xL7j0a5JHIxLOIiS2LE1uixPgQSKQHsL9qvcqZtI7NEnJEZkF5zUJkT tSobSI79sbVIA== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rho44-000000001b3-3Ftm; Wed, 06 Mar 2024 10:59:56 +0100 From: Johan Hovold To: Bjorn Helgaas , Bjorn Andersson Cc: Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , stable@vger.kernel.org Subject: [PATCH v4 3/5] PCI: qcom: Disable ASPM L0s for sc8280xp, sa8540p and sa8295p Date: Wed, 6 Mar 2024 10:56:49 +0100 Message-ID: <20240306095651.4551-4-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306095651.4551-1-johan+linaro@kernel.org> References: <20240306095651.4551-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Commit 9f4f3dfad8cf ("PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops") started enabling ASPM unconditionally when the hardware claims to support it. This triggers Correctable Errors for some PCIe devices on machines like the Lenovo ThinkPad X13s when L0s is enabled, which could indicate an incomplete driver ASPM implementation or that the hardware does in fact not support L0s. This has now been confirmed by Qualcomm to be the case for sc8280xp and its derivate platforms (e.g. sa8540p and sa8295p). Specifically, the PHY configuration used on these platforms is not correctly tuned for L0s and there is currently no updated configuration available. Add a new flag to the driver configuration data and use it to disable ASPM L0s on sc8280xp, sa8540p and sa8295p for now. Note that only the 1.9.0 ops enable ASPM currently. Fixes: 9f4f3dfad8cf ("PCI: qcom: Enable ASPM for platforms supporting 1.9.0 ops") Cc: stable@vger.kernel.org # 6.7 Signed-off-by: Johan Hovold Reviewed-by: Manivannan Sadhasivam Reviewed-by: Bjorn Andersson --- drivers/pci/controller/dwc/pcie-qcom.c | 31 ++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ce2a3bd932b..9f83a1611a20 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -229,6 +229,7 @@ struct qcom_pcie_ops { struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; + bool no_l0s; }; struct qcom_pcie { @@ -272,6 +273,26 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) return 0; } +static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) +{ + struct qcom_pcie *pcie = to_qcom_pcie(pci); + u16 offset; + u32 val; + + if (!pcie->cfg->no_l0s) + return; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + dw_pcie_dbi_ro_wr_en(pci); + + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPM_L0S; + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static void qcom_pcie_clear_hpc(struct dw_pcie *pci) { u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); @@ -961,6 +982,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) { + qcom_pcie_clear_aspm_l0s(pcie->pci); qcom_pcie_clear_hpc(pcie->pci); return 0; @@ -1358,6 +1380,11 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { .ops = &ops_2_9_0, }; +static const struct qcom_pcie_cfg cfg_sc8280xp = { + .ops = &ops_1_9_0, + .no_l0s = true, +}; + static const struct dw_pcie_ops dw_pcie_ops = { .link_up = qcom_pcie_link_up, .start_link = qcom_pcie_start_link, @@ -1629,11 +1656,11 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, - { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0}, { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, - { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp }, { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, From patchwork Wed Mar 6 09:56:50 2024 Content-Type: text/plain; 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Wed, 06 Mar 2024 10:59:56 +0100 From: Johan Hovold To: Bjorn Helgaas , Bjorn Andersson Cc: Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , stable@vger.kernel.org Subject: [PATCH v4 4/5] arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP Date: Wed, 6 Mar 2024 10:56:50 +0100 Message-ID: <20240306095651.4551-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306095651.4551-1-johan+linaro@kernel.org> References: <20240306095651.4551-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the missing PCIe CX performance level votes to avoid relying on other drivers (e.g. USB or UFS) to maintain the nominal performance level required for Gen3 speeds. Fixes: 813e83157001 ("arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes") Cc: stable@vger.kernel.org # 6.2 Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 2fc8d3308844..a8279ba6a756 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1780,6 +1780,7 @@ pcie4: pcie@1c00000 { reset-names = "pci"; power-domains = <&gcc PCIE_4_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie4_phy>; phy-names = "pciephy"; @@ -1878,6 +1879,7 @@ pcie3b: pcie@1c08000 { reset-names = "pci"; power-domains = <&gcc PCIE_3B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3b_phy>; phy-names = "pciephy"; @@ -1976,6 +1978,7 @@ pcie3a: pcie@1c10000 { reset-names = "pci"; power-domains = <&gcc PCIE_3A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie3a_phy>; phy-names = "pciephy"; @@ -2077,6 +2080,7 @@ pcie2b: pcie@1c18000 { reset-names = "pci"; power-domains = <&gcc PCIE_2B_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2b_phy>; phy-names = "pciephy"; @@ -2175,6 +2179,7 @@ pcie2a: pcie@1c20000 { reset-names = "pci"; power-domains = <&gcc PCIE_2A_GDSC>; + required-opps = <&rpmhpd_opp_nom>; phys = <&pcie2a_phy>; phy-names = "pciephy"; From patchwork Wed Mar 6 09:56:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13583729 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72E995F576; Wed, 6 Mar 2024 09:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; cv=none; b=b4e6wY3xg3f+mLP271HdcKdp/OFzNoJG4DD5yLiizrLBnCth3be0w8M2ogJqFTIoackOjanZVuYzmxsEfW7XK2p/sw7FN1EG6sKgzcfP1Pu+VIs+E4BJgWaFkS6JGyvkshr+tQQzQFtozcr0rdx6DzUf1SgxLA0ZtOiFELUCUss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709719189; c=relaxed/simple; bh=ojYPW7jE2rJIAUqkKuKAwwVsYcr465YkRrcIVQM/NDI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lgtTEuHu7+PPV9jj4pXw5rvwG2i07WsvU1HsnKuAmZdp7jdVB0mpocbd6xntgkPDEZwlj+VcX6uKjpKZkOxmu0PAY563+SjSRRxuPQj3wyBGHVdFyKZmaf1VNhlIt9kooZ1csrFl8mN6ifpLdKqDlbgrOlfE5LEZ+kxdUpzpqLo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RhoIEeDR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RhoIEeDR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18B8CC4167E; Wed, 6 Mar 2024 09:59:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1709719189; bh=ojYPW7jE2rJIAUqkKuKAwwVsYcr465YkRrcIVQM/NDI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RhoIEeDROIaO8AA16Uum4Jfj6q12UBAvn3pYSlFTbJnaVJhwiVMNublQEuWDG3yZR JpM1gQgmw9RaHpxVTegRt7ahmT7BsXW+49mj97Dw0LgSSCRsNS1BY9uaFObTxVTOVt +0csGMJeKdOoWd6eZ+Lqs2Vdju2s2FLtTNQOv836oh0jKC50EUDU3p6Int4i+3hO6+ rXV7qgepKR5dxXHsI9Ngvg96O2kVxzxbnkmAXInMZe3TQpWlfFGTfuejH+fwSj87Dc hLLoCf3vyVJSatkk69eWSYf3sFG3r25tBo7DBlx8e9vjlD6HvCSr5jo9MU78Vk/mLZ 865AlormdHJUw== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1rho44-000000001b8-40Qa; Wed, 06 Mar 2024 10:59:56 +0100 From: Johan Hovold To: Bjorn Helgaas , Bjorn Andersson Cc: Konrad Dybcio , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold Subject: [PATCH v4 5/5] arm64: dts: qcom: sc8280xp: enable GICv3 ITS for PCIe Date: Wed, 6 Mar 2024 10:56:51 +0100 Message-ID: <20240306095651.4551-6-johan+linaro@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240306095651.4551-1-johan+linaro@kernel.org> References: <20240306095651.4551-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS). Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. Note that using the GIC ITS on SC8280XP will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. This will specifically lead to notifications about Correctable Errors being logged for the Wi-Fi controller on the Lenovo ThinkPad X13s when ASPM L0s is enabled. Suggested-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Johan Hovold --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a8279ba6a756..906dd4a656a2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1737,6 +1737,8 @@ pcie4: pcie@1c00000 { linux,pci-domain = <6>; num-lanes = <1>; + msi-map = <0x0 &its 0xe0000 0x10000>; + interrupts = , , , @@ -1838,6 +1840,8 @@ pcie3b: pcie@1c08000 { linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &its 0xd0000 0x10000>; + interrupts = , , , @@ -1937,6 +1941,8 @@ pcie3a: pcie@1c10000 { linux,pci-domain = <4>; num-lanes = <4>; + msi-map = <0x0 &its 0xc0000 0x10000>; + interrupts = , , , @@ -2039,6 +2045,8 @@ pcie2b: pcie@1c18000 { linux,pci-domain = <3>; num-lanes = <2>; + msi-map = <0x0 &its 0xb0000 0x10000>; + interrupts = , , , @@ -2138,6 +2146,8 @@ pcie2a: pcie@1c20000 { linux,pci-domain = <2>; num-lanes = <4>; + msi-map = <0x0 &its 0xa0000 0x10000>; + interrupts = , , , @@ -4424,7 +4434,7 @@ intc: interrupt-controller@17a00000 { #size-cells = <2>; ranges; - msi-controller@17a40000 { + its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller;