From patchwork Wed Mar 6 23:01:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13584712 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 064341C2A8 for ; Wed, 6 Mar 2024 23:01:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709766120; cv=none; b=J5Pztmo/4dGDJFGWECodAIzd3VwNKq/o3OZ2PqYRhPJ/2SD0dS3fWmNmXFZWkP2F5eVDiumeO59FMLUx4Tz08R7ayDxLDy7yGg4gY+F8S34Qmn04VYqTLgMtkecx7B/4axJJr1ol5e+7jLpnTXWm+7uGRaumy8VQD77V8D7QBy0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709766120; c=relaxed/simple; bh=F6tQGExbalAmMiQxJduK+2k4ekpLe9FlNQn92O+QbFs=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=oOopRJkjbzVmc3YY6uY4Zp/FRMwrlCRY5/SBUu2C8EIyYVlmGCxNdmu57YKLwT1FlFePwX4eavBzQIVBw29tF9jec+hM3PeaYO5/4FAF77VYJwRup3rSQr7fpA4mimWGFKuCucbfIS3VCDlwwWUU/Y9z8pjprpHz92oFx4jwheA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=rVav1R9m; arc=none smtp.client-ip=209.85.128.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="rVav1R9m" Received: by mail-yw1-f202.google.com with SMTP id 00721157ae682-60810219282so4474337b3.0 for ; Wed, 06 Mar 2024 15:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1709766118; x=1710370918; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=P0WeiDnazmfwO4kq9FVwAuu2D/m0SwnnqZMq8DjgSXQ=; b=rVav1R9mlKIvnveQREKRJWOdNQloPyYA6Vd7lWiqL539VTD7WQOUJ6EtXiY/tGloWl ax2UC5f0QHx+rWEtGk+DOn9F9QMWOr1HLRHlWGfMm8qeToABpNDMsdFK9h0RgpijH+pM RNUl4BwNodi5geNzbBj2qTozXz482V9jd5cKWkSd1NJgTatr991AF1c2OSf+IzS+VAx0 vkclwxZ6uo9iSPyEF9LONz5EPLjGnuLs8Xt2UhCuOTI2bHa8PkorIyQ6C16hHn8RymtG 41fVyWJMsYP95KCbcPMKkls/7pCkvZq0xJmzVopFKdSDBZ6ncSFsPF72AbDavC+ESw3U awKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709766118; x=1710370918; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=P0WeiDnazmfwO4kq9FVwAuu2D/m0SwnnqZMq8DjgSXQ=; b=L5ENTFKh1AuS3G/sgQhT1TFVvnkvGHB6HZmS8XTektzOiyYel8qfUvPWISgvF0gNZc JFkaS6nx7GxNRc5oeXCUEr43+8g9QKzjTY8PyR+v7hKTChJyH4i8ZER7wUwBs7a54kEK u7I5JpjrG08qeVdQcaLW8jDbfFDCHNNxBmXyXktUA0zQuUbb9wOEHBrmfbQoqEQOxVSD I4We+UG2KyZvISIGK6OLiWbdUZegdUoFypZnMymxAsimGgXFtQVeLIV1sdGwGvxTJJnQ RepsNzCUpT77e3ABPcI+lAhK4G9nlMMNrH+e57MmRpz9kFvAMw6l84N9DRmBxlprt1Li RlhQ== X-Gm-Message-State: AOJu0Yxif0Y2f08r9BIRaTEtThdWYLuGD3/pKsEITZ07NBYy9NUA2gwx QoSOP7bKXBLAIIP2KkjfxcdYVptijVpuDLZ1G1xOrKAlafsHaJDVPh5TY6g3gYX2RFd/nT1f0sO Y2Q== X-Google-Smtp-Source: AGHT+IF33AScMRehRjloo2/F9B8jM0Ow73insOMNBjyMbqyGTECJjxUq3/7aYDET+V5PXcDi0FEARvuTgRA= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a0d:df41:0:b0:609:ebe5:7d2a with SMTP id i62-20020a0ddf41000000b00609ebe57d2amr140395ywe.7.1709766117996; Wed, 06 Mar 2024 15:01:57 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 6 Mar 2024 15:01:50 -0800 In-Reply-To: <20240306230153.786365-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240306230153.786365-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240306230153.786365-2-seanjc@google.com> Subject: [kvm-unit-tests PATCH 1/4] x86/pmu: Enable PEBS on fixed counters iff baseline PEBS is support From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson , Like Xu , Mingwei Zhang , Zhenyu Wang , Zhang Xiong , Lv Zhiyuan , Dapeng Mi Enabling PEBS for fixed counters is only allowed if "Extended PEBS" is supported, and unfortunately "Extended PEBS" is bundled with a pile of other PEBS features under the "Baseline" umbrella. KVM emulates this correctly and disallows enabling PEBS on fixed counters if the vCPU doesn't have Baseline PEBS support. Signed-off-by: Sean Christopherson Reviewed-by: Dapeng Mi --- x86/pmu_pebs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index f7b52b90..050617cd 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -356,13 +356,13 @@ static void check_pebs_counters(u64 pebs_data_cfg) unsigned int idx; u64 bitmask = 0; - for (idx = 0; idx < pmu.nr_fixed_counters; idx++) + for (idx = 0; has_baseline && idx < pmu.nr_fixed_counters; idx++) check_one_counter(FIXED, idx, pebs_data_cfg); for (idx = 0; idx < max_nr_gp_events; idx++) check_one_counter(GP, idx, pebs_data_cfg); - for (idx = 0; idx < pmu.nr_fixed_counters; idx++) + for (idx = 0; has_baseline && idx < pmu.nr_fixed_counters; idx++) bitmask |= BIT_ULL(FIXED_CNT_INDEX + idx); for (idx = 0; idx < max_nr_gp_events; idx += 2) bitmask |= BIT_ULL(idx); From patchwork Wed Mar 6 23:01:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13584713 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A878E1C2A0 for ; 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Wed, 06 Mar 2024 15:01:59 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 6 Mar 2024 15:01:51 -0800 In-Reply-To: <20240306230153.786365-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240306230153.786365-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240306230153.786365-3-seanjc@google.com> Subject: [kvm-unit-tests PATCH 2/4] x86/pmu: Iterate over adaptive PEBS flag combinations From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson , Like Xu , Mingwei Zhang , Zhenyu Wang , Zhang Xiong , Lv Zhiyuan , Dapeng Mi Iterate over all possible combinations of adaptive PEBS flags, instead of simply testing each flag individually. There are currently only 16 possible combinations, i.e. there's no reason not to exhaustively test every one. Opportunistically rename PEBS_DATACFG_GP to PEBS_DATACFG_GPRS to differentiate it from general purposes *counters*, which KVM also tends to abbreviate as "GP". Signed-off-by: Sean Christopherson --- lib/x86/pmu.h | 6 +++++- x86/pmu_pebs.c | 20 +++++++++----------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/lib/x86/pmu.h b/lib/x86/pmu.h index 8465e3c9..f07fbd93 100644 --- a/lib/x86/pmu.h +++ b/lib/x86/pmu.h @@ -44,9 +44,13 @@ #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT) #define PEBS_DATACFG_MEMINFO BIT_ULL(0) -#define PEBS_DATACFG_GP BIT_ULL(1) +#define PEBS_DATACFG_GPRS BIT_ULL(1) #define PEBS_DATACFG_XMMS BIT_ULL(2) #define PEBS_DATACFG_LBRS BIT_ULL(3) +#define PEBS_DATACFG_MASK (PEBS_DATACFG_MEMINFO | \ + PEBS_DATACFG_GPRS | \ + PEBS_DATACFG_XMMS | \ + PEBS_DATACFG_LBRS) #define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) #define PEBS_DATACFG_LBR_SHIFT 24 diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 050617cd..dff1ed26 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -78,13 +78,6 @@ static uint32_t intel_arch_events[] = { 0x412e, /* PERF_COUNT_HW_CACHE_MISSES */ }; -static u64 pebs_data_cfgs[] = { - PEBS_DATACFG_MEMINFO, - PEBS_DATACFG_GP, - PEBS_DATACFG_XMMS, - PEBS_DATACFG_LBRS | ((MAX_NUM_LBR_ENTRY -1) << PEBS_DATACFG_LBR_SHIFT), -}; - /* Iterating each counter value is a waste of time, pick a few typical values. */ static u64 counter_start_values[] = { /* if PEBS counter doesn't overflow at all */ @@ -105,7 +98,7 @@ static unsigned int get_adaptive_pebs_record_size(u64 pebs_data_cfg) if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) sz += sizeof(struct pebs_meminfo); - if (pebs_data_cfg & PEBS_DATACFG_GP) + if (pebs_data_cfg & PEBS_DATACFG_GPRS) sz += sizeof(struct pebs_gprs); if (pebs_data_cfg & PEBS_DATACFG_XMMS) sz += sizeof(struct pebs_xmm); @@ -419,9 +412,14 @@ int main(int ac, char **av) if (!has_baseline) continue; - for (j = 0; j < ARRAY_SIZE(pebs_data_cfgs); j++) { - report_prefix_pushf("Adaptive (0x%lx)", pebs_data_cfgs[j]); - check_pebs_counters(pebs_data_cfgs[j]); + for (j = 0; j <= PEBS_DATACFG_MASK; j++) { + u64 pebs_data_cfg = j; + + if (pebs_data_cfg & PEBS_DATACFG_LBRS) + pebs_data_cfg |= ((MAX_NUM_LBR_ENTRY -1) << PEBS_DATACFG_LBR_SHIFT); + + report_prefix_pushf("Adaptive (0x%lx)", pebs_data_cfg); + check_pebs_counters(pebs_data_cfg); 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Wed, 06 Mar 2024 15:02:01 -0800 (PST) Reply-To: Sean Christopherson Date: Wed, 6 Mar 2024 15:01:52 -0800 In-Reply-To: <20240306230153.786365-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240306230153.786365-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240306230153.786365-4-seanjc@google.com> Subject: [kvm-unit-tests PATCH 3/4] x86/pmu: Test adaptive PEBS without any adaptive counters From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson , Like Xu , Mingwei Zhang , Zhenyu Wang , Zhang Xiong , Lv Zhiyuan , Dapeng Mi If adaptive PEBS is supported, verify that only basic PEBS records are generated for counters without their ADAPTIVE flag set. Per the SDM, adaptive records are generated if and only if both the per-counter flag *and* the global enable(s) in MSR_PEBS_DATA_CFG are set. IA32_PERFEVTSELx.Adaptive_Record[34]: If this bit is set and IA32_PEBS_ENABLE.PEBS_EN_PMCx is set for the corresponding GP counter, an overflow of PMCx results in generation of an adaptive PEBS record with state information based on the selections made in MSR_PEBS_DATA_CFG. If this bit is not set, a basic record is generated. and IA32_FIXED_CTR_CTRL.FCx_Adaptive_Record: If this bit is set and IA32_PEBS_ENABLE.PEBS_EN_FIXEDx is set for the corresponding Fixed counter, an overflow of FixedCtrx results in generation of an adaptive PEBS record with state information based on the selections made in MSR_PEBS_DATA_CFG. If this bit is not set, a basic record is generated. Signed-off-by: Sean Christopherson Reviewed-by: Like Xu Reviewed-by: Dapeng Mi --- x86/pmu_pebs.c | 74 ++++++++++++++++++++++++++------------------------ 1 file changed, 38 insertions(+), 36 deletions(-) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index dff1ed26..0e8d60c3 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -89,11 +89,11 @@ static u64 counter_start_values[] = { 0xffffffffffff, }; -static unsigned int get_adaptive_pebs_record_size(u64 pebs_data_cfg) +static unsigned int get_pebs_record_size(u64 pebs_data_cfg, bool use_adaptive) { unsigned int sz = sizeof(struct pebs_basic); - if (!has_baseline) + if (!use_adaptive) return sz; if (pebs_data_cfg & PEBS_DATACFG_MEMINFO) @@ -199,10 +199,10 @@ static void free_buffers(void) free_page(pebs_buffer); } -static void pebs_enable(u64 bitmask, u64 pebs_data_cfg) +static void pebs_enable(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive) { static struct debug_store *ds; - u64 baseline_extra_ctrl = 0, fixed_ctr_ctrl = 0; + u64 adaptive_ctrl = 0, fixed_ctr_ctrl = 0; unsigned int idx; if (has_baseline) @@ -212,15 +212,15 @@ static void pebs_enable(u64 bitmask, u64 pebs_data_cfg) ds->pebs_index = ds->pebs_buffer_base = (unsigned long)pebs_buffer; ds->pebs_absolute_maximum = (unsigned long)pebs_buffer + PAGE_SIZE; ds->pebs_interrupt_threshold = ds->pebs_buffer_base + - get_adaptive_pebs_record_size(pebs_data_cfg); + get_pebs_record_size(pebs_data_cfg, use_adaptive); for (idx = 0; idx < pmu.nr_fixed_counters; idx++) { if (!(BIT_ULL(FIXED_CNT_INDEX + idx) & bitmask)) continue; - if (has_baseline) - baseline_extra_ctrl = BIT(FIXED_CNT_INDEX + idx * 4); + if (use_adaptive) + adaptive_ctrl = BIT(FIXED_CNT_INDEX + idx * 4); wrmsr(MSR_PERF_FIXED_CTRx(idx), ctr_start_val); - fixed_ctr_ctrl |= (0xbULL << (idx * 4) | baseline_extra_ctrl); + fixed_ctr_ctrl |= (0xbULL << (idx * 4) | adaptive_ctrl); } if (fixed_ctr_ctrl) wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, fixed_ctr_ctrl); @@ -228,10 +228,10 @@ static void pebs_enable(u64 bitmask, u64 pebs_data_cfg) for (idx = 0; idx < max_nr_gp_events; idx++) { if (!(BIT_ULL(idx) & bitmask)) continue; - if (has_baseline) - baseline_extra_ctrl = ICL_EVENTSEL_ADAPTIVE; + if (use_adaptive) + adaptive_ctrl = ICL_EVENTSEL_ADAPTIVE; wrmsr(MSR_GP_EVENT_SELECTx(idx), EVNTSEL_EN | EVNTSEL_OS | EVNTSEL_USR | - intel_arch_events[idx] | baseline_extra_ctrl); + intel_arch_events[idx] | adaptive_ctrl); wrmsr(MSR_GP_COUNTERx(idx), ctr_start_val); } @@ -268,11 +268,11 @@ static void pebs_disable(unsigned int idx) wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); } -static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg) +static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive) { struct pebs_basic *pebs_rec = (struct pebs_basic *)pebs_buffer; struct debug_store *ds = (struct debug_store *)ds_bufer; - unsigned int pebs_record_size = get_adaptive_pebs_record_size(pebs_data_cfg); + unsigned int pebs_record_size; unsigned int count = 0; bool expected, pebs_idx_match, pebs_size_match, data_cfg_match; void *cur_record; @@ -293,12 +293,9 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg) do { pebs_rec = (struct pebs_basic *)cur_record; pebs_record_size = pebs_rec->format_size >> RECORD_SIZE_OFFSET; - pebs_idx_match = - pebs_rec->applicable_counters & bitmask; - pebs_size_match = - pebs_record_size == get_adaptive_pebs_record_size(pebs_data_cfg); - data_cfg_match = - (pebs_rec->format_size & GENMASK_ULL(47, 0)) == pebs_data_cfg; + pebs_idx_match = pebs_rec->applicable_counters & bitmask; + pebs_size_match = pebs_record_size == get_pebs_record_size(pebs_data_cfg, use_adaptive); + data_cfg_match = (pebs_rec->format_size & GENMASK_ULL(47, 0)) == pebs_data_cfg; expected = pebs_idx_match && pebs_size_match && data_cfg_match; report(expected, "PEBS record (written seq %d) is verified (including size, counters and cfg).", count); @@ -311,56 +308,57 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg) printf("FAIL: The applicable_counters (0x%lx) doesn't match with pmc_bitmask (0x%lx).\n", pebs_rec->applicable_counters, bitmask); if (!pebs_size_match) - printf("FAIL: The pebs_record_size (%d) doesn't match with MSR_PEBS_DATA_CFG (%d).\n", - pebs_record_size, get_adaptive_pebs_record_size(pebs_data_cfg)); + printf("FAIL: The pebs_record_size (%d) doesn't match with expected record size (%d).\n", + pebs_record_size, get_pebs_record_size(pebs_data_cfg, use_adaptive)); if (!data_cfg_match) - printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with MSR_PEBS_DATA_CFG (0x%lx).\n", - pebs_rec->format_size & 0xffffffffffff, pebs_data_cfg); + printf("FAIL: The pebs_data_cfg (0x%lx) doesn't match with the effective MSR_PEBS_DATA_CFG (0x%lx).\n", + pebs_rec->format_size & 0xffffffffffff, use_adaptive ? pebs_data_cfg : 0); } } -static void check_one_counter(enum pmc_type type, - unsigned int idx, u64 pebs_data_cfg) +static void check_one_counter(enum pmc_type type, unsigned int idx, + u64 pebs_data_cfg, bool use_adaptive) { int pebs_bit = BIT_ULL(type == FIXED ? FIXED_CNT_INDEX + idx : idx); report_prefix_pushf("%s counter %d (0x%lx)", type == FIXED ? "Extended Fixed" : "GP", idx, ctr_start_val); reset_pebs(); - pebs_enable(pebs_bit, pebs_data_cfg); + pebs_enable(pebs_bit, pebs_data_cfg, use_adaptive); workload(); pebs_disable(idx); - check_pebs_records(pebs_bit, pebs_data_cfg); + check_pebs_records(pebs_bit, pebs_data_cfg, use_adaptive); report_prefix_pop(); } /* more than one PEBS records will be generated. */ -static void check_multiple_counters(u64 bitmask, u64 pebs_data_cfg) +static void check_multiple_counters(u64 bitmask, u64 pebs_data_cfg, + bool use_adaptive) { reset_pebs(); - pebs_enable(bitmask, pebs_data_cfg); + pebs_enable(bitmask, pebs_data_cfg, use_adaptive); workload2(); pebs_disable(0); - check_pebs_records(bitmask, pebs_data_cfg); + check_pebs_records(bitmask, pebs_data_cfg, use_adaptive); } -static void check_pebs_counters(u64 pebs_data_cfg) +static void check_pebs_counters(u64 pebs_data_cfg, bool use_adaptive) { unsigned int idx; u64 bitmask = 0; for (idx = 0; has_baseline && idx < pmu.nr_fixed_counters; idx++) - check_one_counter(FIXED, idx, pebs_data_cfg); + check_one_counter(FIXED, idx, pebs_data_cfg, use_adaptive); for (idx = 0; idx < max_nr_gp_events; idx++) - check_one_counter(GP, idx, pebs_data_cfg); + check_one_counter(GP, idx, pebs_data_cfg, use_adaptive); for (idx = 0; has_baseline && idx < pmu.nr_fixed_counters; idx++) bitmask |= BIT_ULL(FIXED_CNT_INDEX + idx); for (idx = 0; idx < max_nr_gp_events; idx += 2) bitmask |= BIT_ULL(idx); report_prefix_pushf("Multiple (0x%lx)", bitmask); - check_multiple_counters(bitmask, pebs_data_cfg); + check_multiple_counters(bitmask, pebs_data_cfg, use_adaptive); report_prefix_pop(); } @@ -408,7 +406,7 @@ int main(int ac, char **av) for (i = 0; i < ARRAY_SIZE(counter_start_values); i++) { ctr_start_val = counter_start_values[i]; - check_pebs_counters(0); + check_pebs_counters(0, false); if (!has_baseline) continue; @@ -419,7 +417,11 @@ int main(int ac, char **av) pebs_data_cfg |= ((MAX_NUM_LBR_ENTRY -1) << PEBS_DATACFG_LBR_SHIFT); report_prefix_pushf("Adaptive (0x%lx)", pebs_data_cfg); - check_pebs_counters(pebs_data_cfg); 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If KVM fails to context switch LBRs, e.g. when the guest isn't using LBRs, as is the case in the pmu_pebs test, then adaptive PEBS can be used to read the *host* LBRs as the CPU doesn't enforce the VMX MSR bitmaps when generating PEBS records, i.e. ignores KVM's interception of reads to LBR MSRs. This testcase is best exercised by simultaneously utilizing LBRs in the host, e.g. by running "perf record -b -e instructions", so that there is non-zero data in the LBR MSRs. Cc: Like Xu Cc: Mingwei Zhang Cc: Zhenyu Wang Cc: Zhang Xiong Cc: Lv Zhiyuan Cc: Dapeng Mi Signed-off-by: Sean Christopherson Reviewed-by: Like Xu Reviewed-by: Dapeng Mi --- x86/pmu_pebs.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c index 0e8d60c3..df8e736f 100644 --- a/x86/pmu_pebs.c +++ b/x86/pmu_pebs.c @@ -299,6 +299,19 @@ static void check_pebs_records(u64 bitmask, u64 pebs_data_cfg, bool use_adaptive expected = pebs_idx_match && pebs_size_match && data_cfg_match; report(expected, "PEBS record (written seq %d) is verified (including size, counters and cfg).", count); + if (use_adaptive && (pebs_data_cfg & PEBS_DATACFG_LBRS)) { + unsigned int lbrs_offset = get_pebs_record_size(pebs_data_cfg & ~PEBS_DATACFG_LBRS, true); + struct lbr_entry *pebs_lbrs = cur_record + lbrs_offset; + int i; + + for (i = 0; i < MAX_NUM_LBR_ENTRY; i++) { + if (!pebs_lbrs[i].from && !pebs_lbrs[i].to) + continue; + + report_fail("PEBS LBR record %u isn't empty, got from = '%lx', to = '%lx', info = '%lx'", + i, pebs_lbrs[i].from, pebs_lbrs[i].to, pebs_lbrs[i].info); + } + } cur_record = cur_record + pebs_record_size; count++; } while (expected && (void *)cur_record < (void *)ds->pebs_index);