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b=skoWgE83iN3xC58PV/DR83mlH6LOWVsDaCpU843zMV6/gF3uRdUhlQwVog7T/YJTMbnxhD3/9Bb2qwxdzqcb/Z+XHsWfRRaa8/hHkVZkTic6R6EWFE2+q1r2bYZeFG54WiNnHkOeeQxZJ+778mISb7P1NP+BHaZUcyrfRTjk8KE= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS4PR04MB9338.eurprd04.prod.outlook.com (2603:10a6:20b:4e6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.32; Thu, 7 Mar 2024 02:47:58 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 02:47:58 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 1/7] dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible Date: Thu, 7 Mar 2024 10:47:48 +0800 Message-Id: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS4PR04MB9338:EE_ X-MS-Office365-Filtering-Correlation-Id: c437633c-c45c-4d50-1037-08dc3e50ff2a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This will add a compatible for it. Acked-by: Conor Dooley Signed-off-by: Xu Yang --- Changes in v2: - no changes Changes in v3: - let imx95 compatilbe with imx93 Changes in v4: - add Acked-by tag Changes in v5: - no changes --- Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 6c96a4204e5d..37e8b98f2cdc 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -30,6 +30,9 @@ properties: - items: - const: fsl,imx8dxl-ddr-pmu - const: fsl,imx8-ddr-pmu + - items: + - const: fsl,imx95-ddr-pmu + - const: fsl,imx93-ddr-pmu reg: maxItems: 1 From patchwork Thu Mar 7 02:47:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13584982 Received: from EUR02-AM0-obe.outbound.protection.outlook.com (mail-am0eur02on2089.outbound.protection.outlook.com [40.107.247.89]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BDA5EED7 for ; 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Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS4PR04MB9338.eurprd04.prod.outlook.com (2603:10a6:20b:4e6::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.32; Thu, 7 Mar 2024 02:48:05 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 02:48:05 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 2/7] perf: imx_perf: refactor driver for imx93 Date: Thu, 7 Mar 2024 10:47:49 +0800 Message-Id: <20240307024754.3469810-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS4PR04MB9338:EE_ X-MS-Office365-Filtering-Correlation-Id: a822dd32-e456-49f1-a4fb-08dc3e510390 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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However, some macro definitions and events are different on these two Socs. For preparing imx95 supports, this will refactor driver for imx93. Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - use is_visible to hide unwanted attributes as suggested by Will --- drivers/perf/fsl_imx9_ddr_perf.c | 66 +++++++++++++++++++++----------- 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 9685645bfe04..f4dca813b174 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -11,14 +11,14 @@ #include /* Performance monitor configuration */ -#define PMCFG1 0x00 -#define PMCFG1_RD_TRANS_FILT_EN BIT(31) -#define PMCFG1_WR_TRANS_FILT_EN BIT(30) -#define PMCFG1_RD_BT_FILT_EN BIT(29) -#define PMCFG1_ID_MASK GENMASK(17, 0) +#define PMCFG1 0x00 +#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) +#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) +#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) +#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) -#define PMCFG2 0x04 -#define PMCFG2_ID GENMASK(17, 0) +#define PMCFG2 0x04 +#define MX93_PMCFG2_ID GENMASK(17, 0) /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 @@ -71,6 +71,11 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static inline bool is_imx93(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx93_devtype_data; +} + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, { /* sentinel */ } @@ -178,7 +183,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), /* imx93 specific*/ /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), @@ -190,7 +195,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), /* imx93 specific*/ /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), @@ -202,7 +207,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), - IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), /* imx93 specific*/ /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), @@ -237,9 +242,26 @@ static struct attribute *ddr_perf_events_attrs[] = { NULL, }; +static umode_t +ddr_perf_events_attrs_is_visible(struct kobject *kobj, + struct attribute *attr, int unused) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); + + if ((!strcmp(attr->name, "eddrtq_pm_rd_trans_filt") || + !strcmp(attr->name, "eddrtq_pm_wr_trans_filt") || + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt")) && + !is_imx93(ddr_pmu)) + return 0; + + return attr->mode; +} + static const struct attribute_group ddr_perf_events_attr_group = { .name = "events", .attrs = ddr_perf_events_attrs, + .is_visible = ddr_perf_events_attrs_is_visible, }; PMU_FORMAT_ATTR(event, "config:0-7"); @@ -361,7 +383,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, } } -static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) { u32 pmcfg1, pmcfg2; int event, counter; @@ -372,27 +394,27 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int pmcfg1 = readl_relaxed(pmu->base + PMCFG1); if (counter == 2 && event == 73) - pmcfg1 |= PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_TRANS_FILT_EN; else if (counter == 2 && event != 73) - pmcfg1 &= ~PMCFG1_RD_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_TRANS_FILT_EN; if (counter == 3 && event == 73) - pmcfg1 |= PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 |= MX93_PMCFG1_WR_TRANS_FILT_EN; else if (counter == 3 && event != 73) - pmcfg1 &= ~PMCFG1_WR_TRANS_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_WR_TRANS_FILT_EN; if (counter == 4 && event == 73) - pmcfg1 |= PMCFG1_RD_BT_FILT_EN; + pmcfg1 |= MX93_PMCFG1_RD_BT_FILT_EN; else if (counter == 4 && event != 73) - pmcfg1 &= ~PMCFG1_RD_BT_FILT_EN; + pmcfg1 &= ~MX93_PMCFG1_RD_BT_FILT_EN; - pmcfg1 &= ~FIELD_PREP(PMCFG1_ID_MASK, 0x3FFFF); - pmcfg1 |= FIELD_PREP(PMCFG1_ID_MASK, cfg2); + pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); + pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, cfg2); writel(pmcfg1, pmu->base + PMCFG1); pmcfg2 = readl_relaxed(pmu->base + PMCFG2); - pmcfg2 &= ~FIELD_PREP(PMCFG2_ID, 0x3FFFF); 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Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS8PR04MB8022.eurprd04.prod.outlook.com (2603:10a6:20b:28a::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Thu, 7 Mar 2024 02:48:12 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 02:48:12 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 3/7] perf: imx_perf: fix counter start and config sequence Date: Thu, 7 Mar 2024 10:47:50 +0800 Message-Id: <20240307024754.3469810-3-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS8PR04MB8022:EE_ X-MS-Office365-Filtering-Correlation-Id: 86b8975d-2181-4048-bbff-08dc3e5107ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This sequence is not correct for AXI filter events since the correct AXI_MASK and AXI_ID are not set yet. Then the results may be inaccurate. Signed-off-by: Xu Yang --- Changes in v5: - new patch --- drivers/perf/fsl_imx9_ddr_perf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index f4dca813b174..2cd5bcf1d3d1 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -498,12 +498,12 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; - if (flags & PERF_EF_START) - ddr_perf_event_start(event, flags); - /* read trans, write trans, read beat */ imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + if (flags & PERF_EF_START) + ddr_perf_event_start(event, flags); + return 0; } From patchwork Thu Mar 7 02:47:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13584984 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2049.outbound.protection.outlook.com [40.107.7.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AF3B182BB for ; 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Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS8PR04MB8022.eurprd04.prod.outlook.com (2603:10a6:20b:28a::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Thu, 7 Mar 2024 02:48:21 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 02:48:21 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 4/7] perf: imx_perf: add macro definitions for parsing config attr Date: Thu, 7 Mar 2024 10:47:51 +0800 Message-Id: <20240307024754.3469810-4-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS8PR04MB8022:EE_ X-MS-Office365-Filtering-Correlation-Id: 91765e0e-5db4-41e6-6210-08dc3e510d4e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This will add macro definitions to avoid hard-code in driver. Signed-off-by: Xu Yang --- Changes in v4: - new patch Changes in v5: - move this patch earlier --- drivers/perf/fsl_imx9_ddr_perf.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 2cd5bcf1d3d1..35e422083948 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -42,6 +42,11 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CONFIG_EVENT_MASK 0x00FF +#define CONFIG_EVENT_OFFSET 0 +#define CONFIG_COUNTER_MASK 0xFF00 +#define CONFIG_COUNTER_OFFSET 8 + #define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) #define DDR_PERF_DEV_NAME "imx9_ddr" @@ -361,8 +366,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, int counter, bool enable) { u32 ctrl_a; + int event; ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); + event = (config & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; if (enable) { ctrl_a |= PMLCA_FC; @@ -374,7 +381,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, ctrl_a &= ~PMLCA_FC; ctrl_a |= PMLCA_CE; ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); - ctrl_a |= FIELD_PREP(PMLCA_EVENT, (config & 0x000000FF)); + ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); writel(ctrl_a, pmu->base + PMLCA(counter)); } else { /* Freeze counter. */ @@ -388,8 +395,8 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 u32 pmcfg1, pmcfg2; int event, counter; - event = cfg & 0x000000FF; - counter = (cfg & 0x0000FF00) >> 8; + event = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; pmcfg1 = readl_relaxed(pmu->base + PMCFG1); @@ -491,7 +498,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg2 = event->attr.config2; int counter; - counter = (cfg & 0x0000FF00) >> 8; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; pmu->events[counter] = event; pmu->active_events++; From patchwork Thu Mar 7 02:47:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13584985 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2071.outbound.protection.outlook.com [40.107.7.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AF931BC56 for ; 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Received: from DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) by AS8PR04MB8022.eurprd04.prod.outlook.com (2603:10a6:20b:28a::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39; Thu, 7 Mar 2024 02:48:28 +0000 Received: from DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0]) by DU2PR04MB8822.eurprd04.prod.outlook.com ([fe80::d45f:4483:c11:68b0%7]) with mapi id 15.20.7339.035; Thu, 7 Mar 2024 02:48:28 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 5/7] perf: imx_perf: add support for i.MX95 platform Date: Thu, 7 Mar 2024 10:47:52 +0800 Message-Id: <20240307024754.3469810-5-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS8PR04MB8022:EE_ X-MS-Office365-Filtering-Correlation-Id: efcfd9fe-882d-4e83-097b-08dc3e51116b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This will add support for i.MX95 and enhance the driver to support specific filter handling for it. Usage: For read beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt2,counter=3,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt1,counter=4,axi_mask=ID_MASK,axi_id=ID/ ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_rd_beat_filt0,counter=5,axi_mask=0x00f,axi_id=0x00c/ For write beat: ~# perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=ID_MASK,axi_id=ID/ eg: For edma2: perf stat -a -I 1000 -e imx9_ddr0/eddrtq_pm_wr_beat_filt,counter=2,axi_mask=0x00f,axi_id=0x00c/ Signed-off-by: Xu Yang --- Changes in v2: - put soc spefific axi filter events to drvdata according to franks suggestions. - adjust pmcfg axi_id and axi_mask config Changes in v3: - no changes Changes in v4: - only contain imx95 parts Changes in v5: - improve imx95_ddr_perf_monitor_config() - use write_relaxed to pair read_relaxed --- drivers/perf/fsl_imx9_ddr_perf.c | 96 +++++++++++++++++++++++++++++++- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index 35e422083948..f25f55126004 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -17,9 +17,19 @@ #define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) #define MX93_PMCFG1_ID_MASK GENMASK(17, 0) +#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) +#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) + #define PMCFG2 0x04 #define MX93_PMCFG2_ID GENMASK(17, 0) +#define PMCFG3 0x08 +#define PMCFG4 0x0C +#define PMCFG5 0x10 +#define PMCFG6 0x14 +#define MX95_PMCFG_ID_MASK GENMASK(9, 0) +#define MX95_PMCFG_ID GENMASK(25, 16) + /* Global control register affects all counters and takes priority over local control registers */ #define PMGC0 0x40 /* Global control register bits */ @@ -76,13 +86,23 @@ static const struct imx_ddr_devtype_data imx93_devtype_data = { .identifier = "imx93", }; +static const struct imx_ddr_devtype_data imx95_devtype_data = { + .identifier = "imx95", +}; + static inline bool is_imx93(struct ddr_pmu *pmu) { return pmu->devtype_data == &imx93_devtype_data; } +static inline bool is_imx95(struct ddr_pmu *pmu) +{ + return pmu->devtype_data == &imx95_devtype_data; +} + static const struct of_device_id imx_ddr_pmu_dt_ids[] = { - {.compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data}, + { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, + { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); @@ -189,6 +209,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73), /* imx93 specific*/ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, 73), /* imx95 specific*/ /* counter3 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64), @@ -201,6 +222,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73), /* imx93 specific*/ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, 73), /* imx95 specific*/ /* counter4 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64), @@ -213,6 +235,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73), /* imx93 specific*/ + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, 73), /* imx95 specific*/ /* counter5 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64), @@ -224,6 +247,7 @@ static struct attribute *ddr_perf_events_attrs[] = { IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70), IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71), IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72), + IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, 73), /* imx95 specific*/ /* counter6 specific events */ IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64), @@ -260,6 +284,13 @@ ddr_perf_events_attrs_is_visible(struct kobject *kobj, !is_imx93(ddr_pmu)) return 0; + if ((!strcmp(attr->name, "eddrtq_pm_wr_beat_filt") || + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt2") || + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt1") || + !strcmp(attr->name, "eddrtq_pm_rd_beat_filt0")) && + !is_imx95(ddr_pmu)) + return 0; + return attr->mode; } @@ -425,6 +456,60 @@ static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1 writel(pmcfg2, pmu->base + PMCFG2); } +static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int cfg2) +{ + u32 pmcfg1, pmcfg, offset = 0; + int event, counter; + + event = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; + counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; + + pmcfg1 = readl_relaxed(pmu->base + PMCFG1); + + if (event == 73) { + switch (counter) { + case 2: + pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; + offset = PMCFG3; + break; + case 3: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG4; + break; + case 4: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG5; + break; + case 5: + pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; + offset = PMCFG6; + break; + } + } else { + switch (counter) { + case 2: + pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; + break; + case 3: + case 4: + case 5: + pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; + break; + } + } + + writel_relaxed(pmcfg1, pmu->base + PMCFG1); + + if (offset) { + pmcfg = readl_relaxed(pmu->base + offset); + pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) | + FIELD_PREP(MX95_PMCFG_ID, 0x3FF)); + pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, cfg2) | + FIELD_PREP(MX95_PMCFG_ID, cfg1)); + writel_relaxed(pmcfg, pmu->base + offset); + } +} + static void ddr_perf_event_update(struct perf_event *event) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -505,8 +590,13 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) hwc->idx = counter; hwc->state |= PERF_HES_STOPPED; - /* read trans, write trans, read beat */ - imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); + if (is_imx93(pmu)) + /* read trans, write trans, read beat */ + imx93_ddr_perf_monitor_config(pmu, cfg, cfg1, cfg2); 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Thu, 7 Mar 2024 02:48:35 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 6/7] perf: imx_perf: limit counter ID from user space and optimize counter usage Date: Thu, 7 Mar 2024 10:47:53 +0800 Message-Id: <20240307024754.3469810-6-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS8PR04MB8022:EE_ X-MS-Office365-Filtering-Correlation-Id: 853ae16e-5bf8-405b-a1be-08dc3e511583 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This will add necessary check for counter ID from user space. Besides, this pmu has 10 counters except cycle counter which can be used to count reference events and counter specific evnets. This will also add supports to auto allocate counter if the user doesn't pass it the perf. Then, the usage of counter will be optimized. Signed-off-by: Xu Yang --- Changes in v2: - limit counter ID from user to 0-10 - combine dynamic and static allocation of counter Changes in v3: - no changes Changes in v4: - rename ddr_perf_is_specific_event() - use macro definitions to parse config attr Changes in v5: - improve ddr_perf_is_counter_specific_event() --- drivers/perf/fsl_imx9_ddr_perf.c | 69 +++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c index f25f55126004..0ac680ee2505 100644 --- a/drivers/perf/fsl_imx9_ddr_perf.c +++ b/drivers/perf/fsl_imx9_ddr_perf.c @@ -51,6 +51,7 @@ #define NUM_COUNTERS 11 #define CYCLES_COUNTER 0 +#define CYCLES_EVENT_ID 0 #define CONFIG_EVENT_MASK 0x00FF #define CONFIG_EVENT_OFFSET 0 @@ -271,6 +272,16 @@ static struct attribute *ddr_perf_events_attrs[] = { NULL, }; +/* + * An event is either reference evnet or counter specific event. + * For counter specific event, the event count will only be incremented + * on the corresponding counter. + */ +static bool ddr_perf_is_counter_specific_event(int event) +{ + return event >= 64 && event <= 73; +} + static umode_t ddr_perf_events_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int unused) @@ -529,6 +540,7 @@ static int ddr_perf_event_init(struct perf_event *event) struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; struct perf_event *sibling; + int event_id, counter; if (event->attr.type != event->pmu->type) return -ENOENT; @@ -541,6 +553,18 @@ static int ddr_perf_event_init(struct perf_event *event) return -EOPNOTSUPP; } + counter = (event->attr.config & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; + if (counter > NUM_COUNTERS) { + dev_warn(pmu->dev, "Only counter 0-10 is supported!\n"); + return -EINVAL; + } + + event_id = (event->attr.config & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; + if (ddr_perf_is_counter_specific_event(event_id) && counter == 0) { + dev_err(pmu->dev, "Need specify counter for counter specific events!\n"); + return -EINVAL; + } + /* * We must NOT create groups containing mixed PMUs, although software * events are acceptable (for example to create a CCN group @@ -574,6 +598,39 @@ static void ddr_perf_event_start(struct perf_event *event, int flags) hwc->state = 0; } +static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter) +{ + int i; + + if (event == CYCLES_EVENT_ID) { + /* + * Always map cycle event to counter 0. + * Cycles counter is dedicated for cycle event + * can't used for the other counters. + */ + if (pmu->events[CYCLES_COUNTER] == NULL) + return CYCLES_COUNTER; + } else if (counter != 0) { + /* + * 1. ddr_perf_event_init() will make sure counter + * is not 0 for counter specific events. + * 2. Allow specify counter for referene event too. + */ + if (pmu->events[counter] == NULL) + return counter; + } else { + /* + * Counter may be 0 if user doesn't specify it. + * Auto allocate counter for referene event. + */ + for (i = 1; i < NUM_COUNTERS; i++) + if (pmu->events[i] == NULL) + return i; + } + + return -ENOENT; +} + static int ddr_perf_event_add(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); @@ -581,10 +638,18 @@ static int ddr_perf_event_add(struct perf_event *event, int flags) int cfg = event->attr.config; int cfg1 = event->attr.config1; int cfg2 = event->attr.config2; - int counter; + int event_id, counter; + event_id = (cfg & CONFIG_EVENT_MASK) >> CONFIG_EVENT_OFFSET; counter = (cfg & CONFIG_COUNTER_MASK) >> CONFIG_COUNTER_OFFSET; + /* check if counter is available or needs to allocate one */ + counter = ddr_perf_alloc_counter(pmu, event_id, counter); + if (counter < 0) { + dev_dbg(pmu->dev, "There are not enough counters\n"); + return -EOPNOTSUPP; + } + pmu->events[counter] = event; pmu->active_events++; hwc->idx = counter; @@ -620,9 +685,11 @@ static void ddr_perf_event_del(struct perf_event *event, int flags) { struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); struct hw_perf_event *hwc = &event->hw; + int counter = hwc->idx; ddr_perf_event_stop(event, PERF_EF_UPDATE); + pmu->events[counter] = NULL; pmu->active_events--; hwc->idx = -1; } From patchwork Thu Mar 7 02:47:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Yang X-Patchwork-Id: 13584987 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2078.outbound.protection.outlook.com [40.107.7.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3D9C1C6B4 for ; Thu, 7 Mar 2024 02:48:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.7.78 ARC-Seal: i=2; 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Thu, 7 Mar 2024 02:48:42 +0000 From: Xu Yang To: Frank.li@nxp.com, will@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, john.g.garry@oracle.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com Cc: mike.leach@linaro.org, peterz@infradead.org, mingo@redhat.com, acme@kernel.org, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, imx@lists.linux.dev Subject: [PATCH v5 7/7] perf vendor events arm64:: Add i.MX95 DDR Performance Monitor metrics Date: Thu, 7 Mar 2024 10:47:54 +0800 Message-Id: <20240307024754.3469810-7-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240307024754.3469810-1-xu.yang_2@nxp.com> References: <20240307024754.3469810-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI2PR02CA0037.apcprd02.prod.outlook.com (2603:1096:4:196::8) To DU2PR04MB8822.eurprd04.prod.outlook.com (2603:10a6:10:2e1::11) Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU2PR04MB8822:EE_|AS8PR04MB8022:EE_ X-MS-Office365-Filtering-Correlation-Id: b502acc2-22b1-4ca4-0247-08dc3e51199f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Ian Rogers Reviewed-by: Frank Li Signed-off-by: Xu Yang --- Changes in v2: - fix wrong AXI_MASK setting - remove unnecessary metrics - add bandwidth_usage, camera_all, disp_all metrics Changes in v3: - no changes Changes in v4: - add Reviewed-by tag Changes in v5: - fix typo --- .../arch/arm64/freescale/imx95/sys/ddrc.json | 9 + .../arm64/freescale/imx95/sys/metrics.json | 778 ++++++++++++++++++ tools/perf/pmu-events/jevents.py | 1 + 3 files changed, 788 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json create mode 100644 tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json new file mode 100644 index 000000000000..4dc9d2968bdc --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/ddrc.json @@ -0,0 +1,9 @@ +[ + { + "BriefDescription": "ddr cycles event", + "EventCode": "0x00", + "EventName": "imx95_ddr.cycles", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json new file mode 100644 index 000000000000..2bfcd4d574a8 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/freescale/imx95/sys/metrics.json @@ -0,0 +1,778 @@ +[ + { + "BriefDescription": "bandwidth usage for lpddr5 evk board", + "MetricName": "imx95_bandwidth_usage.lpddr5", + "MetricExpr": "(( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32 / duration_time) / (6400 * 1000000 * 4)", + "ScaleUnit": "1e2%", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters read from ddr", + "MetricName": "imx95_ddr_read.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all masters write to ddr", + "MetricName": "imx95_ddr_write.all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x000\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 read from ddr", + "MetricName": "imx95_ddr_read.a55_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part1)", + "MetricName": "imx95_ddr_write.a55_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fc\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all a55 write to ddr (part2)", + "MetricName": "imx95_ddr_write.a55_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3fe\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 read from ddr", + "MetricName": "imx95_ddr_read.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 0 write to ddr", + "MetricName": "imx95_ddr_write.a55_0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3ff\\,axi_id\\=0x000@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 read from ddr", + "MetricName": "imx95_ddr_read.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 1 write to ddr", + "MetricName": "imx95_ddr_write.a55_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x001@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 read from ddr", + "MetricName": "imx95_ddr_read.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 2 write to ddr", + "MetricName": "imx95_ddr_write.a55_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x002@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 read from ddr", + "MetricName": "imx95_ddr_read.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 3 write to ddr", + "MetricName": "imx95_ddr_write.a55_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x003@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 read from ddr", + "MetricName": "imx95_ddr_read.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 4 write to ddr", + "MetricName": "imx95_ddr_write.a55_4", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x004@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 read from ddr", + "MetricName": "imx95_ddr_read.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of a55 core 5 write to ddr", + "MetricName": "imx95_ddr_write.a55_5", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x005@ ) * 32", + "ScaleUnit": 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"Compat": "imx95" + }, + { + "BriefDescription": "bytes of m33 write to ddr", + "MetricName": "imx95_ddr_write.m33", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x008@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 read from ddr", + "MetricName": "imx95_ddr_read.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of m7 write to ddr", + "MetricName": "imx95_ddr_write.m7", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x009@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel read from ddr", + "MetricName": "imx95_ddr_read.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of sentinel write to ddr", + "MetricName": "imx95_ddr_write.sentinel", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00a@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 read from ddr", + "MetricName": "imx95_ddr_read.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of edma1 write to ddr", + "MetricName": "imx95_ddr_write.edma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x00f\\,axi_id\\=0x00b@ ) * 32", + "ScaleUnit": "9.765625e-4KB", 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"ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of gpu write to ddr", + "MetricName": "imx95_ddr_write.gpu", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x020@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 read from ddr", + "MetricName": "imx95_ddr_read.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc1 write to ddr", + "MetricName": "imx95_ddr_write.usdhc1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of usdhc2 read from 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imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0d0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi read from ddr", + "MetricName": "imx95_ddr_read.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of xspi write to ddr", + "MetricName": "imx95_ddr_write.xspi", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x0f0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of pcie1 read from ddr", + "MetricName": "imx95_ddr_read.pcie1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x100@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": 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imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of vpu codec secondary bus write to ddr", + "MetricName": "imx95_ddr_write.vpu_secndy", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x190@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg decoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder read from ddr", + "MetricName": "imx95_ddr_read.jpeg_dec", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of jpeg encoder write to ddr", + "MetricName": "imx95_ddr_write.jpeg_enc", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x1b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all vpu submodules read from ddr", + "MetricName": "imx95_ddr_read.vpu_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all vpu submodules write to ddr", + "MetricName": "imx95_ddr_write.vpu_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380\\,axi_id\\=0x180@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ read from ddr", + "MetricName": "imx95_ddr_read.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of cortex m0+ write to ddr", + "MetricName": "imx95_ddr_write.m0", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma read from ddr", + "MetricName": "imx95_ddr_read.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of camera edma write to ddr", + "MetricName": "imx95_ddr_write.camera_edma", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x210@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd read from ddr", + "MetricName": "imx95_ddr_read.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi rd write to ddr", + "MetricName": "imx95_ddr_write.isi_rd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x220@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr y write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_y", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x230@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr u write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_u", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x240@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v read from ddr", + "MetricName": "imx95_ddr_read.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isi wr v write to ddr", + "MetricName": "imx95_ddr_write.isi_wr_v", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x250@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x260@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp input dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_in_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x270@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma1 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 read from ddr", + "MetricName": "imx95_ddr_read.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of isp output dma2 write to ddr", + "MetricName": "imx95_ddr_write.isp_out_dma2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules read from ddr", + "MetricName": "imx95_ddr_read.camera_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x380\\,axi_id\\=0x200@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ + imx9_ddr0@eddrtq_pm_rd_beat_filt2\\,counter\\=3\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.camera_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x380\\,axi_id\\=0x200@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.camera_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x280@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all camera submodules write to ddr (part3)", + "MetricName": "imx95_ddr_write.camera_all_3", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x290@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter store read from ddr", + "MetricName": "imx95_ddr_read.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display blitter write to ddr", + "MetricName": "imx95_ddr_write.disp_blit", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer read from ddr", + "MetricName": "imx95_ddr_read.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of display command sequencer write to ddr", + "MetricName": "imx95_ddr_write.disp_cmd", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3f0\\,axi_id\\=0x2b0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules read from ddr", + "MetricName": "imx95_ddr_read.disp_all", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_rd_beat_filt0\\,counter\\=5\\,axi_mask\\=0x300\\,axi_id\\=0x300@ + imx9_ddr0@eddrtq_pm_rd_beat_filt1\\,counter\\=4\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part1)", + "MetricName": "imx95_ddr_write.disp_all_1", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x300\\,axi_id\\=0x300@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + }, + { + "BriefDescription": "bytes of all display submodules write to ddr (part2)", + "MetricName": "imx95_ddr_write.disp_all_2", + "MetricExpr": "( imx9_ddr0@eddrtq_pm_wr_beat_filt\\,counter\\=2\\,axi_mask\\=0x3a0\\,axi_id\\=0x2a0@ ) * 32", + "ScaleUnit": "9.765625e-4KB", + "Unit": "imx9_ddr", + "Compat": "imx95" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py index 53ab050c8fa4..be4b541a0820 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -284,6 +284,7 @@ class JsonEvent: 'hisi_sccl,hha': 'hisi_sccl,hha', 'hisi_sccl,l3c': 'hisi_sccl,l3c', 'imx8_ddr': 'imx8_ddr', + 'imx9_ddr': 'imx9_ddr', 'L3PMC': 'amd_l3', 'DFPMC': 'amd_df', 'UMCPMC': 'amd_umc',