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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 1/2] dt-bindings: net: add phy-supply property for stm32 Date: Thu, 7 Mar 2024 14:59:56 +0100 Message-ID: <20240307135957.303481-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307135957.303481-1-christophe.roullier@foss.st.com> References: <20240307135957.303481-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.128] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-07_08,2024-03-06_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240307_060257_523505_7236EA50 X-CRM114-Status: GOOD ( 11.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Phandle to a regulator that provides power to the PHY. This regulator will be managed during the PHY power on/off sequence. Acked-by: Krzysztof Kozlowski Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7dc..80937b28fa046 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -82,6 +82,9 @@ properties: Should be phandle/offset pair. The phandle to the syscon node which encompases the glue register, and the offset of the control register + phy-supply: + description: PHY regulator + st,eth-clk-sel: description: set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. From patchwork Thu Mar 7 13:59:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13585717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 577A4C48BF6 for ; Thu, 7 Mar 2024 14:03:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3HTAyxWqFYMsdF6EbEHoMSPIDAaTp97uHpPZ3U6M2X8=; b=NJZA0zVeG6p8cD 6gTIplJ1EgmNqkLUN4o1YxMoNCRmf+iBE5Z5eeQkB6X4dpaBfvzkPkEFfdEFOXeIzpDAxag4CYB+1 d8BfPwn+/pkANL0ZEOxv8lDN/H5O0zUexb3acaCurFutm77Tk7TRksPmG3orsh/F5/6JPbaI5o5+y qbf6NOu41zIEd320Rjsypn3+LaHmXLS+/ZFslfc60tTi6efDiN1JbV942BHOXFB6ZfAG2ywdCPH88 SlJYKNJHmw9qn8XXUfDlr1AtiMO1I9HSp+n9+KsTUM1g97MmCFrH2Jf2lsnMfURqXLwu4EMj8suQD o7ehNv8pzFzzjxfPz2Gg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1riEKd-00000004uzA-0wgV; Thu, 07 Mar 2024 14:02:47 +0000 Received: from mx07-00178001.pphosted.com ([185.132.182.106]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1riEKU-00000004uqF-3PCV for linux-arm-kernel@lists.infradead.org; Thu, 07 Mar 2024 14:02:41 +0000 Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 427A9dg7015304; Thu, 7 Mar 2024 15:02:24 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=sMzsSSzo2PkJfpYCCdg9znEVD7Q6RBjU2TnjYoyuVdM=; b=AH rVBjk8rM7YTS+jgI8EJcNLY95q+DL53Va4M/AfVEGPrcZgliQNbbgZeEiPfJOXnx QFbqvJTlwvX93fGOqh+ewdbpxFcM2ZBujetMGbMu+sL+2QIBzZIwBGmlvj9LzDmg yqulRMWT1xPJjfTuDk4BVlMesNMGjPS8s1NTDesf0CCTwI69/35F5tUwiJWhTeTK VBRRaqKHfSBfmXKphmk5oGRqeHAa3l9PfA4kyYiT5eS3i5dyLZZ4KqfXqTHFYQv/ zQmAofOSlyIcoRGfPu4i3pyblcs/7BnxnHxjbZaWX5pESoB32XU5tWhd2tYnISh+ vkkVI3mDGEHfmyMr8a7g== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3wmej5dxs5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 07 Mar 2024 15:02:24 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7CADC40046; Thu, 7 Mar 2024 15:02:21 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CBE4F27D0FF; Thu, 7 Mar 2024 15:01:11 +0100 (CET) Received: from localhost (10.201.21.128) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 7 Mar 2024 15:01:10 +0100 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 2/2] dt-bindings: net: add new property st,ext-phyclk in documentation for stm32 Date: Thu, 7 Mar 2024 14:59:57 +0100 Message-ID: <20240307135957.303481-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240307135957.303481-1-christophe.roullier@foss.st.com> References: <20240307135957.303481-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.128] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-07_08,2024-03-06_01,2023-05-22_02 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240307_060239_266316_F3CEC1A2 X-CRM114-Status: GOOD ( 11.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add property st,ext-phyclk to manage cases when PHY have no cristal/quartz This property can be used with RMII phy without cristal 50Mhz and when we want to select RCC clock instead of ETH_REF_CLK Can be used also with RGMII phy with no cristal and we select RCC clock instead of ETH_CLK125 Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 80937b28fa046..529665d4fc911 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -85,6 +85,13 @@ properties: phy-supply: description: PHY regulator + st,ext-phyclk: + description: + set this property in RMII mode when you have PHY without crystal 50MHz and want to + select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when you want to select + RCC clock instead of ETH_CLK125. + type: boolean + st,eth-clk-sel: description: set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.