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[79.204.140.106]) by smtp.googlemail.com with ESMTPSA id zh16-20020a170906881000b00a44d01aff81sm345320ejb.97.2024.03.08.17.30.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Mar 2024 17:30:21 -0800 (PST) From: =?utf-8?q?Niklas_S=C3=B6derlund?= To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?q?Niklas_S=C3=B6derlund?= Subject: [PATCH] arm64: dts: renesas: white-hawk: ethernet: Describe adv1 and avb2 Date: Sat, 9 Mar 2024 02:30:06 +0100 Message-ID: <20240309013006.723934-1-niklas.soderlund+renesas@ragnatech.se> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Describe the two Marvel 88Q2110/QFN40 PHYs available on the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) sub-board. The two PHYs are wired up on the board by default, there is no need to move any resistors which are needed to access other PHYs available on this sub-board. Signed-off-by: Niklas Söderlund --- Hello Geert, This patch depends on the update to the bindings posted in [1] to not fail DT validation check's. However with this change I can bind to the two PHYs without having to touch ether the PHY or RAVB drivers, the MDIO core handle the reset of the MDIO bus. 1. [PACH] dt-bindings: net: renesas,etheravb: Add MDIO bus reset properties --- .../renesas/r8a779g0-white-hawk-ethernet.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi index 4f411f95c674..63e0fdae4ff6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi @@ -6,6 +6,38 @@ * Copyright (C) 2022 Glider bv */ +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + status = "okay"; + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupt-parent = <&gpio6>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&phy2>; + status = "okay"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + phy2: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + }; +}; + &i2c0 { eeprom@53 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -14,3 +46,45 @@ eeprom@53 { pagesize = <8>; }; }; + +&pfc { + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + pins_mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + pins_mii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + pins_mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + pins_mii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +};