From patchwork Sat Mar 9 01:36:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13587471 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9541D1BF3F for ; Sat, 9 Mar 2024 01:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709948208; cv=none; b=H1oi9hdd17f4HucTXgsMdEDZfPOREfLD0Fe5opUsTmAFuF0VBUjuEjvocpyclGveqEsMNn29nyvNZm+K6Bl1f+UvCPrAC6maYAToMdtp9oQOMrf6PCUI5iGtN3o/DUuUzqqsvAI9yXlz2cFJT29CPJWJ8TlO3umDzBw8Xfgq3Vg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709948208; c=relaxed/simple; bh=VJikoSrQo43avUuqAwx40juOg+W7uxK2JNJYf8WFBZc=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=OtoGlMAl7ME+QyHEuNGXX2C+gy/dC3bZVGPi+A2qzOMyWuKW+VGAX2qp78bhbVHfjeecLdJsBt7TG0FYt67I31N500lVkQURJL9ttUDUVlijWPl2ir36Hj6zfEvN2GoYEaEgQRIqpNoHWcJskZJEw8+3DPf+Wmu8bGNjMaz5AmA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=KSayU958; arc=none smtp.client-ip=209.85.219.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--seanjc.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="KSayU958" Received: by mail-yb1-f201.google.com with SMTP id 3f1490d57ef6-dc6b26845cdso4128072276.3 for ; Fri, 08 Mar 2024 17:36:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1709948205; x=1710553005; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=y0BhAxRzKsAvo5OwS6Sm/EpbJRorm6UaRPV9uoZ1QIo=; b=KSayU958IypRqhH6kxzGdePO9rJCxvJvHnnbJwOF3DXada6AHEmKUR7DUusDA9o+sM Vl/XG26p9FuhfOTRUu2lxWDdSBtxN9sknEqghv66KejDsDUO3gu2pTCJhTBz9+k7agZj T3RbtUq+GIFywlsOn2ttMMAx6GdNM/kBdtEwgDWLP2qM8/RPc5lVPm525aLSG9CRbPw+ 7iQoIOB9iykvSg+Wz5Ie7gomuvSB+SxSnZiDF7wKeLPoirEHhJ5MebajYYmqU48bezrO 3lWWi+wDK5bhJ9JOaDDZ2AN6FW2uYoI4ooY2qgxmTterp/w/RO/akHoJEGeJkvihd5Ex CKUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1709948205; x=1710553005; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=y0BhAxRzKsAvo5OwS6Sm/EpbJRorm6UaRPV9uoZ1QIo=; b=C2hrEEFoGqYiXvSFNw3d2BQksHVeS3+ToMtcYxmzTw6ZDRRnX8oISr5q/Hk/LVUrUj LVH4d5b9+HUl2bXnqxwVenZLzA5TxaD/EuD3XsE1+/k/++9vqsapS0PWqI30AIqUlDzo jpwjfxoqn8CNawmCAleZF7RMI6Qv7Gf83v5RRl5Ma7oRUhnIQWKdUREGzjm8q8aJRxBb j78Iv7f0kUu2LswSL1egSAaBQagBDF5CZJTnwaZSW4cZ9Atd8PnWqAYf7wE6hheSYmXF NtKsag1K7jtvfFWFSDXRys3rWIJHPyWX+vFSD5nTq2/8ekBzMG2zIVBEUUj78FNsWl8A mZag== X-Gm-Message-State: AOJu0YxHSWNmj3hhtxpObqgtIOPTzGLVIbvnf+Lu9wTe3U2IaDWlNS3G 5aJf1PGfuklDNmEnYQ/OyyYoVgREOghag9aN/I9p0tgABsDWuq/A1W3OZsAQUeESPoTQ6pfm6uq vkA== X-Google-Smtp-Source: AGHT+IE7Q4/FbKsrxNDlfIOzAZB8pOyKI7MQmZxeak1X4epqT0OuTAuCFMQulvj7P9tT6+ZcW27G4fYd7Cs= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a25:aa83:0:b0:dc2:3441:897f with SMTP id t3-20020a25aa83000000b00dc23441897fmr188875ybi.6.1709948205744; Fri, 08 Mar 2024 17:36:45 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 8 Mar 2024 17:36:40 -0800 In-Reply-To: <20240309013641.1413400-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240309013641.1413400-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240309013641.1413400-2-seanjc@google.com> Subject: [PATCH 1/2] KVM: x86/pmu: Set enable bits for GP counters in PERF_GLOBAL_CTRL at "RESET" From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Babu Moger , Sandipan Das , Like Xu , Mingwei Zhang , Dapeng Mi Set the enable bits for general purpose counters in IA32_PERF_GLOBAL_CTRL when refreshing the PMU to emulate the MSR's architecturally defined post-RESET behavior. Per Intel's SDM: IA32_PERF_GLOBAL_CTRL: Sets bits n-1:0 and clears the upper bits. and Where "n" is the number of general-purpose counters available in the processor. AMD also documents this behavior for PerfMonV2 CPUs in one of AMD's many PPRs. Do not set any PERF_GLOBAL_CTRL bits if there are no general purpose counters, although a literal reading of the SDM would require the CPU to set either bits 63:0 or 31:0. The intent of the behavior is to globally enable all GP counters; honor the intent, if not the letter of the law. Leaving PERF_GLOBAL_CTRL '0' effectively breaks PMU usage in guests that haven't been updated to work with PMUs that support PERF_GLOBAL_CTRL. This bug was recently exposed when KVM added supported for AMD's PerfMonV2, i.e. when KVM started exposing a vPMU with PERF_GLOBAL_CTRL to guest software that only knew how to program v1 PMUs (that don't support PERF_GLOBAL_CTRL). Failure to emulate the post-RESET behavior results in such guests unknowingly leaving all general purpose counters globally disabled (the entire reason the post-RESET value sets the GP counter enable bits is to maintain backwards compatibility). The bug has likely gone unnoticed because PERF_GLOBAL_CTRL has been supported on Intel CPUs for as long as KVM has existed, i.e. hardly anyone is running guest software that isn't aware of PERF_GLOBAL_CTRL on Intel PMUs. And because up until v6.0, KVM _did_ emulate the behavior for Intel CPUs, although the old behavior was likely dumb luck. Because (a) that old code was also broken in its own way (the history of this code is a comedy of errors), and (b) PERF_GLOBAL_CTRL was documented as having a value of '0' post-RESET in all SDMs before March 2023. Initial vPMU support in commit f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests") *almost* got it right (again likely by dumb luck), but for some reason only set the bits if the guest PMU was advertised as v1: if (pmu->version == 1) { pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1; return; } Commit f19a0c2c2e6a ("KVM: PMU emulation: GLOBAL_CTRL MSR should be enabled on reset") then tried to remedy that goof, presumably because guest PMUs were leaving PERF_GLOBAL_CTRL '0', i.e. weren't enabling counters. pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED); pmu->global_ctrl_mask = ~pmu->global_ctrl; That was KVM's behavior up until commit c49467a45fe0 ("KVM: x86/pmu: Don't overwrite the pmu->global_ctrl when refreshing") removed *everything*. However, it did so based on the behavior defined by the SDM , which at the time stated that "Global Perf Counter Controls" is '0' at Power-Up and RESET. But then the March 2023 SDM (325462-079US), stealthily changed its "IA-32 and Intel 64 Processor States Following Power-up, Reset, or INIT" table to say: IA32_PERF_GLOBAL_CTRL: Sets bits n-1:0 and clears the upper bits. Note, kvm_pmu_refresh() can be invoked multiple times, i.e. it's not a "pure" RESET flow. But it can only be called prior to the first KVM_RUN, i.e. the guest will only ever observe the final value. Note #2, KVM has always cleared global_ctrl during refresh (see commit f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests")), i.e. there is no danger of breaking existing setups by clobbering a value set by userspace. Reported-by: Babu Moger Cc: Sandipan Das Cc: Like Xu Cc: Mingwei Zhang Cc: Dapeng Mi Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Tested-by: Babu Moger --- arch/x86/kvm/pmu.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index c397b28e3d1b..a593b03c9aed 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -775,8 +775,20 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) pmu->pebs_data_cfg_mask = ~0ull; bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX); - if (vcpu->kvm->arch.enable_pmu) - static_call(kvm_x86_pmu_refresh)(vcpu); + if (!vcpu->kvm->arch.enable_pmu) + return; + + static_call(kvm_x86_pmu_refresh)(vcpu); + + /* + * At RESET, both Intel and AMD CPUs set all enable bits for general + * purpose counters in IA32_PERF_GLOBAL_CTRL (so that software that + * was written for v1 PMUs don't unknowingly leave GP counters disabled + * in the global controls). Emulate that behavior when refreshing the + * PMU so that userspace doesn't need to manually set PERF_GLOBAL_CTRL. + */ + if (kvm_pmu_has_perf_global_ctrl(pmu) && pmu->nr_arch_gp_counters) + pmu->global_ctrl = GENMASK_ULL(pmu->nr_arch_gp_counters - 1, 0); } void kvm_pmu_init(struct kvm_vcpu *vcpu) From patchwork Sat Mar 9 01:36:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13587472 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9630B22F13 for ; Sat, 9 Mar 2024 01:36:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1709948210; cv=none; b=DAAZZkQ0+AmjG4LhMIh2cO0x29LvojVi1FBpjyMc6/Z4UMpMi7E6JL7x5VylzbTib15BH61dplp4SSk+WJPhLCajdt/vDBhpm2LFCcA6alpTCtRSJDJrBm3CiWhOCqhT8kV7c52FoHAj/QNbeWbr7q4E+04PEdvZi6PlEmnpFr8= ARC-Message-Signature: i=1; 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b=qr8oriFRBl6x5ogtJyuZc/tDLhlOhJSr9DKm1pblzFts8xePw+7T7PF693w8aG79TC h6sfSPhhs1xsxI+mNVE9Yl5SlecmICsVTKAlcuEu1JzCrjAbwzyYXzkVpeiMCfrrGbQF 4eYx/V4V0iJgY3If+KlMcRcDdA1/JzFJ9mkMG6VylrYkjBMLXoOQbtVGuFsPVVKBtolQ zVG8Yf72ubMkX5wMvziWQhRiiMz8AdWW51o/kBRaqxqp2plA9QJ5o/Z1X4qh5Algtgae 1rJfRWspdpkOtgzszbN/LxyDcu1U3IsmK/Cr07FgReLvScdeEXjbuui+mdhEUVaDOf8W /iuA== X-Gm-Message-State: AOJu0YwHfqMb0WA6NHNcomYtNjYRKofol/Y5uxOuXRmkQvSHm1us+54W b+R51YUJQ7MDyQ/z3hmjxnXe1QMiOLmouxtGYF5XR4JmI/Um2QddcPxykOTGiXrFTf153a++aN4 jwQ== X-Google-Smtp-Source: AGHT+IFvwDv/b0ydhsjPUXHw+jUb9gLdfBmL+i1F0ATMcxKeC9RIVzkgTlzWkZAwh4wYWsQF1XGiHgwcQwY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a05:6902:100d:b0:dcc:8be2:7cb0 with SMTP id w13-20020a056902100d00b00dcc8be27cb0mr40937ybt.0.1709948207688; Fri, 08 Mar 2024 17:36:47 -0800 (PST) Reply-To: Sean Christopherson Date: Fri, 8 Mar 2024 17:36:41 -0800 In-Reply-To: <20240309013641.1413400-1-seanjc@google.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240309013641.1413400-1-seanjc@google.com> X-Mailer: git-send-email 2.44.0.278.ge034bb2e1d-goog Message-ID: <20240309013641.1413400-3-seanjc@google.com> Subject: [PATCH 2/2] KVM: selftests: Verify post-RESET value of PERF_GLOBAL_CTRL in PMCs test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Babu Moger , Sandipan Das , Like Xu , Mingwei Zhang , Dapeng Mi Add a guest assert in the PMU counters test to verify that KVM stuffs the vCPU's post-RESET value to globally enable all general purpose counters. Per Intel's SDM, IA32_PERF_GLOBAL_CTRL: Sets bits n-1:0 and clears the upper bits. and Where "n" is the number of general-purpose counters available in the processor. For the edge case where there are zero GP counters, follow the spirit of the architecture, not the SDM's literal wording, which doesn't account for this possibility and would require the CPU to set _all_ bits in PERF_GLOBAL_CTRL. Signed-off-by: Sean Christopherson --- .../selftests/kvm/x86_64/pmu_counters_test.c | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c index 29609b52f8fa..26c85815f7e9 100644 --- a/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86_64/pmu_counters_test.c @@ -416,12 +416,30 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters static void guest_test_gp_counters(void) { + uint8_t pmu_version = guest_get_pmu_version(); uint8_t nr_gp_counters = 0; uint32_t base_msr; - if (guest_get_pmu_version()) + if (pmu_version) nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); + /* + * For v2+ PMUs, PERF_GLOBAL_CTRL's architectural post-RESET value is + * "Sets bits n-1:0 and clears the upper bits", where 'n' is the number + * of GP counters. If there are no GP counters, require KVM to leave + * PERF_GLOBAL_CTRL '0'. This edge case isn't covered by the SDM, but + * follow the spirit of the architecture and only globally enable GP + * counters, of which there are none. + */ + if (pmu_version > 1) { + uint64_t global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL); + + if (nr_gp_counters) + GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0)); + else + GUEST_ASSERT_EQ(global_ctrl, 0); + } + if (this_cpu_has(X86_FEATURE_PDCM) && rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) base_msr = MSR_IA32_PMC0;