From patchwork Tue Mar 12 14:38:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4D311C54E60 for ; Tue, 12 Mar 2024 14:41:20 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3HN-0003Vw-MO; Tue, 12 Mar 2024 10:38:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HL-0003V3-KR for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:38:55 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HD-0007iL-Qb for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:38:55 -0400 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-5dc949f998fso5126932a12.3 for ; Tue, 12 Mar 2024 07:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254325; x=1710859125; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+H4gb0JZklIT8hGflGjARBk523KJUlTbHGv63Qa3NVo=; b=L5VtP5TBMzfW6z190PqZObdPrXZIvMQGknkJRBgCmYZ8hK4Gh3GItTE6o0YsZFraWe hS3Mhk6SqH8rtEsrOiq7yaMabTkogJn7OT04tqudTAyu/C/cKtUIueKQXwaN9LZqP7S/ TeXW/y6wvandxsE5gtQ6AneyuQSazMOq3ULbkIiGPygZzvy9NRai0OXnqbEc7c64DOBx thyOoPEIpjc2qTbf4ejw6OgCGHF9ShnOvSnk6eiUQ3iz4KDeVBjWG9XRRPc7PFnkwqF4 5t3H2Ca6unZ63//zI/E5c5Hod/OoYsLf1ISjOebfxggWrPelL1WQK9/e96Fu7I8nOBRj XFAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254325; x=1710859125; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+H4gb0JZklIT8hGflGjARBk523KJUlTbHGv63Qa3NVo=; b=FiSMXem3GjD6O8DKgIkFYUBZ322j2p2zFcETEMmXc3cdF00XKX8AX+lfosjB1UsVn2 PqlYYc1zPW94It7JmTrBqVN9t4+4KoQp+qSA0Gw2i2886ft6ThR4y9jW48T5G9TouMQU 6kZDiiHc3ig4dviLkuBqMpTpPMgjPq69sXBbOAOqdPa2SifjwHbcJhVTNiiL5HYwwNWT 1uLa/GopWsqIWTwHL7/lP75h3so3j5/Kdv02BXAvktz1/0xEBey7KqyO4ZUp43SGZ+yV YAmoQAOPUy77uz8bZKWNhb5CTBOS2Ee3AngYIBlyLC2QsJjA2JslIgdh6X+6voizM5FH LTKg== X-Gm-Message-State: AOJu0YyI5uZ6dleuaSu6hNhcF9mtZOyx5TQc5sg8pvkPAX1zeRnxxUQm Uf0G1ND3YAQ23REZqGDWMGgCf1IMLQRabKnyfzp47EgT0SbH/CP+mc5RKtbCORf77oCNvl4WUAy A X-Google-Smtp-Source: AGHT+IGTpWip/BLsisPEtx6zSjrRYDA9hCDrR8obtFb2GrDS7YZvoENFAVJrNYKU8yoxignOJ8dS9Q== X-Received: by 2002:a17:90a:390c:b0:29b:a509:30aa with SMTP id y12-20020a17090a390c00b0029ba50930aamr2148609pjb.14.1710254324815; Tue, 12 Mar 2024 07:38:44 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 01/15] tcg/optimize: Fold andc with immediate to and Date: Tue, 12 Mar 2024 04:38:25 -1000 Message-Id: <20240312143839.136408-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 752cc5c56b..2ec52df368 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1324,17 +1324,23 @@ static bool fold_andc(OptContext *ctx, TCGOp *op) z1 = arg_info(op->args[1])->z_mask; - /* - * Known-zeros does not imply known-ones. Therefore unless - * arg2 is constant, we can't infer anything from it. - */ if (arg_is_const(op->args[2])) { - uint64_t z2 = ~arg_info(op->args[2])->z_mask; - ctx->a_mask = z1 & ~z2; - z1 &= z2; - } - ctx->z_mask = z1; + uint64_t val = ~arg_info(op->args[2])->val; + /* Fold andc r,x,i to and r,x,~i. */ + op->opc = (ctx->type == TCG_TYPE_I32 + ? INDEX_op_and_i32 : INDEX_op_and_i64); + op->args[2] = arg_new_constant(ctx, val); + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer anything from it. + */ + ctx->a_mask = z1 & ~val; + z1 &= val; + } + + ctx->z_mask = z1; ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; return fold_masks(ctx, op); From patchwork Tue Mar 12 14:38:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 77177C54E58 for ; Tue, 12 Mar 2024 14:43:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hn-0003ZT-GN; Tue, 12 Mar 2024 10:39:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HY-0003Wr-2P for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:08 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HE-0007ik-Hs for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:02 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-29bb3d62949so2882512a91.1 for ; Tue, 12 Mar 2024 07:38:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254326; x=1710859126; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=RnJQyEnXrtZcjBCHyJq+5yv9WO+0xDyYir75PeP3MhY=; b=kATDgmQmhJ+Ob75w7trJZRHt1FX2uoW08aQ7rPUJuhsowzunuksXXI8COqL7KFa5q9 BBMCppjRk6pCRdeycPIBdm21hLl1qCS0rRi1vF8Gw1nVIJJjl6OhqjTsdqtgvBrZFXRx xcKyHq0BsU7BA7Qzie4T3H4VImzr6y0DboHps57edol7okikFC1DTNp7scKYLrE5XZFv ilzWIN84J1ZpBW3gaMyJItg8xUP2WMv+HbLeeUVkoSJp1tpzG5Feel3NfQSGR1oGMmYB oTIwB2WIiSnV4wWF1iGw3ynrHgC0WK/4+NR8EK2OcHIMj56kkgDbtSPbUcTrSdkvyJON 4p3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254326; x=1710859126; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RnJQyEnXrtZcjBCHyJq+5yv9WO+0xDyYir75PeP3MhY=; b=bnvxQpTdBAjd1Fb+epOctBSGskOSC1rzgzToYAsq+mpNRuShxeunHNtR5qRSWEz0oY 3cxLUbi1L4khgdAKnG8Qypg09jJPMkQTq3nb5qE0vUnsavdm/WxB0MlzK3SbBDt61hvq 83IL/Dcq1DXQnqpfa4lMTT5/Rdlvqf32oPuro/F8WpTOe8wrgb3h/4+a2oHOYmRJyId7 HgWUeB30+HODGzwn1+zBMbqUo0GqvAeNHZFpGli8k218ml1mq0btBmhz029qo4E2HZig b7et40TY+PFTNlv9owvOw4qHJGmU1eNj41xM8pJbbR5pKa3Fl4P4AY4iHyFUujpunJG2 aQBw== X-Gm-Message-State: AOJu0YwAKCg0Xcz3NlzRo/iPTY7BoWstzpkPRFX/hkCEFIP8MnyeX7EI NhxiaXgmIoMJ3JPIPNlHcdKSZDDjTSVuyvA2PY/PLSSw4DtERjaHzwCA+sEXReDoqtO/o1blrCW s X-Google-Smtp-Source: AGHT+IHKhVf+TXwzt/cKB0dC0VBh7J2msvqV1qn10M5SoKWsCQIs3Vd5NkaqFfOnjyjiHijls1gydA== X-Received: by 2002:a17:90a:fb57:b0:29b:af8d:3264 with SMTP id iq23-20020a17090afb5700b0029baf8d3264mr1933099pjb.37.1710254326258; Tue, 12 Mar 2024 07:38:46 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/15] tcg/optimize: Fold orc with immediate to or Date: Tue, 12 Mar 2024 04:38:26 -1000 Message-Id: <20240312143839.136408-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 2ec52df368..5729433548 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2065,6 +2065,15 @@ static bool fold_orc(OptContext *ctx, TCGOp *op) return true; } + /* Fold orc r,x,i to or r,x,~i. */ + if (arg_is_const(op->args[2])) { + uint64_t val = ~arg_info(op->args[2])->val; + + op->opc = (ctx->type == TCG_TYPE_I32 + ? INDEX_op_or_i32 : INDEX_op_or_i64); + op->args[2] = arg_new_constant(ctx, val); + } + ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; return false; From patchwork Tue Mar 12 14:38:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84998C54E5D for ; Tue, 12 Mar 2024 14:40:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hj-0003YN-6K; Tue, 12 Mar 2024 10:39:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HY-0003Wq-2N for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:08 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HG-0007jd-WD for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:02 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-29b9f258cd9so3749757a91.3 for ; Tue, 12 Mar 2024 07:38:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254328; x=1710859128; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=UlKx6mBylhjK+QdjE0ijHuQmNK+qb5/whrN67puRMnA=; b=BsGiqLqc0NQw+VkQFAH6Gn6UKq104TsDyj9edqN+o1Ie3m0cvymqpkueyMLHksYM28 xDkPFiQbfsz2+BWeou0TkeVgQR6BxJyCqQJaJevu9lkcWSqbn8AOwGrlssPW4U5jGYMd vYlKScUEW3Xppm/p4E+BNhLoJmVGM15D9urfdJxyk5sYmNem5glwVW8zKquOeULZ+3a0 u7V5iIkWN0zQ7lBHzNpT+uJYrXjuc5/gwhUvDvpxHxsZdDPhtwVWG2sg6QaUDgjgkUgJ 0JikBdJpZUABJcUa29f5WQvGes2GbOSzEXzjJ+JbALy9v1lNCN6QTkRRQqfzErh3f6md GuCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254328; x=1710859128; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UlKx6mBylhjK+QdjE0ijHuQmNK+qb5/whrN67puRMnA=; b=WGn1hS6zzagFcZo+dsR+Rr1q2A7G0MfEAWL7sDWa3eECswOhIykeeSfRZTlR0v9to3 WyrWkqbp66Wi7gJWurxOlGWmUJMy29M7UYlCsrsFIyfAsMO0rIrDrjEyi5HFi+sJW0Q9 AZ8ygA9rVCh7NIz6tqjK7cdWLzBvDlfH/ei/gYhtrQjf9AlYT04i2OrEdAQeR6T8Bm+G lbFlTD7C/P6Xzfazktfj8jZAtnNtX7etHPIozlTzensQi/Mp/x7OD7nxk+5eRgvR1mzM WVS+key4s2smDY9fZKoLaDBSjBwQufXBlIoaoS4P9of4BGBo3AYVWMOUy6MoW1Z5LXjO Yw4A== X-Gm-Message-State: AOJu0YyIvq1QaqQwU36IfhbILCMVGJkz3JEirlS5QQbtvwTTzt+oSMXs mPzIdWmTaYOg14Y4blPEHm3OCJvHG/60LfkM/Qoi4xnncUIqvdU8bnWVP30d8TjYTOP+2laDREM c X-Google-Smtp-Source: AGHT+IGd6D4siOHpMaxb79mZ3fOIoUhRm4B32YyGvaQbvpzb3rApXzrTIjwjHI6TAVXbx3MMpehvug== X-Received: by 2002:a17:90a:fd8e:b0:29b:c13d:457f with SMTP id cx14-20020a17090afd8e00b0029bc13d457fmr6619187pjb.19.1710254327779; Tue, 12 Mar 2024 07:38:47 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/15] tcg/optimize: Fold eqv with immediate to xor Date: Tue, 12 Mar 2024 04:38:27 -1000 Message-Id: <20240312143839.136408-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index 5729433548..c6b0ab35c8 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1687,6 +1687,15 @@ static bool fold_eqv(OptContext *ctx, TCGOp *op) return true; } + /* Fold eqv r,x,i to xor r,x,~i. */ + if (arg_is_const(op->args[2])) { + uint64_t val = ~arg_info(op->args[2])->val; + + op->opc = (ctx->type == TCG_TYPE_I32 + ? INDEX_op_xor_i32 : INDEX_op_xor_i64); + op->args[2] = arg_new_constant(ctx, val); + } + ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; return false; From patchwork Tue Mar 12 14:38:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EF7BCC54E58 for ; Tue, 12 Mar 2024 14:41:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hz-0003co-GJ; Tue, 12 Mar 2024 10:39:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HZ-0003XI-9Z for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HI-0007jl-41 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:04 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-29c23f53eabso1171708a91.0 for ; Tue, 12 Mar 2024 07:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254329; x=1710859129; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=nauksK2e7Q6WDYDd+VxmoOkYOzpKhwUNqATghqi1W1o=; b=cE6362RLwa/WE8xuQF2uNmluduGAju8nq8RxX3QebsxMR0Wni059khizwMYdrTmVux A1pDsv/3e3uRmopE+bmWvYTq/uPmmNwTkT/aCigN6xzCVLprbLencDchEe2RFb3v1G8m Aopgz9aG6x/SW/RkjA02udf+6965mX4qxsJJ92lAEERxBCc7r836XX6/HZUKYv4KPBpl xhxrOO4DNzDriWJ2v0o1JV7HK89v1k9Bw3rn2dwO9aM69pnrowtsMr8Q8uEz+wl7vwOC iPx+uMWm9S0Dz7fUybjV5mxc+RZ5BLrmDOGSVu8BVFXQziHrXCHm/jWHhCTpC3rlU5vx +9NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254329; x=1710859129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nauksK2e7Q6WDYDd+VxmoOkYOzpKhwUNqATghqi1W1o=; b=FyFa7ZcnnFMrnCN1lKxZchzG/Z5ZWRgE7GEZvbUkrDw9CSQa8pmGSb0dT0hLg2YHzZ jwYwIXkcGWFXd02c2TJloSnbHpYIWD4IK1qFS7+x40oUIR0CRj7p/At5PNJ2rcaUrPSe T5g9aLhz/wMeHm0a8QCvhc0GcGaA3ovGhFWxyVXxRfP3FEYx7NbCFPvZO5cjMPsPmUGj vI7XU4E2U/ugC13olFzCqXKEr/zGWP/XUQ6dHxxhiss0GbrL5j1fRLs8DWriB7fXyyZV ToBjcu8vzQMolUZwBY9yCfsr033IR0GlEMfmrwlDXP226x8IGauCeqOkkWgMviNSGhpM ZMaQ== X-Gm-Message-State: AOJu0Yz8H4HaOu419awcjAOKg0wGq81yU9i2xx58znP/iAe+6ta6PFE3 lWdMRH/7LPXQtT6vLhdu/I2vGzr3wk60HFEI2H3xrjZ2E0u6xAFxnD5BqSahpTZwjztIcUe9ZjQ W X-Google-Smtp-Source: AGHT+IGvpCf77yTRFxhE+2188kmtd9jaKw2/y0ZdzkVlBxpLo+6Sa4+H4AKsqiuLHfNY6EhB6flTsQ== X-Received: by 2002:a17:90a:e60a:b0:29b:9f14:e18e with SMTP id j10-20020a17090ae60a00b0029b9f14e18emr6881687pjy.40.1710254329236; Tue, 12 Mar 2024 07:38:49 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/15] tcg/i386: Do not accept immediate operand for andc Date: Tue, 12 Mar 2024 04:38:28 -1000 Message-Id: <20240312143839.136408-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformation of andc with immediate to and is now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target-con-set.h | 3 +-- tcg/i386/tcg-target-con-str.h | 1 - tcg/i386/tcg-target.c.inc | 20 +++++--------------- 3 files changed, 6 insertions(+), 18 deletions(-) diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h index e24241cfa2..69d2d38570 100644 --- a/tcg/i386/tcg-target-con-set.h +++ b/tcg/i386/tcg-target-con-set.h @@ -40,11 +40,10 @@ C_O1_I2(r, 0, r) C_O1_I2(r, 0, re) C_O1_I2(r, 0, reZ) C_O1_I2(r, 0, ri) -C_O1_I2(r, 0, rI) C_O1_I2(r, L, L) +C_O1_I2(r, r, r) C_O1_I2(r, r, re) C_O1_I2(r, r, ri) -C_O1_I2(r, r, rI) C_O1_I2(x, x, x) C_N1_I2(r, r, r) C_N1_I2(r, r, rW) diff --git a/tcg/i386/tcg-target-con-str.h b/tcg/i386/tcg-target-con-str.h index cc22db227b..0c766eac7e 100644 --- a/tcg/i386/tcg-target-con-str.h +++ b/tcg/i386/tcg-target-con-str.h @@ -27,7 +27,6 @@ REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */ * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('e', TCG_CT_CONST_S32) -CONST('I', TCG_CT_CONST_I32) CONST('T', TCG_CT_CONST_TST) CONST('W', TCG_CT_CONST_WSZ) CONST('Z', TCG_CT_CONST_U32) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index c6ba498623..ed70524864 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -130,9 +130,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 #define TCG_CT_CONST_U32 0x200 -#define TCG_CT_CONST_I32 0x400 -#define TCG_CT_CONST_WSZ 0x800 -#define TCG_CT_CONST_TST 0x1000 +#define TCG_CT_CONST_WSZ 0x400 +#define TCG_CT_CONST_TST 0x800 /* Registers used with L constraint, which are the first argument registers on x86_64, and two random call clobbered registers on @@ -203,8 +202,7 @@ static bool tcg_target_const_match(int64_t val, int ct, return 1; } if (type == TCG_TYPE_I32) { - if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | - TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) { + if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_TST)) { return 1; } } else { @@ -214,9 +212,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { return 1; } - if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) { - return 1; - } /* * This will be used in combination with TCG_CT_CONST_S32, * so "normal" TESTQ is already matched. Also accept: @@ -2666,12 +2661,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; OP_32_64(andc): - if (const_a2) { - tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, a1); - tgen_arithi(s, ARITH_AND + rexw, a0, ~a2, 0); - } else { - tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); - } + tcg_out_vex_modrm(s, OPC_ANDN + rexw, a0, a2, a1); break; OP_32_64(mul): @@ -3442,7 +3432,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_andc_i32: case INDEX_op_andc_i64: - return C_O1_I2(r, r, rI); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shl_i64: From patchwork Tue Mar 12 14:38:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75C3CC54E58 for ; Tue, 12 Mar 2024 14:41:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hr-0003Zy-EL; Tue, 12 Mar 2024 10:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HZ-0003XJ-9J for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HI-0007ju-46 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:04 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-29be9c136a2so1964174a91.0 for ; Tue, 12 Mar 2024 07:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254330; x=1710859130; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=aSfVCHCwzSzRVXOz7WshzegXhabuAUGT/As/uR9fcX8=; b=S9Fl3hzVee0ld3o4lmT9yAcTxyMWObfHb+EWpcd49Aic4VRuZrOV2wvsgTFN3ShdYb 8Jwx7AxclNcwR0wHntJlMJ0+GFBV0EK05Vmn3OSCQN76Y7u3TQZs+Pfe6jOVZvHARBT5 JWNPu0jq2ZzbAYsuxSePSf+QdwhOth4uZVPD9zSU08slh/jlu0XaIVAKhC37IQa0v7fD FG3EHPG+t2MCyC4sepehKEhHarZlUIqs6oZhLiT/xhacFm/+uiXy1iKWBeb5b9OIHFTk 8IuFuaRw2Jk7n1aLeWLLaHqaR19m7Nv77fpOZvF0tZBxUZ6iaI+OsZvv57w5iktqwkyV 6vzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254330; x=1710859130; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSfVCHCwzSzRVXOz7WshzegXhabuAUGT/As/uR9fcX8=; b=OKrliT36GV31EWWTHX1nQDe9FwUcfl1zCr5S42CBeB+7OKnuoHR9Lt69ybvQKqmBXV odhCBx3GayG65tjTTtPEI7AMZJzLYmDfLyhkxLrl5CCki16ESPRTJyJFOC+NkCXX+vbL Xs6sPbPq8KEyKbMtc4eLuJw9q1tXj2RE+Ur/trfRCpgv3y979LgnCLqc6TgGHe8OUpks ATcwOma05R8EUiiquodZdU4DakXiCT5sQ0661iPymeqvY8GLLaSzon6UXAJ2S5p04b7X U7te4NLceH+qfy3VPxkw06HRcxHA+4fDgjkaBHzTmNWi3vc7RgbaPpLckd9HscrvBESs 8G/g== X-Gm-Message-State: AOJu0YyO1ZcwenFvtah0MimgB1gsdkwpImJfLOHkV7Jq4jEH9LQN0v+M s0rAaNzTKEm6S2lZA8AKHXxRlOX8mJeTYaarOeEomtNk2kkMWJVoESEleB2B0bDRLwthjU1UQfh s X-Google-Smtp-Source: AGHT+IHzYTJFgwTi9pNPUBNV/c2jjSUMP/9bUdAw0FSNZpCtEyg6lIS46LVM43bzZafTUFLN5wXF2A== X-Received: by 2002:a17:90b:3ec3:b0:29a:e0bc:4a9b with SMTP id rm3-20020a17090b3ec300b0029ae0bc4a9bmr7969926pjb.16.1710254330634; Tue, 12 Mar 2024 07:38:50 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/15] tcg/aarch64: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:29 -1000 Message-Id: <20240312143839.136408-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 50 +++++++++++------------------------- 1 file changed, 15 insertions(+), 35 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index dec8ecc1b6..68a381e4af 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2216,17 +2216,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_andc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_andc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); - } - break; - case INDEX_op_or_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -2238,17 +2227,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_orc_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ - case INDEX_op_orc_i64: - if (c2) { - tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); - } - break; - case INDEX_op_xor_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -2260,15 +2238,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2); + break; + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2); + break; case INDEX_op_eqv_i32: - a2 = (int32_t)a2; - /* FALLTHRU */ case INDEX_op_eqv_i64: - if (c2) { - tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2); - } else { - tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); - } + tcg_out_insn(s, 3510, EON, ext, a0, a1, a2); break; case INDEX_op_not_i64: @@ -2995,6 +2975,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rC); + case INDEX_op_andc_i32: + case INDEX_op_andc_i64: + case INDEX_op_orc_i32: + case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: + case INDEX_op_eqv_i64: case INDEX_op_mul_i32: case INDEX_op_mul_i64: case INDEX_op_div_i32: @@ -3015,12 +3001,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - case INDEX_op_andc_i32: - case INDEX_op_andc_i64: - case INDEX_op_orc_i32: - case INDEX_op_orc_i64: - case INDEX_op_eqv_i32: - case INDEX_op_eqv_i64: return C_O1_I2(r, r, rL); case INDEX_op_shl_i32: From patchwork Tue Mar 12 14:38:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590097 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B76DC54E58 for ; Tue, 12 Mar 2024 14:40:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3HY-0003Wp-RP; Tue, 12 Mar 2024 10:39:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3HT-0003W9-1k for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:03 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HK-0007k3-Dm for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:02 -0400 Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-29bf9bd1907so1663615a91.1 for ; Tue, 12 Mar 2024 07:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254332; x=1710859132; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+U6hRnnu1FyU4GsVaJb1EG0lBm+OsXguv63B7cAYsao=; b=TwKx0AFKsZ3v2ZvZvWI/sUGh4FlySEmwpNeWZLEHmROiaIBoVXEIpjzhLdRnqZQTgf y8LHMOSRJnQ6eOVzkdMeDF/GF8+fRi/xXYdgz1/uizXNIgZAM5nGOpEL/n9cXfV10dtc B5dX26tdPrppvayN+oI9L7wD+Bd7jdUx9TqojK0SysPeI4o+3nz2EV7lzGrbVTiB5R5K ww+/XtwW6L7XCtqdfAMNPL4LzmsB1bjOBN2P4gYICJC3ARyM8AxJA17NX9RPgduF/e8+ CQ8lx6JNMEsnUJHxU0KcgfqsZ2jT75Mxldsn+eg1wtcO4JYdKT3C2G9Q1ZibjsAY9MJQ DZhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254332; x=1710859132; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+U6hRnnu1FyU4GsVaJb1EG0lBm+OsXguv63B7cAYsao=; b=A4gY0uwNUzY6dSFpW6sTLavDNx4SbcV5NggrY0GXLSEo89Mt6fAgchlNXZLa5/DiFB rm8nTlOrwjmcpfGjvpaLYn8GqdK//x1bM4yTBWxWH4/H3PHeR0EnAku3ooxG8an4mj4O ntErhwRxy6iezfP0w4unwsZX9XTw7Tny/9FSkDAlOLfWWTyEmqyQGR1fSOMeTgmqOnIC a4XibAj/aT73+v1XHUpLtREMVQs0ADRVTlRVNuh42cBOBEQ8xS0Rrd/C/Fxmi6yH99gk OOselvSX31v3/kG3KoLeAmdw7sc9pkd/eC1Hz1wasCYHbeVJs/+0gQq08DQnnKIV1iZz kDZw== X-Gm-Message-State: AOJu0Yyl8PwtcAcGarzYa5B5uYGFiNOH0nGD8bYFqdNEER1mfhw4Z4/t PuhHWjIOJwl71ec0fd9gg6zD25Px3bYYaFoGucZ7AAKn6rKa6e+teET+LsUNVD4MoTM/shuLQTb 7 X-Google-Smtp-Source: AGHT+IHzn+c36MROMu7wMybNlQqmjmRkixnEtRkcngcluvCyIATvshm+YdoD4MGDHvjBOdfgO6UsxA== X-Received: by 2002:a17:90a:d714:b0:29b:75b0:994d with SMTP id y20-20020a17090ad71400b0029b75b0994dmr590990pju.42.1710254332118; Tue, 12 Mar 2024 07:38:52 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/15] tcg/arm: Do not accept immediate operand for andc Date: Tue, 12 Mar 2024 04:38:30 -1000 Message-Id: <20240312143839.136408-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformation of andc with immediate to and is now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 6a04c73c76..a0c5887579 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1869,8 +1869,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], const_args[2]); break; case INDEX_op_andc_i32: - tcg_out_dat_rIK(s, COND_AL, ARITH_BIC, ARITH_AND, - args[0], args[1], args[2], const_args[2]); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, args[0], args[1], + args[2], SHIFT_IMM_LSL(0)); break; case INDEX_op_or_i32: c = ARITH_ORR; @@ -2152,11 +2152,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I2(r, r, rIN); case INDEX_op_and_i32: - case INDEX_op_andc_i32: case INDEX_op_clz_i32: case INDEX_op_ctz_i32: return C_O1_I2(r, r, rIK); + case INDEX_op_andc_i32: case INDEX_op_mul_i32: case INDEX_op_div_i32: case INDEX_op_divu_i32: From patchwork Tue Mar 12 14:38:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590105 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58440C54E58 for ; Tue, 12 Mar 2024 14:41:45 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I2-0003eh-Je; Tue, 12 Mar 2024 10:39:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Ha-0003XZ-Ka for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:12 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HK-0007k5-Ph for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:08 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1dd6412da28so31257555ad.3 for ; Tue, 12 Mar 2024 07:38:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254333; x=1710859133; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=6WDUOYZWLT555AjxYlW12yt2eENGmiwsLor7nsvhIVw=; b=lRLcYKbkvLIoyBXEn13gBq0+IFApEDPWli8p9TsfDu3IbnvqDiq2QCh5MAFkd4/pJs y7v2+5bNr+WJnl9v/18xoHdr4DpznzpJlhlwhIpv9+cjQMyNF5koCLVDamDCgkaR+Pjj GThT+byZghQAb23dkRA1dI5L4xyuHoamGAJz9nNd/DDfNolbXuqpty6qUFoAVySvB+s8 +fNcXFgLIjWoKYyEr5m5zd3BexKobwc/ptgcIQrz9vMmLj5oZC56NDn5tX0cPxSqAAaH suJLWOquxWJtiVKflSbtNxY5gxfkf6vYUX3BG2xIdCDAToMICHaTdMqGi7LuibvEl70+ Ek8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254333; x=1710859133; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6WDUOYZWLT555AjxYlW12yt2eENGmiwsLor7nsvhIVw=; b=PZesqedBw325K46BUVDn6bjtKdJwWgUqXxpsoIUNR3klGUwGn4OCpY220pIB9/Jnb9 UEWE264EGZYz+Cixih9lLMsDURbmTfEJCxQdOHVUjI32Z6Gd34O+Xt+SOuQkN0wF3VGA Qin5oZMbwiK8JG+CQn+lGbBT+LihohAkQjM4GuTZ8y/TGDnoHishOOsYdGLzX3sQZf4w 7TViC3AhWbifamajM0w1GusJmACa5g3bWcQnMFGWRnuQi5FnWEPCYDH7Q/QA+lm9mXUv Se1rApG0LoDgjToiqnA83Epjg/mw2RM3rMHcc2uzTCrrM4kdezevgNOTk431Kdq6vCzc Pzaw== X-Gm-Message-State: AOJu0Yz/U6sW5ijXl0dxAxF78HnEZSfQZtoya/M60j0TuTtCc2MUeGgH Cl8Y6DHIYIB8oDelfl2E2xj2R3dZd+Ug8TDj2yEd8/ttWnTFIKcjeVUaGpwHYH+h2YtDXPxBh0g n X-Google-Smtp-Source: AGHT+IFaMkrDWHpiY2l+oYdKcp54wHTy7L5FTS2UYvlT/xgW9ehyio4yPtRZ7DllwhIGPfaSRAPpVQ== X-Received: by 2002:a17:90a:77c5:b0:299:1777:134c with SMTP id e5-20020a17090a77c500b002991777134cmr3281311pjs.33.1710254333445; Tue, 12 Mar 2024 07:38:53 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/15] tcg/ppc: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:31 -1000 Message-Id: <20240312143839.136408-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 32 +++++--------------------------- 1 file changed, 5 insertions(+), 27 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7f3829beeb..336b8a28ba 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3070,36 +3070,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi32(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } - break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_andi64(s, a0, a1, ~a2); - } else { - tcg_out32(s, ANDC | SAB(a1, a0, a2)); - } + tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); break; case INDEX_op_orc_i32: - if (const_args[2]) { - tcg_out_ori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: - if (const_args[2]) { - tcg_out_xori32(s, args[0], args[1], ~args[2]); - break; - } - /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; @@ -4120,16 +4098,12 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_and_i32: case INDEX_op_or_i32: case INDEX_op_xor_i32: - case INDEX_op_andc_i32: - case INDEX_op_orc_i32: - case INDEX_op_eqv_i32: case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: case INDEX_op_and_i64: - case INDEX_op_andc_i64: case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: @@ -4145,10 +4119,14 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i32: case INDEX_op_rem_i32: case INDEX_op_remu_i32: + case INDEX_op_andc_i32: + case INDEX_op_orc_i32: + case INDEX_op_eqv_i32: case INDEX_op_nand_i32: case INDEX_op_nor_i32: case INDEX_op_muluh_i32: case INDEX_op_mulsh_i32: + case INDEX_op_andc_i64: case INDEX_op_orc_i64: case INDEX_op_eqv_i64: case INDEX_op_nand_i64: From patchwork Tue Mar 12 14:38:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA668C54E5D for ; Tue, 12 Mar 2024 14:44:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I1-0003eb-4O; Tue, 12 Mar 2024 10:39:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Ha-0003Xb-Ll for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:12 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HL-0007kK-Rq for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-29c14800a7fso1409131a91.2 for ; Tue, 12 Mar 2024 07:38:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254334; x=1710859134; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=jbNLo5y1YUnPREukd4mIwrgqxX0R9HS5MZo8QZlenPA=; b=EyMHQIROka49yu0z6FCyh9iWfivz0aJvFOVJDT897Nz0Lbi9nrPUVdViaS3Rguq5OK lr2uN9ZosPpleiFxtScNGRMhYYFJPhEV0ZF5orR4dKBtAIaGx57DJyj4euOjxJxwlG+W kSJ3yZblpu4Oawpu94qys8jDbyWyyh9r5EPoR9vB7PnTDALITphS+sHwhX7w1PIPsUGu /DcN711UtfpN4Xu5azWh/XcTM4+d0BdtFjhyJDuU+LNPdX48NXAEtkxL8fKhuhgqxyaQ MTA3ZeO4lVuz3KvxslfUdiOqP9NPBG/Eti7OMxyUm3WL7nwit1lue5UvaIpKXwIgKZfA 4EvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254334; x=1710859134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jbNLo5y1YUnPREukd4mIwrgqxX0R9HS5MZo8QZlenPA=; b=hprl1sdYgVCCawH5cXFLbj+TYjVxoRgVuwAGnNqFq/eeIfBITwb3sYcP4K0iOOc+VK ApW/XaIszmK35O9dZneChp/UYjw4Ue+gdwZMfl+K7CKqxMENEdBQ3GFHBhvU5/TJj6B2 Dmtn5f1UlAxMIDID9UFCjpG995C+oGqz4whV1vAKnIdzHNCxT3DqbGIyqUZsEaz15Wtf 91IChrgr3T0AYsKc7sCTFjEChEKtq67fZJq7/2/ANJDEMkzxRZbkXoa0QUAbP2Llb8gz GtgbH3ArUfSvm6BbzxVI2yPoPv/IHSWNx86HEwECKOek+FRdCM3F05YKM2kLnWeLMnVk nddA== X-Gm-Message-State: AOJu0YwiMKjU0PwRfk6ll6T0gMG0+xeXHynF1Zddt3LYKIp2SXg4P9Du RxLLvmdNMum2tIbvOUWlqGrJJlmSZHDv5wq3HWzdiqvg8kprRP4L4S0iVTZuN+BwPveQLVbMNIe g X-Google-Smtp-Source: AGHT+IFdW2IFo8FNHQrGTtqM5B79OCqEmlLHO6DKMOtd/2wO+pPwVS+eJPlos5TCFwM/HwU/8+aiOA== X-Received: by 2002:a17:90b:4c87:b0:29b:3cae:c50d with SMTP id my7-20020a17090b4c8700b0029b3caec50dmr2221819pjb.0.1710254334606; Tue, 12 Mar 2024 07:38:54 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/15] tcg/loongarch64: Do not accept immediate operand for andc, orc Date: Tue, 12 Mar 2024 04:38:32 -1000 Message-Id: <20240312143839.136408-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 +- tcg/loongarch64/tcg-target-con-str.h | 1 - tcg/loongarch64/tcg-target.c.inc | 31 ++++++---------------------- 3 files changed, 7 insertions(+), 27 deletions(-) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index cae6c2aad6..272f33c1e4 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -22,7 +22,7 @@ C_O0_I3(r, r, r) C_O1_I1(r, r) C_O1_I1(w, r) C_O1_I1(w, w) -C_O1_I2(r, r, rC) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) C_O1_I2(r, r, rJ) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-target-con-str.h index 2ba9c135ac..e7d2686db3 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -24,7 +24,6 @@ CONST('I', TCG_CT_CONST_S12) CONST('J', TCG_CT_CONST_S32) CONST('U', TCG_CT_CONST_U12) CONST('Z', TCG_CT_CONST_ZERO) -CONST('C', TCG_CT_CONST_C12) CONST('W', TCG_CT_CONST_WSZ) CONST('M', TCG_CT_CONST_VCMP) CONST('A', TCG_CT_CONST_VADD) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 69c5b8ac4f..e343d33dba 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -169,10 +169,9 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_S12 0x200 #define TCG_CT_CONST_S32 0x400 #define TCG_CT_CONST_U12 0x800 -#define TCG_CT_CONST_C12 0x1000 -#define TCG_CT_CONST_WSZ 0x2000 -#define TCG_CT_CONST_VCMP 0x4000 -#define TCG_CT_CONST_VADD 0x8000 +#define TCG_CT_CONST_WSZ 0x1000 +#define TCG_CT_CONST_VCMP 0x2000 +#define TCG_CT_CONST_VADD 0x4000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) @@ -201,9 +200,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { return true; } - if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { - return true; - } if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { return true; } @@ -1236,22 +1232,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i32: case INDEX_op_andc_i64: - if (c2) { - /* guaranteed to fit due to constraint */ - tcg_out_opc_andi(s, a0, a1, ~a2); - } else { - tcg_out_opc_andn(s, a0, a1, a2); - } + tcg_out_opc_andn(s, a0, a1, a2); break; case INDEX_op_orc_i32: case INDEX_op_orc_i64: - if (c2) { - /* guaranteed to fit due to constraint */ - tcg_out_opc_ori(s, a0, a1, ~a2); - } else { - tcg_out_opc_orn(s, a0, a1, a2); - } + tcg_out_opc_orn(s, a0, a1, a2); break; case INDEX_op_and_i32: @@ -2120,12 +2106,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_andc_i64: case INDEX_op_orc_i32: case INDEX_op_orc_i64: - /* - * LoongArch insns for these ops don't have reg-imm forms, but we - * can express using andi/ori if ~constant satisfies - * TCG_CT_CONST_U12. - */ - return C_O1_I2(r, r, rC); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shl_i64: From patchwork Tue Mar 12 14:38:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590106 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1899C54E5D for ; Tue, 12 Mar 2024 14:41:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I3-0003ew-Ez; Tue, 12 Mar 2024 10:39:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Ha-0003Xe-M6 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:13 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HN-0007km-Ka for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-5cf2d73a183so11456a12.1 for ; Tue, 12 Mar 2024 07:38:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254336; x=1710859136; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=/4kUSHiFCpPL9qQ3UOiS3LaHR+iaHi7L4Tr6+QKuD7g=; b=h3+muNBKfIxVTR9m70iLQsI6lEoOnuEryRaETdIhtI3bmsLXxUrOMGhXU86G23SmPf BG5D2gMBi1GXlNWnqMoVGLcEQhWUe5OXEkDqaHGT/eo9dwMpsqDSrIFlqQQYxeneBlyL LfGeP6a/q0mNRcqGWf3/S0myn+o7dnHmXXdOdwDuMG79ohJAdQ2F41ccoPE+wvVJ4mow HPDvfexaSV2JYyF0wLOmOtjfKUfmXLDHr+6/DYDNL7o0n6FA67rHR26TOQYSpJPd+IFp tRbJ3/RbF9hfwxUKZ7nv8yWJq7tl04eeuLBKoU6sC14ThwkWnB7Ciu4ljwAfq0HGRQWP DfTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254336; x=1710859136; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/4kUSHiFCpPL9qQ3UOiS3LaHR+iaHi7L4Tr6+QKuD7g=; b=X0nWmaC7N3MyHWKxPjgq5RMOQMg4PJ4XwH6SfW+Pns0DrkkKnDgCOqzUy6NTBvMl9N paxktRfQrxSiHn3km46rLR+oAu2CKJ7BTpQWxEq05YrZPkeCwbbdYuGy1fc2GyoAjswH MQxJgbszhEcF3ZOSxaUlapnZ21cLBlUcxgLEI5Dr0HHE+EBOrhzRxIVHmFak/S/ifTYM c+JKDQgpp/SESPl+9YVL0H2X1uNiSx9r3eJA1V23zSQfZcEwCh10yR8djz4Q9Fwzc9Ba FwIoo8WdxzjBJuTSdocS2GcxiJiV87DyefwB2kEV0PWe0HrDcmLF8z8N1xN4PyHPjRge t49Q== X-Gm-Message-State: AOJu0YxrObG+EixgrIVSYgrvoSGqaSF79U0sCsolZsjaCUOx7GktH61u NMFTBU+Ezh0BnhvhLmTgxYYqwCBW9TpkJ5gg2y0kQwogZKkT8oiZvZHECyPajK9QspNhqIoQr15 K X-Google-Smtp-Source: AGHT+IFcUBgePyeB82JACZt34VbG7Z2/dTgZLbqYHsgB/D9soIHNfDgoHrkj/4bbvEhSBycdzD74mA== X-Received: by 2002:a17:90a:2ce6:b0:29b:c432:c1bb with SMTP id n93-20020a17090a2ce600b0029bc432c1bbmr12061537pjd.24.1710254335929; Tue, 12 Mar 2024 07:38:55 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/15] tcg/s390x: Do not accept immediate operand for andc, orc Date: Tue, 12 Mar 2024 04:38:33 -1000 Message-Id: <20240312143839.136408-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 56 ++++++-------------------------------- 1 file changed, 8 insertions(+), 48 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index ad587325fc..b9a3e6e56a 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2216,31 +2216,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_andc_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_andi(s, TCG_TYPE_I32, a0, (uint32_t)~a2); - } else { - tcg_out_insn(s, RRFa, NCRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NCRK, args[0], args[1], args[2]); break; case INDEX_op_orc_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen_ori(s, a0, (uint32_t)~a2); - } else { - tcg_out_insn(s, RRFa, OCRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, OCRK, args[0], args[1], args[2]); break; case INDEX_op_eqv_i32: - a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tcg_out_insn(s, RIL, XILF, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NXRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NXRK, args[0], args[1], args[2]); break; case INDEX_op_nand_i32: tcg_out_insn(s, RRFa, NNRK, args[0], args[1], args[2]); @@ -2517,31 +2499,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_andc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_andi(s, TCG_TYPE_I64, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NCGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NCGRK, args[0], args[1], args[2]); break; case INDEX_op_orc_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_ori(s, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, OCGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, OCGRK, args[0], args[1], args[2]); break; case INDEX_op_eqv_i64: - a0 = args[0], a1 = args[1], a2 = args[2]; - if (const_args[2]) { - tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen_xori(s, a0, ~a2); - } else { - tcg_out_insn(s, RRFa, NXGRK, a0, a1, a2); - } + tcg_out_insn(s, RRFa, NXGRK, args[0], args[1], args[2]); break; case INDEX_op_nand_i64: tcg_out_insn(s, RRFa, NNGRK, args[0], args[1], args[2]); @@ -3244,15 +3208,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I2(r, r, rK); case INDEX_op_andc_i32: - case INDEX_op_orc_i32: - case INDEX_op_eqv_i32: - return C_O1_I2(r, r, ri); case INDEX_op_andc_i64: - return C_O1_I2(r, r, rKR); + case INDEX_op_orc_i32: case INDEX_op_orc_i64: + case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return C_O1_I2(r, r, rNK); - case INDEX_op_nand_i32: case INDEX_op_nand_i64: case INDEX_op_nor_i32: From patchwork Tue Mar 12 14:38:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BBECBC54E58 for ; Tue, 12 Mar 2024 14:44:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I0-0003e0-1A; Tue, 12 Mar 2024 10:39:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Ha-0003Xd-Ll for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:12 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HO-0007ks-Mr for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-29c23f53eabso1171793a91.0 for ; Tue, 12 Mar 2024 07:38:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254337; x=1710859137; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=pNp6XquX3YweCwEwuUg2y5RKbGsMH7v+obg5kp5OsQE=; b=z6NwP0klODqOYD+9cJXe4n0q4qXo7B0oMzjL0LD9tDVdh5lSOLi2LDS9kfmQzy8Zaj +t+yZ1HTGD1+6xv6+xfATR0+dAtAfOyY5RJ4IDoz+xlvpfk2B9pex90NMp0loGPF3LO9 A49l0OFjmRMIa41LHTwKbctycVr/9/KA1yxNMtP2IaaSvbSsCmUWjT+eIjNWVzu1xBX+ CCFxKq/04XSGWSbr2CgHyxXsruSBKRT12ortJYVSJKN3RI/hzaw+kHji3bEmqSpm6FZI 3KFbl1JnlNzk9sHMRr+RvqjqWe0MlnAVZ5bmcOsv2VgU+7lLRvvRO56GC8v4i6DtnMKO SsRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254337; x=1710859137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pNp6XquX3YweCwEwuUg2y5RKbGsMH7v+obg5kp5OsQE=; b=jFmF3FNX/cmv6FtETW2+n4WU3zWBaCFm9Eu9kAzbKoRLq1EfOt/jEgydg03yhzB6HP cDMRR8HyqBSBtpSkopZg5M3xVb8kWdxTcuHvXq9hkGAZlakzeqZBPTU6OdB44q6DyqaH /6Cir+x7esqRLOw5pPxNYlL806hmsVsy0F3sL1zBKOU2KPha198ppiQCYWpa85ZJCAox 2wUe0BcHpu2s2QgYXoiVYvwg9c2rxyxCZVPjyVEGv0hGMw73lBoGmCU41EP+UpqGm22C Pg4AUalVAhg2/rEUncChKJLHb61hhosUrazdtLFqeTyRTVN+V0nDZNLGVYRcuV91vJ0+ aTVg== X-Gm-Message-State: AOJu0Yx7oFE49lj1SvRo/CNV5j/aiGKzDo8+FSlPjwiYR3/qBeT++qhU Qac40zZY9MXK9ILWbotEmFhLNRCiQFLg0SCDhUGMUUgbMFhrzWFUWUdCwN3muuPcVrM9fuZyrTi J X-Google-Smtp-Source: AGHT+IEAq0AVx4e/IzTTjVNTzageDZJzIRszOVVR2UGvJFyRM2vc/4g8awAzTemkZCV4iO63b65oxA== X-Received: by 2002:a17:90b:8cc:b0:29b:2268:3349 with SMTP id ds12-20020a17090b08cc00b0029b22683349mr7779350pjb.18.1710254337386; Tue, 12 Mar 2024 07:38:57 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/15] tcg/riscv: Do not accept immediate operand for andc, orc, eqv Date: Tue, 12 Mar 2024 04:38:34 -1000 Message-Id: <20240312143839.136408-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations with inverted immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 36 +++++++--------------------------- 3 files changed, 7 insertions(+), 31 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index aac5ceee2b..0f72281a08 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -15,7 +15,6 @@ C_O0_I2(rZ, rZ) C_O1_I1(r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, r, rJ) C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index d5c419dff1..6f1cfb976c 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -15,7 +15,6 @@ REGS('r', ALL_GENERAL_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S12) -CONST('J', TCG_CT_CONST_J12) CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 639363039b..2b889486e4 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -138,7 +138,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_S12 0x200 #define TCG_CT_CONST_N12 0x400 #define TCG_CT_CONST_M12 0x800 -#define TCG_CT_CONST_J12 0x1000 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) @@ -176,13 +175,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { return 1; } - /* - * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff]. - * Used to map ANDN back to ANDI, etc. - */ - if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { - return 1; - } return 0; } @@ -1610,27 +1602,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_i32: case INDEX_op_andc_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); break; case INDEX_op_orc_i32: case INDEX_op_orc_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); break; case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_XORI, a0, a1, ~a2); - } else { - tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); break; case INDEX_op_not_i32: @@ -1963,18 +1943,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rI); + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return C_O1_I2(r, rZ, rN); + case INDEX_op_andc_i32: case INDEX_op_andc_i64: case INDEX_op_orc_i32: case INDEX_op_orc_i64: case INDEX_op_eqv_i32: case INDEX_op_eqv_i64: - return C_O1_I2(r, r, rJ); - - case INDEX_op_sub_i32: - case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); - case INDEX_op_mul_i32: case INDEX_op_mulsh_i32: case INDEX_op_muluh_i32: From patchwork Tue Mar 12 14:38:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 576F3C54E5D for ; Tue, 12 Mar 2024 14:42:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hz-0003dJ-Ic; Tue, 12 Mar 2024 10:39:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Ha-0003Xc-Lq for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:12 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HQ-0007kw-ON for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:09 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-29bf998872fso1478053a91.3 for ; Tue, 12 Mar 2024 07:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254339; x=1710859139; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=cbxM+ZYIVDOiIr29L7EmXNz1akvOYPBrfp8Zc64o4J8=; b=dO15TNi4nnD1mBGQ4DFuKHxFjX/FqPlp/UoKZxNvviGoiOrpZJonfHQZA+05HVMei1 9V8SL0NczT2A52mvslN7xuUplbjVLUyYa38o221nk/GqEtfjHm8ZeVWEJBJKBP6W0eHx KHoyLr+fWP8sitC5ICeaCdm2XAee5L/r0Kzf1aMAdJQacLmG9TESprPt2+W/Lo+bgfav uQxpZ1re8sXmQ5Gvfz2sDIL8P4x7QnUYPn7Wq+vJS/F1VsZCsdDqa2LOsW0D8vbn4UMA wtGYNG63Ji2o2ZES0kgG7KaF/Ud/uEj9LBKbMo1eScalWGijtCeZSIPhzQoS3UREZFbq iK5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254339; x=1710859139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cbxM+ZYIVDOiIr29L7EmXNz1akvOYPBrfp8Zc64o4J8=; b=UEgJCd4Wq1dPQcjlvH0W18Mnt9wmeOi3kvPw2qK86eZ/hG0Ky6nhFr6AnVnopcx6UR 9N0FC55WmrP/s8KWam8ZfN+Q4/sV7Z6jIaqc5J5AXJa/diubmVHwHgtwe/paMPLE74P7 qTDeTRPzBXpZAdlr1mwbBYaWGVO15YrPlbqJJwnoHDBowl64Dh3fAXCZGVi2pKcML6rX sHsYZeg1ABpOxyTQe6YHuyZpTJkDzkWiQIOMCjJWW9AlO14VLnZAY1jfeasdosAR4ieK zn18Zuu7DxuGEkbrE/K3BCTq5LLkcaZ2bDJDTe3EgSIJRx/3D9Ov9ED9c8k10J8AupUa +XQA== X-Gm-Message-State: AOJu0Ywc/FMKZOCrhBPnySSWIdGgRYxdPl2u3LFFAVnzPz9wTOIiIU7n hZSwK95PBd+KXY+P8MRA3gr8+AmFt5ZZIIBegD3DBA4fyKfiQayOYW6R7XlOYhxuIqNem/t2KOC u X-Google-Smtp-Source: AGHT+IFZHOzx9j2OBhipPnHXuNJY6DfPc/XZuUthJn3NEM2vKuIutqtavLjHKUcs1nQKYDpbNt3eJg== X-Received: by 2002:a17:90a:c406:b0:29b:b3fa:b7ac with SMTP id i6-20020a17090ac40600b0029bb3fab7acmr6922906pjt.10.1710254338788; Tue, 12 Mar 2024 07:38:58 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/15] tcg/riscv: Do not accept immediate operands for sub Date: Tue, 12 Mar 2024 04:38:35 -1000 Message-Id: <20240312143839.136408-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The transformations to neg and add immediate are now done generically and need not be handled by the backend. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 +- tcg/riscv/tcg-target-con-str.h | 1 - tcg/riscv/tcg-target.c.inc | 24 ++++-------------------- 3 files changed, 5 insertions(+), 22 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 0f72281a08..13a383aeb1 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -13,9 +13,9 @@ C_O0_I1(r) C_O0_I2(rZ, r) C_O0_I2(rZ, rZ) C_O1_I1(r, r) +C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, rZ, rN) C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h index 6f1cfb976c..a8d57c0e37 100644 --- a/tcg/riscv/tcg-target-con-str.h +++ b/tcg/riscv/tcg-target-con-str.h @@ -15,6 +15,5 @@ REGS('r', ALL_GENERAL_REGS) * CONST(letter, TCG_CT_CONST_* bit set) */ CONST('I', TCG_CT_CONST_S12) -CONST('N', TCG_CT_CONST_N12) CONST('M', TCG_CT_CONST_M12) CONST('Z', TCG_CT_CONST_ZERO) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2b889486e4..6b28f2f85d 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -136,8 +136,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 -#define TCG_CT_CONST_N12 0x400 -#define TCG_CT_CONST_M12 0x800 +#define TCG_CT_CONST_M12 0x400 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) @@ -160,13 +159,6 @@ static bool tcg_target_const_match(int64_t val, int ct, if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { return 1; } - /* - * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. - * Used for subtraction, where a constant must be handled by ADDI. - */ - if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { - return 1; - } /* * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. * Used by addsub2 and movcond, which may need the negative value, @@ -1559,18 +1551,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_sub_i32: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); break; case INDEX_op_sub_i64: - if (c2) { - tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); - } else { - tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); - } + tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); break; case INDEX_op_and_i32: @@ -1945,7 +1929,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return C_O1_I2(r, rZ, rN); + return C_O1_I2(r, r, r); case INDEX_op_andc_i32: case INDEX_op_andc_i64: From patchwork Tue Mar 12 14:38:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0D76C54E58 for ; Tue, 12 Mar 2024 14:44:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I1-0003ea-3u; Tue, 12 Mar 2024 10:39:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3He-0003YL-G4 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:15 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HS-0007ky-5P for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:14 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6e6afd8da93so313825b3a.3 for ; Tue, 12 Mar 2024 07:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254340; x=1710859140; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=mWv/lYl0jTYk+QCDeO6yVFPWdK9NhQ8DhGo71nIOR9Q=; b=SKXP0RjEW3X6J8L8iBO9cvi0aAzb8sf7CTwQGud6W/cALW30dLTaFV/g3Rf4+CoBu7 Ij6h3ARH21SOvxVBbWZEWDa6WAFgrFC2bDWomysK8OSXTw6mqqGFjYrkI0gkM2MyryEs QgS0bMKmcrYhmHI/PymbqBAHCaWi7BB78hmPoUeOpJQJkBgyvxXMIuVqbM5NEvCieYZj YwG/cgY9GG27K3KK2/FNYqzzrbo3BE/ToChP0mUCuC1U90RXpKq8DCEjjTubn4+pfRVN hO/FKAAkcMoTwn3HhzOSJ0V1xl0yyabTtj59P0fS3Pxz1Np6/HbgZeJ0CO3NAsAOufHR KD4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254340; x=1710859140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mWv/lYl0jTYk+QCDeO6yVFPWdK9NhQ8DhGo71nIOR9Q=; b=pz4uba6dG/CVntpaOKIlcrRCbiz4rQ4HDOVh6Ayl87cx7fIACFFfoXrI11awcon+Z9 6nD0DHgC7lSMp8oSr2l8wq+y5IwSAn22Vr4jPCd9nZeuOwqW/JuJDh5C1upWqWg0n4OP YvLiveLvsLXXB7bnvjMyfZ4eqwAnKjibIlfZ/mdBh+MLxT0coBpw4f7R25wnNhKdJhxb TldErNs9Ahfy1ehwb6lo37rGowBlhjiwdjfd5eFEz89+0qSjsLpP4iq+H0BKi+Q9Lp73 gmv0LHUpMxq09K4NvACP2s7/cBtr/2S9zN4NXvf57q8LBF5mDOnp22GxB1UzrutKNRAw H1BQ== X-Gm-Message-State: AOJu0YyjwS4d+icwtKZsYZDFdBMrafW82nSs0S4DQlq2GxxgP1sE0nd7 PDGoC7TWvtzLitZmqKgCHapAyYskd5S2neRe2F8+16LU3hMpYocGmNGiKyaDEwYtUmqHCo8P24s v X-Google-Smtp-Source: AGHT+IG5Kh/wMHgAgjwIxFniYarzVPsqIYLlp94Zuou/gew7RNdw9xj+8oDcnjcqXIvz4CAZFZVapA== X-Received: by 2002:a05:6a20:840f:b0:1a1:4757:927e with SMTP id c15-20020a056a20840f00b001a14757927emr8384179pzd.33.1710254339917; Tue, 12 Mar 2024 07:38:59 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.38.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:38:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/15] tcg/riscv: Do not accept zero operands for logicals, multiply or divide Date: Tue, 12 Mar 2024 04:38:36 -1000 Message-Id: <20240312143839.136408-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Trust that the optimizer has folded all of these away. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 1 - tcg/riscv/tcg-target.c.inc | 4 +--- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h index 13a383aeb1..527d2fd4d9 100644 --- a/tcg/riscv/tcg-target-con-set.h +++ b/tcg/riscv/tcg-target-con-set.h @@ -16,7 +16,6 @@ C_O1_I1(r, r) C_O1_I2(r, r, r) C_O1_I2(r, r, ri) C_O1_I2(r, r, rI) -C_O1_I2(r, rZ, rZ) C_N1_I2(r, r, rM) C_O1_I4(r, r, rI, rM, rM) C_O2_I4(r, r, rZ, rZ, rM, rM) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6b28f2f85d..0dc1b2d8f7 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1929,8 +1929,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i32: case INDEX_op_sub_i64: - return C_O1_I2(r, r, r); - case INDEX_op_andc_i32: case INDEX_op_andc_i64: case INDEX_op_orc_i32: @@ -1951,7 +1949,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_divu_i64: case INDEX_op_rem_i64: case INDEX_op_remu_i64: - return C_O1_I2(r, rZ, rZ); + return C_O1_I2(r, r, r); case INDEX_op_shl_i32: case INDEX_op_shr_i32: From patchwork Tue Mar 12 14:38:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EFB1C54E58 for ; Tue, 12 Mar 2024 14:42:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I5-0003ez-EI; Tue, 12 Mar 2024 10:39:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3He-0003YM-GD for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:15 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HS-0007l6-O6 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:14 -0400 Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-29c4fe68666so244025a91.0 for ; Tue, 12 Mar 2024 07:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254341; x=1710859141; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5KtrDk5IPnNDG0tAWNMkEiXDVZJDwN45mTz+TeCGBQA=; b=GdMEGvaUAI3jnHq49kTWvoiiWe5LDGy3ml45e5dJnDNmXF0Ic5r1iYsV5DS/zTQ4pf udfN449lfTbk0DqaRDH4nfuJD0i6aYt/O8GuzT5yVN6BpzHqLaUaNQHtpaa9QLQfozUC EQsv45T3XLNPPxJEhHtAzgjrHrkkv6kQaF5+dQwAIZcPJxdu85PPvEmRvgPMlcbem7A0 Vb4WsiD0IYE+j2Wd2LAyxOcs/vwdKE2hrIm/ZsXVNI/ekmAGaVs8m0xF4OkiGFnFiQOh /qAjt2ZdCJvyxsnxOI4p/6RERR/fr3anpE7SBI+15cD+G8vfVYM0Om642f047t75TfuY 4Csw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254341; x=1710859141; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5KtrDk5IPnNDG0tAWNMkEiXDVZJDwN45mTz+TeCGBQA=; b=iCOhjnEDB32ORabnIfSOR8xWVCbIT2R4Hmio6HTib0gSoruQ6q2VpSFP0G/jznt1tC vWJxoYmbWcL42F1aAQvdBVX42ItHMo/0dc4KusE2QVLekkfAcYLb7u1ZekSP0Ulhj+pt TJZwXxOCi+W8fT2AsTLzF5FnTRWEDVmjpom+eVzoSHyExO9F1ephyvCY+3g6VOW49Asf pOUVe6E/3K11mi3IcldfSZDGOfEH686hAHaQ+dGGgNKMA8bKE6eHUbuhDYDm2Y72ee1V JURUKFLFYAfWHAiI6uBqeOJSkWVhiXJU1YJwpiDj4/nA1uyuQzwaDSB1AE9YCgUpGRKM qiwQ== X-Gm-Message-State: AOJu0YwAHb6BiHzvWgArMXe56QT1AM4CDzjYjxvJq0h/a7PQ+X3vtJRU 6Ff5HRL/3BGZlRlCbvCUUdbbsOZjfiNPFhkQpGz1xXIQYQ8tKpaQn4cXMh4nvAveMvIrj9PX5Ge B X-Google-Smtp-Source: AGHT+IGu6IfMQkCydRLVGkB/KcOR1hZjtaBiz8+25roD1Zv6WvvtF9fxvyv+DBxAFUBZYfPFGFuUFw== X-Received: by 2002:a17:90a:f011:b0:29a:8ac0:9fd2 with SMTP id bt17-20020a17090af01100b0029a8ac09fd2mr510545pjb.49.1710254341049; Tue, 12 Mar 2024 07:39:01 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/15] tcg/optimize: Fold and to extu during optimize Date: Tue, 12 Mar 2024 04:38:37 -1000 Message-Id: <20240312143839.136408-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 43 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index c6b0ab35c8..39bcd32f72 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1300,11 +1300,46 @@ static bool fold_and(OptContext *ctx, TCGOp *op) ctx->s_mask = arg_info(op->args[1])->s_mask & arg_info(op->args[2])->s_mask; - /* - * Known-zeros does not imply known-ones. Therefore unless - * arg2 is constant, we can't infer affected bits from it. - */ if (arg_is_const(op->args[2])) { + TCGOpcode ext8 = 0, ext16 = 0, ext32 = 0; + + /* Canonicalize as zero-extend, if supported. */ + switch (ctx->type) { + case TCG_TYPE_I32: + ext8 = TCG_TARGET_HAS_ext8u_i32 ? INDEX_op_ext8u_i32 : 0; + ext16 = TCG_TARGET_HAS_ext16u_i32 ? INDEX_op_ext16u_i32 : 0; + break; + case TCG_TYPE_I64: + ext8 = TCG_TARGET_HAS_ext8u_i64 ? INDEX_op_ext8u_i64 : 0; + ext16 = TCG_TARGET_HAS_ext16u_i64 ? INDEX_op_ext16u_i64 : 0; + ext32 = TCG_TARGET_HAS_ext32u_i64 ? INDEX_op_ext32u_i64 : 0; + break; + default: + break; + } + + switch (arg_info(op->args[2])->val) { + case 0xff: + if (ext8) { + op->opc = ext8; + } + break; + case 0xffff: + if (ext16) { + op->opc = ext16; + } + break; + case UINT32_MAX: + if (ext32) { + op->opc = ext32; + } + break; + } + + /* + * Known-zeros does not imply known-ones. Therefore unless + * arg2 is constant, we can't infer affected bits from it. + */ ctx->a_mask = z1 & ~z2; } From patchwork Tue Mar 12 14:38:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 128C1C54E58 for ; Tue, 12 Mar 2024 14:44:33 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3I5-0003ey-EY; Tue, 12 Mar 2024 10:39:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Hh-0003Yi-GD for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:19 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HW-0007lH-Ip for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:14 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-29bf9bd1907so1663736a91.1 for ; Tue, 12 Mar 2024 07:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254342; x=1710859142; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4kGtxvZdOI4O7h397wt7Rdsn7HhdcYY3ZpxBI2vFnmQ=; b=ddrgLnUhYTpUf8096/8VR6xp9aWJcJ013OVE6LR5U6S6ZMpF6flZHIht5LlZnvh03h timKwhZ7cnQ6X13TNUpmQgOrHLslSwjvWExUnaZcl7NgOJeB1RqcL25QnVXNkCnnwdib cw/fokdx6uyB6zFfEvyMRjB5351x8QYGIhlTh9j1EeZXm24rAS57HQafMfF3iabjEoBx uNTPxJuCmivMQgcGrGcjh9ObVhXK+vf0wAjgfxAV+001VYN0bS2iTwQsCQgjnIIGG1vM Rwn6vjdglsorayZGQ0U47SEgGsTQ2TpV02+886EoFG3RxFA0w4cSbBAZhntpuhmS2JQy 41Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254342; x=1710859142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4kGtxvZdOI4O7h397wt7Rdsn7HhdcYY3ZpxBI2vFnmQ=; b=D8thayn55LrLWGmldcC5JY5+YVm658s5E1rlPH1EsyU1zhjEnbl8JEGEDhb2UDJfQH TbQ2P2hR8K6RknRmzBO0NKmfyz0iyFDCaBzUSZgiqOeR4UIqCwetvE/qx21KMkNHGEI0 Mr4TsiCkwoPLM/175tn/9kZ8La4huR7X4OLfd4a47KPUXB7tviM0zSx+widNkBhMOpao ejO+PRVVTH/50KOJ+UxiMCXUfs409PnuJ5dYVqr7uF9mJ+sdOlHYVVi0u3DXaM9k1+Qi FdmKT+sYC3zOnBBPhoonxjNZRlQ1LCnAOQ7FkMiwiTeg5La6QIGrj95ucZ7uiKsUb9Qb xZkg== X-Gm-Message-State: AOJu0YyZ4HeD/MONucvdms1zMqZKuhPUheWMpc3XNwYLJCgR0lYcOjAV VTm0P7ru0rU1DWv7/ZK/iVbUB9HGpkDHM2VZZdR77NWvnaILzkeDZvm5UtXzmX09JqN8NLSaxGA 0 X-Google-Smtp-Source: AGHT+IHlOS2xj0anKavqKlad4CNIkDBOcuEN+KGtRwjo5Ro7M+z1bC+QgOjkAEJccs0T/S2StX4HVg== X-Received: by 2002:a17:90b:48d2:b0:299:3ebf:d180 with SMTP id li18-20020a17090b48d200b002993ebfd180mr634093pjb.6.1710254342569; Tue, 12 Mar 2024 07:39:02 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/15] tcg: Use arg_is_const_val in fold_sub_to_neg Date: Tue, 12 Mar 2024 04:38:38 -1000 Message-Id: <20240312143839.136408-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/optimize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 39bcd32f72..f3867ce9e6 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -2451,7 +2451,7 @@ static bool fold_sub_to_neg(OptContext *ctx, TCGOp *op) TCGOpcode neg_op; bool have_neg; - if (!arg_is_const(op->args[1]) || arg_info(op->args[1])->val != 0) { + if (!arg_is_const_val(op->args[1], 0)) { return false; } From patchwork Tue Mar 12 14:38:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 13590109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EAB2CC54E5D for ; Tue, 12 Mar 2024 14:42:25 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rk3Hn-0003Zk-HG; Tue, 12 Mar 2024 10:39:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rk3Hi-0003Yp-92 for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:19 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rk3HZ-0007lc-8j for qemu-devel@nongnu.org; Tue, 12 Mar 2024 10:39:16 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1ddc7e45c47so1132175ad.1 for ; Tue, 12 Mar 2024 07:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710254345; x=1710859145; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ICGHco8N2bsqwCEhCf7Urzzd713nkLezWtvD//1fvW4=; b=Vu7pLF/IKm0mSCmPwcwTT0jROBJGjREm86dOkIWyTZntrAidZ3xagSSPOkzbX4ETTu kx9m3a7S0Sp2W35Fj1rG8Sdj6VcUoyPtveEBggVz97tCbQpuUamOmwfowz2Xe37uSaaR IpVChmo5jlbZQwJx3lSjy2+2yDaHNGYJnQWRRJ0cw+dde/ECmTqYrmlsTVORmp5JXPYl QYIKZpsDoWsPhilEWlKiRCFBIFBhgJFDSQ8cT+YEMi4A2jZ89UvZp25ROMOT9MWYfaIU 1dBYggbskmXI/4ryOezwQKjdNSUmgOs/T1az7s6ZBkKm1o+MrV2PaRDS6J5PZdNzwWFh tpmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710254345; x=1710859145; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICGHco8N2bsqwCEhCf7Urzzd713nkLezWtvD//1fvW4=; b=w+T8ppHqozCg1g83oyiIrgWuz84f0ggVEfhq6c3QHWmtHEHM4NzXWlYho+9JcSmLcj zVSOUBKsGYGVR29FH7hP/gbYWrWZBmUFPOofCO+IcSyGs5jC7fKUeuyBfwFgbteoL8yy lE97ZXd6DO4yw/h2Gk+srMEY7dPekvXG7cw1ItCwXzBTiPnUtg5NI/8PY82QuaOAehan ZxCed/RHfgx2NIykiLUyKeiL1LECzp79+k/Y4Sy5JuzI917p9Okme/r1/uDx6dreSjaf /Wwf1rMxgU++XWjF4iA0Qoe0xCYco+GbQTTrm008xGDULQEMorOe5qhQyL44htGhn3rr jskA== X-Gm-Message-State: AOJu0YzllmSBhEcYbckjSotHgU/ThruW973gAmI7CQKds30nN4SYVGLl MuX1J1Uj2KSol6W4g+tuexzd6+lus02jlpHDjYFma/CMH2+nBkN/vwhno3l8Ft516pS2ZWP9+iU s X-Google-Smtp-Source: AGHT+IHfhKKZiG4v7KFSPrkcc4bFM18xw8OrgWQndElMJgpfVFk1eoFFVNEoxJsSIr6L0o0S3owLcA== X-Received: by 2002:a17:90a:c695:b0:29b:3106:7f24 with SMTP id n21-20020a17090ac69500b0029b31067f24mr525828pjt.37.1710254344976; Tue, 12 Mar 2024 07:39:04 -0700 (PDT) Received: from stoup.. (173-197-098-125.biz.spectrum.com. [173.197.98.125]) by smtp.gmail.com with ESMTPSA id jx15-20020a17090b46cf00b0029baa0b1a6csm7492214pjb.24.2024.03.12.07.39.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Mar 2024 07:39:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 15/15] tcg/optimize: Lower unsupported deposit during optimize Date: Tue, 12 Mar 2024 04:38:39 -1000 Message-Id: <20240312143839.136408-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240312143839.136408-1-richard.henderson@linaro.org> References: <20240312143839.136408-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The expansions that we chose in tcg-op.c may be less than optimial. Delay lowering until optimize, so that we have propagated constants and have computed known zero masks. Signed-off-by: Richard Henderson --- tcg/optimize.c | 231 +++++++++++++++++++++++++++++++++++++++++----- tcg/tcg-op.c | 244 ++++++++++++------------------------------------- 2 files changed, 266 insertions(+), 209 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index f3867ce9e6..ce1dbab097 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1632,51 +1632,234 @@ static bool fold_ctpop(OptContext *ctx, TCGOp *op) static bool fold_deposit(OptContext *ctx, TCGOp *op) { - TCGOpcode and_opc; + TCGOpcode and_opc, or_opc, ex2_opc, shl_opc, rotl_opc; + TCGOp *op2; + TCGArg ret = op->args[0]; + TCGArg arg1 = op->args[1]; + TCGArg arg2 = op->args[2]; + int ofs = op->args[3]; + int len = op->args[4]; + int width; + uint64_t type_mask; + bool valid; - if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) { - uint64_t t1 = arg_info(op->args[1])->val; - uint64_t t2 = arg_info(op->args[2])->val; + if (arg_is_const(arg1) && arg_is_const(arg2)) { + uint64_t t1 = arg_info(arg1)->val; + uint64_t t2 = arg_info(arg2)->val; - t1 = deposit64(t1, op->args[3], op->args[4], t2); - return tcg_opt_gen_movi(ctx, op, op->args[0], t1); + t1 = deposit64(t1, ofs, len, t2); + return tcg_opt_gen_movi(ctx, op, ret, t1); } switch (ctx->type) { case TCG_TYPE_I32: and_opc = INDEX_op_and_i32; + or_opc = INDEX_op_or_i32; + shl_opc = INDEX_op_shl_i32; + ex2_opc = TCG_TARGET_HAS_extract2_i32 ? INDEX_op_extract2_i32 : 0; + rotl_opc = TCG_TARGET_HAS_rot_i32 ? INDEX_op_rotl_i32 : 0; + valid = (TCG_TARGET_HAS_deposit_i32 && + TCG_TARGET_deposit_i32_valid(ofs, len)); + width = 32; + type_mask = UINT32_MAX; break; case TCG_TYPE_I64: and_opc = INDEX_op_and_i64; + or_opc = INDEX_op_or_i64; + shl_opc = INDEX_op_shl_i64; + ex2_opc = TCG_TARGET_HAS_extract2_i64 ? INDEX_op_extract2_i64 : 0; + rotl_opc = TCG_TARGET_HAS_rot_i64 ? INDEX_op_rotl_i64 : 0; + valid = (TCG_TARGET_HAS_deposit_i64 && + TCG_TARGET_deposit_i64_valid(ofs, len)); + width = 64; + type_mask = UINT64_MAX; break; default: g_assert_not_reached(); } - /* Inserting a value into zero at offset 0. */ - if (arg_is_const_val(op->args[1], 0) && op->args[3] == 0) { - uint64_t mask = MAKE_64BIT_MASK(0, op->args[4]); + if (arg_is_const(arg2)) { + uint64_t val = arg_info(arg2)->val; + uint64_t mask = MAKE_64BIT_MASK(0, len); - op->opc = and_opc; - op->args[1] = op->args[2]; - op->args[2] = arg_new_constant(ctx, mask); - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; - return false; + /* Inserting all-zero into a value. */ + if ((val & mask) == 0) { + op->opc = and_opc; + op->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + return fold_and(ctx, op); + } + + /* Inserting all-one into a value. */ + if ((val & mask) == mask) { + op->opc = or_opc; + op->args[2] = arg_new_constant(ctx, mask << ofs); + goto done; + } + + /* Lower invalid deposit of constant as AND + OR. */ + if (!valid) { + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + fold_and(ctx, op2); /* fold to ext*u */ + + op->opc = or_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, (val & mask) << ofs); + goto done; + } } - /* Inserting zero into a value. */ - if (arg_is_const_val(op->args[2], 0)) { - uint64_t mask = deposit64(-1, op->args[3], op->args[4], 0); + /* Inserting a value into zero. */ + if (arg_is_const_val(arg1, 0)) { + uint64_t mask = MAKE_64BIT_MASK(0, len); + uint64_t need_mask = arg_info(arg2)->z_mask & ~mask & type_mask; - op->opc = and_opc; - op->args[2] = arg_new_constant(ctx, mask); - ctx->z_mask = mask & arg_info(op->args[1])->z_mask; - return false; + /* Always lower deposit into zero at 0 as AND. */ + if (ofs == 0) { + if (!need_mask) { + return tcg_opt_gen_mov(ctx, op, ret, arg2); + } + op->opc = and_opc; + op->args[1] = arg2; + op->args[2] = arg_new_constant(ctx, mask); + return fold_and(ctx, op); + } + + /* If no mask required, fold as SHL. */ + if (!((need_mask << ofs) & type_mask)) { + op->opc = shl_opc; + op->args[1] = arg2; + op->args[2] = arg_new_constant(ctx, ofs); + goto done; + } + + /* Lower invalid deposit into zero as AND + SHL. */ + if (!valid) { + /* + * ret = arg2 & mask + * ret = ret << ofs + */ + TCGOpcode ext_second_opc = 0; + + switch (ofs + len) { + case 8: + ext_second_opc = + (ctx->type == TCG_TYPE_I32 + ? (TCG_TARGET_HAS_ext8u_i32 ? INDEX_op_ext8u_i32 : 0) + : (TCG_TARGET_HAS_ext8u_i64 ? INDEX_op_ext8u_i64 : 0)); + break; + case 16: + ext_second_opc = + (ctx->type == TCG_TYPE_I32 + ? (TCG_TARGET_HAS_ext16u_i32 ? INDEX_op_ext16u_i32 : 0) + : (TCG_TARGET_HAS_ext16u_i64 ? INDEX_op_ext16u_i64 : 0)); + break; + case 32: + ext_second_opc = + TCG_TARGET_HAS_ext32u_i64 ? INDEX_op_ext32u_i64 : 0; + break; + } + + if (ext_second_opc) { + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, ofs); + + op->opc = ext_second_opc; + op->args[1] = ret; + } else { + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, mask); + fold_and(ctx, op2); + + op->opc = shl_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, ofs); + } + goto done; + } } - ctx->z_mask = deposit64(arg_info(op->args[1])->z_mask, - op->args[3], op->args[4], - arg_info(op->args[2])->z_mask); + /* After special cases, lower invalid deposit. */ + if (!valid) { + uint64_t mask = MAKE_64BIT_MASK(0, len); + TCGArg tmp; + + /* + * ret = arg2:arg1 >> len + * ret = rotl(ret, len) + */ + if (ex2_opc && rotl_opc && ofs == 0) { + op2 = tcg_op_insert_before(ctx->tcg, op, ex2_opc, 4); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg2; + op2->args[3] = len; + + op->opc = rotl_opc; + op->args[1] = ret; + op->args[2] = arg_new_constant(ctx, len); + goto done; + } + + /* + * tmp = arg1 << len + * ret = arg2:tmp >> len + */ + if (ex2_opc && ofs + len == width) { + tmp = ret == arg2 ? arg_new_temp(ctx) : ret; + + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 4); + op2->args[0] = tmp; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, len); + + op->opc = ex2_opc; + op->args[0] = ret; + op->args[1] = tmp; + op->args[2] = arg2; + op->args[3] = len; + goto done; + } + + /* + * tmp = arg2 & mask + * ret = arg1 & ~(mask << ofs) + * tmp = tmp << ofs + * ret = ret | tmp + */ + tmp = arg_new_temp(ctx); + + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = tmp; + op2->args[1] = arg2; + op2->args[2] = arg_new_constant(ctx, mask); + fold_and(ctx, op2); + + op2 = tcg_op_insert_before(ctx->tcg, op, shl_opc, 3); + op2->args[0] = tmp; + op2->args[1] = tmp; + op2->args[2] = arg_new_constant(ctx, ofs); + + op2 = tcg_op_insert_before(ctx->tcg, op, and_opc, 3); + op2->args[0] = ret; + op2->args[1] = arg1; + op2->args[2] = arg_new_constant(ctx, ~(mask << ofs)); + fold_and(ctx, op2); + + op->opc = or_opc; + op->args[1] = ret; + op->args[2] = tmp; + } + + done: + ctx->z_mask = deposit64(arg_info(arg1)->z_mask, ofs, len, + arg_info(arg2)->z_mask); return false; } diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index aa6bc6f57d..76a1f5e296 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -874,9 +874,6 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { - uint32_t mask; - TCGv_i32 t1; - tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 32); @@ -886,37 +883,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, tcg_gen_mov_i32(ret, arg2); return; } - if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { - tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); - return; - } - - t1 = tcg_temp_ebb_new_i32(); - - if (TCG_TARGET_HAS_extract2_i32) { - if (ofs + len == 32) { - tcg_gen_shli_i32(t1, arg1, len); - tcg_gen_extract2_i32(ret, t1, arg2, len); - goto done; - } - if (ofs == 0) { - tcg_gen_extract2_i32(ret, arg1, arg2, len); - tcg_gen_rotli_i32(ret, ret, len); - goto done; - } - } - - mask = (1u << len) - 1; - if (ofs + len < 32) { - tcg_gen_andi_i32(t1, arg2, mask); - tcg_gen_shli_i32(t1, t1, ofs); - } else { - tcg_gen_shli_i32(t1, arg2, ofs); - } - tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i32(ret, ret, t1); - done: - tcg_temp_free_i32(t1); + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); } void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -931,48 +898,9 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_gen_shli_i32(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { + } else { TCGv_i32 zero = tcg_constant_i32(0); tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - } else { - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); } } @@ -2611,9 +2539,6 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { - uint64_t mask; - TCGv_i64 t1; - tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); tcg_debug_assert(len <= 64); @@ -2623,52 +2548,41 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, tcg_gen_mov_i64(ret, arg2); return; } - if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { + + if (TCG_TARGET_REG_BITS == 64) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); - return; - } - - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), - TCGV_LOW(arg2), ofs - 32, len); - tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), - TCGV_LOW(arg2), ofs, len); - tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); - return; - } - } - - t1 = tcg_temp_ebb_new_i64(); - - if (TCG_TARGET_HAS_extract2_i64) { - if (ofs + len == 64) { - tcg_gen_shli_i64(t1, arg1, len); - tcg_gen_extract2_i64(ret, t1, arg2, len); - goto done; - } - if (ofs == 0) { - tcg_gen_extract2_i64(ret, arg1, arg2, len); - tcg_gen_rotli_i64(ret, ret, len); - goto done; - } - } - - mask = (1ull << len) - 1; - if (ofs + len < 64) { - tcg_gen_andi_i64(t1, arg2, mask); - tcg_gen_shli_i64(t1, t1, ofs); + } else if (ofs >= 32) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_LOW(arg2), ofs - 32, len); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1)); + } else if (ofs + len <= 32) { + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_LOW(arg2), ofs, len); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1)); + } else if (ofs == 0) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_HIGH(arg2), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg2)); } else { - tcg_gen_shli_i64(t1, arg2, ofs); + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len = 32 - ofs; + unsigned hi_len = len - lo_len; + TCGv_i32 tl = tcg_temp_ebb_new_i32(); + TCGv_i32 th = tcg_temp_ebb_new_i32(); + + tcg_gen_deposit_i32(tl, TCGV_LOW(arg1), TCGV_LOW(arg2), ofs, lo_len); + if (len <= 32) { + tcg_gen_shri_i32(th, TCGV_LOW(arg2), lo_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg2), TCGV_HIGH(arg2), lo_len); + } + tcg_gen_deposit_i32(th, TCGV_HIGH(arg1), th, 0, hi_len); + + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_gen_mov_i32(TCGV_HIGH(ret), th); + tcg_temp_free_i32(tl); + tcg_temp_free_i32(th); } - tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i64(ret, ret, t1); - done: - tcg_temp_free_i64(t1); } void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, @@ -2683,75 +2597,35 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_gen_shli_i64(ret, arg, ofs); } else if (ofs == 0) { tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { + } else if (TCG_TARGET_REG_BITS == 64) { TCGv_i64 zero = tcg_constant_i64(0); tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); + } else if (ofs >= 32) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), ofs - 32, len); + tcg_gen_movi_i32(TCGV_LOW(ret), 0); + } else if (ofs + len <= 32) { + tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); + tcg_gen_movi_i32(TCGV_HIGH(ret), 0); + } else if (ofs == 0) { + tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_HIGH(arg), 0, len - 32); + tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg)); } else { - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } + /* The 64-bit deposit is split across the 32-bit halves. */ + unsigned lo_len = 32 - ofs; + unsigned hi_len = len - lo_len; + TCGv_i32 tl = tcg_temp_ebb_new_i32(); + TCGv_i32 th = TCGV_HIGH(ret); + + tcg_gen_deposit_z_i32(tl, TCGV_LOW(arg), ofs, lo_len); + if (len <= 32) { + tcg_gen_shri_i32(th, TCGV_LOW(arg), lo_len); + } else { + tcg_gen_extract2_i32(th, TCGV_LOW(arg), TCGV_HIGH(arg), lo_len); } - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); + tcg_gen_deposit_z_i32(th, th, 0, hi_len); + + tcg_gen_mov_i32(TCGV_LOW(ret), tl); + tcg_temp_free_i32(tl); } }