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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by CH1PEPF0000AD76.mail.protection.outlook.com (10.167.244.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Wed, 13 Mar 2024 00:55:04 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 12 Mar 2024 19:55:04 -0500 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 12 Mar 2024 19:55:02 -0500 From: Anatoliy Klymenko Date: Tue, 12 Mar 2024 17:54:58 -0700 Subject: [PATCH v2 1/8] drm: xlnx: zynqmp_dpsub: Set layer mode during creation Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240312-dp-live-fmt-v2-1-a9c35dc5c50d@amd.com> References: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> In-Reply-To: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Michal Simek , "Andrzej Hajda" , Neil Armstrong , Robert Foss , Jonas Karlman , "Jernej Skrabec" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab CC: , , , , , Anatoliy Klymenko X-Mailer: b4 0.13.0 Received-SPF: None (SATLEXMB03.amd.com: anatoliy.klymenko@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD76:EE_|MW4PR12MB5603:EE_ X-MS-Office365-Filtering-Correlation-Id: 4041570d-faa5-4ef6-5827-08dc42f83892 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 00:55:04.7580 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4041570d-faa5-4ef6-5827-08dc42f83892 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD76.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5603 Set layer mode of operation (live or dma-based) during layer creation. Each DPSUB layer mode of operation is defined by corresponding DT node port connection, so it is possible to assign it during layer object creation. Previously it was set in layer enable functions, although it is too late as setting layer format depends on layer mode, and should be done before given layer enabled. Signed-off-by: Anatoliy Klymenko Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 20 ++++++++++++++++---- drivers/gpu/drm/xlnx/zynqmp_disp.h | 13 +------------ drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- 4 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index 8a39b3accce5..e6d26ef60e89 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -64,6 +64,16 @@ #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 +/** + * enum zynqmp_dpsub_layer_mode - Layer mode + * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode + * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode + */ +enum zynqmp_dpsub_layer_mode { + ZYNQMP_DPSUB_LAYER_NONLIVE, + ZYNQMP_DPSUB_LAYER_LIVE, +}; + /** * struct zynqmp_disp_format - Display subsystem format information * @drm_fmt: DRM format (4CC) @@ -902,15 +912,12 @@ u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, /** * zynqmp_disp_layer_enable - Enable a layer * @layer: The layer - * @mode: Operating mode of layer * * Enable the @layer in the audio/video buffer manager and the blender. DMA * channels are started separately by zynqmp_disp_layer_update(). */ -void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, - enum zynqmp_dpsub_layer_mode mode) +void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) { - layer->mode = mode; zynqmp_disp_avbuf_enable_video(layer->disp, layer); zynqmp_disp_blend_layer_enable(layer->disp, layer); } @@ -1134,6 +1141,11 @@ static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) layer->id = i; layer->disp = disp; layer->info = &layer_info[i]; + /* For now assume dpsub works in either live or non-live mode for both layers. + * Hybrid mode is not supported yet. + */ + layer->mode = disp->dpsub->dma_enabled ? ZYNQMP_DPSUB_LAYER_NONLIVE + : ZYNQMP_DPSUB_LAYER_LIVE; ret = zynqmp_disp_layer_request_dma(disp, layer); if (ret) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.h b/drivers/gpu/drm/xlnx/zynqmp_disp.h index 123cffac08be..9b8b202224d9 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.h @@ -42,16 +42,6 @@ enum zynqmp_dpsub_layer_id { ZYNQMP_DPSUB_LAYER_GFX, }; -/** - * enum zynqmp_dpsub_layer_mode - Layer mode - * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode - * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode - */ -enum zynqmp_dpsub_layer_mode { - ZYNQMP_DPSUB_LAYER_NONLIVE, - ZYNQMP_DPSUB_LAYER_LIVE, -}; - void zynqmp_disp_enable(struct zynqmp_disp *disp); void zynqmp_disp_disable(struct zynqmp_disp *disp); int zynqmp_disp_setup_clock(struct zynqmp_disp *disp, @@ -62,8 +52,7 @@ void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, unsigned int *num_formats); -void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer, - enum zynqmp_dpsub_layer_mode mode); +void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, const struct drm_format_info *info); diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 1846c4971fd8..04b6bcac3b07 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1295,7 +1295,7 @@ static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, /* TODO: Make the format configurable. */ info = drm_format_info(DRM_FORMAT_YUV422); zynqmp_disp_layer_set_format(layer, info); - zynqmp_disp_layer_enable(layer, ZYNQMP_DPSUB_LAYER_LIVE); + zynqmp_disp_layer_enable(layer); if (layer_id == ZYNQMP_DPSUB_LAYER_GFX) zynqmp_disp_blend_set_global_alpha(dp->dpsub->disp, true, 255); diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index db3bb4afbfc4..43bf416b33d5 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -122,7 +122,7 @@ static void zynqmp_dpsub_plane_atomic_update(struct drm_plane *plane, /* Enable or re-enable the plane if the format has changed. */ if (format_changed) - zynqmp_disp_layer_enable(layer, ZYNQMP_DPSUB_LAYER_NONLIVE); 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Tue, 12 Mar 2024 19:55:04 -0500 From: Anatoliy Klymenko Date: Tue, 12 Mar 2024 17:54:59 -0700 Subject: [PATCH v2 2/8] drm: xlnx: zynqmp_dpsub: Update live format defines Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240312-dp-live-fmt-v2-2-a9c35dc5c50d@amd.com> References: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> In-Reply-To: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Michal Simek , "Andrzej Hajda" , Neil Armstrong , Robert Foss , Jonas Karlman , "Jernej Skrabec" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab CC: , , , , , Anatoliy Klymenko X-Mailer: b4 0.13.0 Received-SPF: None (SATLEXMB03.amd.com: anatoliy.klymenko@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|DS7PR12MB8203:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b9ba767-5dec-4700-7bf9-08dc42f83ba8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Anatoliy Klymenko Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/xlnx/zynqmp_disp_regs.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h index f92a006d5070..fa3935384834 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp_regs.h @@ -165,10 +165,10 @@ #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3 #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0) -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x0 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x1 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x2 -#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x3 +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB (0x0 << 4) +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 (0x1 << 4) +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 (0x2 << 4) +#define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY (0x3 << 4) #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4) #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8) #define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400 From patchwork Wed Mar 13 00:55:00 2024 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 00:55:10.9675 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1570f1f-fd00-46db-d68b-08dc42f83c45 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8919 DPSUB in bridge mode supports multiple input media bus formats. Announce the list of supported input media bus formats via drm_bridge.atomic_get_input_bus_fmts callback. Introduce a set of live input formats, supported by DPSUB. Rename zynqmp_disp_layer_drm_formats() to zynqmp_disp_layer_formats() to reflect semantics for both live and non-live layer format lists. Signed-off-by: Anatoliy Klymenko Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 67 +++++++++++++++++++++++++++++++++----- drivers/gpu/drm/xlnx/zynqmp_disp.h | 4 +-- drivers/gpu/drm/xlnx/zynqmp_dp.c | 26 +++++++++++++++ drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- 4 files changed, 88 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index e6d26ef60e89..af851190f447 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -77,12 +78,16 @@ enum zynqmp_dpsub_layer_mode { /** * struct zynqmp_disp_format - Display subsystem format information * @drm_fmt: DRM format (4CC) + * @bus_fmt: Media bus format * @buf_fmt: AV buffer format * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats * @sf: Scaling factors for color components */ struct zynqmp_disp_format { - u32 drm_fmt; + union { + u32 drm_fmt; + u32 bus_fmt; + }; u32 buf_fmt; bool swap; const u32 *sf; @@ -182,6 +187,12 @@ static const u32 scaling_factors_565[] = { ZYNQMP_DISP_AV_BUF_5BIT_SF, }; +static const u32 scaling_factors_666[] = { + ZYNQMP_DISP_AV_BUF_6BIT_SF, + ZYNQMP_DISP_AV_BUF_6BIT_SF, + ZYNQMP_DISP_AV_BUF_6BIT_SF, +}; + static const u32 scaling_factors_888[] = { ZYNQMP_DISP_AV_BUF_8BIT_SF, ZYNQMP_DISP_AV_BUF_8BIT_SF, @@ -364,6 +375,36 @@ static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { }, }; +/* List of live video layer formats */ +static const struct zynqmp_disp_format avbuf_live_fmts[] = { + { + .bus_fmt = MEDIA_BUS_FMT_RGB666_1X18, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, + .sf = scaling_factors_666, + }, { + .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X24, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, + .sf = scaling_factors_888, + }, { + .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422, + .sf = scaling_factors_888, + }, { + .bus_fmt = MEDIA_BUS_FMT_VUY8_1X24, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444, + .sf = scaling_factors_888, + }, { + .bus_fmt = MEDIA_BUS_FMT_UYVY10_1X20, + .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 | + ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422, + .sf = scaling_factors_101010, + }, +}; + static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg) { return readl(disp->avbuf.base + reg); @@ -883,16 +924,17 @@ zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, } /** - * zynqmp_disp_layer_drm_formats - Return the DRM formats supported by the layer + * zynqmp_disp_layer_formats - Return DRM or media bus formats supported by + * the layer * @layer: The layer * @num_formats: Pointer to the returned number of formats * - * Return: A newly allocated u32 array that stores all the DRM formats + * Return: A newly allocated u32 array that stores all DRM or media bus formats * supported by the layer. The number of formats in the array is returned * through the num_formats argument. */ -u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, - unsigned int *num_formats) +u32 *zynqmp_disp_layer_formats(struct zynqmp_disp_layer *layer, + unsigned int *num_formats) { unsigned int i; u32 *formats; @@ -1131,6 +1173,11 @@ static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) .num_channels = 1, }, }; + static const struct zynqmp_disp_layer_info live_layer_info = { + .formats = avbuf_live_fmts, + .num_formats = ARRAY_SIZE(avbuf_live_fmts), + .num_channels = 0, + }; unsigned int i; int ret; @@ -1140,12 +1187,16 @@ static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) layer->id = i; layer->disp = disp; - layer->info = &layer_info[i]; /* For now assume dpsub works in either live or non-live mode for both layers. * Hybrid mode is not supported yet. */ - layer->mode = disp->dpsub->dma_enabled ? ZYNQMP_DPSUB_LAYER_NONLIVE - : ZYNQMP_DPSUB_LAYER_LIVE; + if (disp->dpsub->dma_enabled) { + layer->mode = ZYNQMP_DPSUB_LAYER_NONLIVE; + layer->info = &layer_info[i]; + } else { + layer->mode = ZYNQMP_DPSUB_LAYER_LIVE; + layer->info = &live_layer_info; + } ret = zynqmp_disp_layer_request_dma(disp, layer); if (ret) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.h b/drivers/gpu/drm/xlnx/zynqmp_disp.h index 9b8b202224d9..88c285a12e23 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.h @@ -50,8 +50,8 @@ int zynqmp_disp_setup_clock(struct zynqmp_disp *disp, void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, bool enable, u32 alpha); -u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer, - unsigned int *num_formats); +u32 *zynqmp_disp_layer_formats(struct zynqmp_disp_layer *layer, + unsigned int *num_formats); void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 04b6bcac3b07..a0d169ac48c0 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1568,6 +1568,31 @@ static const struct drm_edid *zynqmp_dp_bridge_edid_read(struct drm_bridge *brid return drm_edid_read_ddc(connector, &dp->aux.ddc); } +static u32 * +zynqmp_dp_bridge_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + struct zynqmp_dp *dp = bridge_to_dp(bridge); + struct zynqmp_disp_layer *layer; + enum zynqmp_dpsub_layer_id layer_id; + + if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) + layer_id = ZYNQMP_DPSUB_LAYER_VID; + else if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_GFX)) + layer_id = ZYNQMP_DPSUB_LAYER_GFX; + else { + *num_input_fmts = 0; + return NULL; + } + layer = dp->dpsub->layers[layer_id]; + + return zynqmp_disp_layer_formats(layer, num_input_fmts); +} + static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = { .attach = zynqmp_dp_bridge_attach, .detach = zynqmp_dp_bridge_detach, @@ -1580,6 +1605,7 @@ static const struct drm_bridge_funcs zynqmp_dp_bridge_funcs = { .atomic_check = zynqmp_dp_bridge_atomic_check, .detect = zynqmp_dp_bridge_detect, .edid_read = zynqmp_dp_bridge_edid_read, + .atomic_get_input_bus_fmts = zynqmp_dp_bridge_get_input_bus_fmts, }; /* ----------------------------------------------------------------------------- diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index 43bf416b33d5..bf9fba01df0e 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -152,7 +152,7 @@ static int zynqmp_dpsub_create_planes(struct zynqmp_dpsub *dpsub) unsigned int num_formats; u32 *formats; - formats = zynqmp_disp_layer_drm_formats(layer, &num_formats); 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Tue, 12 Mar 2024 19:55:07 -0500 From: Anatoliy Klymenko Date: Tue, 12 Mar 2024 17:55:01 -0700 Subject: [PATCH v2 4/8] drm: xlnx: zynqmp_dpsub: Minimize usage of global flag Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240312-dp-live-fmt-v2-4-a9c35dc5c50d@amd.com> References: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> In-Reply-To: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Michal Simek , "Andrzej Hajda" , Neil Armstrong , Robert Foss , Jonas Karlman , "Jernej Skrabec" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab CC: , , , , , Anatoliy Klymenko X-Mailer: b4 0.13.0 Received-SPF: None (SATLEXMB03.amd.com: anatoliy.klymenko@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|SA1PR12MB8723:EE_ X-MS-Office365-Filtering-Correlation-Id: be69a5a1-5736-47c2-6fa9-08dc42f83ca0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This flag signals whether the driver runs in DRM CRTC or DRM bridge mode, assuming that all display layers share the same live or non-live mode of operation. Using per-layer mode instead of global flag will siplify future support of the hybrid scenario. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index af851190f447..dd48fa60fa9a 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -975,7 +975,7 @@ void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) { unsigned int i; - if (layer->disp->dpsub->dma_enabled) { + if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { for (i = 0; i < layer->drm_fmt->num_planes; i++) dmaengine_terminate_sync(layer->dmas[i].chan); } @@ -1001,7 +1001,7 @@ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); - if (!layer->disp->dpsub->dma_enabled) + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return; /* @@ -1039,7 +1039,7 @@ int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, const struct drm_format_info *info = layer->drm_fmt; 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Tue, 12 Mar 2024 19:55:10 -0500 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 12 Mar 2024 19:55:09 -0500 From: Anatoliy Klymenko Date: Tue, 12 Mar 2024 17:55:02 -0700 Subject: [PATCH v2 5/8] drm: xlnx: zynqmp_dpsub: Set input live format Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240312-dp-live-fmt-v2-5-a9c35dc5c50d@amd.com> References: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> In-Reply-To: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Michal Simek , "Andrzej Hajda" , Neil Armstrong , Robert Foss , Jonas Karlman , "Jernej Skrabec" , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab CC: , , , , , Anatoliy Klymenko X-Mailer: b4 0.13.0 Received-SPF: None (SATLEXMB03.amd.com: anatoliy.klymenko@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD76:EE_|CH3PR12MB7545:EE_ X-MS-Office365-Filtering-Correlation-Id: 60b2752b-022f-485b-1234-08dc42f83cbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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In the bridge mode of operation, DPSUB is connected to FPGA CRTC which almost certainly supports a single media bus format as its output. Expect this to be delivered via the new bridge atomic state. Program DPSUB registers accordingly. Update zynqmp_disp_layer_set_format() API to fit both live and non-live layer types. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/xlnx/zynqmp_disp.c | 93 +++++++++++++++++++++++++++++++------- drivers/gpu/drm/xlnx/zynqmp_disp.h | 2 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 13 ++++-- drivers/gpu/drm/xlnx/zynqmp_kms.c | 2 +- 4 files changed, 87 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c index dd48fa60fa9a..0cacd597f4b8 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c @@ -383,7 +383,7 @@ static const struct zynqmp_disp_format avbuf_live_fmts[] = { ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, .sf = scaling_factors_666, }, { - .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X24, + .bus_fmt = MEDIA_BUS_FMT_RBG888_1X24, .buf_fmt = ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 | ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB, .sf = scaling_factors_888, @@ -433,19 +433,28 @@ static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp, const struct zynqmp_disp_format *fmt) { unsigned int i; - u32 val; + u32 val, reg; - val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT); - val &= zynqmp_disp_layer_is_video(layer) - ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK - : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; - val |= fmt->buf_fmt; - zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val); + layer->disp_fmt = fmt; + if (layer->mode == ZYNQMP_DPSUB_LAYER_NONLIVE) { + reg = ZYNQMP_DISP_AV_BUF_FMT; + val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT); + val &= zynqmp_disp_layer_is_video(layer) + ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK + : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; + val |= fmt->buf_fmt; + } else { + reg = zynqmp_disp_layer_is_video(layer) + ? ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG + : ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG; + val = fmt->buf_fmt; + } + zynqmp_disp_avbuf_write(disp, reg, val); for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { - unsigned int reg = zynqmp_disp_layer_is_video(layer) - ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) - : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); + reg = zynqmp_disp_layer_is_video(layer) + ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) + : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]); } @@ -984,23 +993,73 @@ void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) zynqmp_disp_blend_layer_disable(layer->disp, layer); } +struct zynqmp_disp_bus_to_drm { + u32 bus_fmt; + u32 drm_fmt; +}; + +/** + * zynqmp_disp_reference_drm_format - Get reference DRM format corresponding + * to the given media bus format. + * @bus_format: Media bus format + * + * Map media bus format to some DRM format that represents the same color space + * and chroma subsampling as the @bus_format video signal. These DRM format + * properties are required to program the blender. + * + * Return: DRM format code corresponding to @bus_format + */ +static u32 zynqmp_disp_reference_drm_format(u32 bus_format) +{ + static const struct zynqmp_disp_bus_to_drm format_map[] = { + { + .bus_fmt = MEDIA_BUS_FMT_RGB666_1X18, + .drm_fmt = DRM_FORMAT_RGB565, + }, { + .bus_fmt = MEDIA_BUS_FMT_RBG888_1X24, + .drm_fmt = DRM_FORMAT_RGB888, + }, { + .bus_fmt = MEDIA_BUS_FMT_UYVY8_1X16, + .drm_fmt = DRM_FORMAT_YUV422, + }, { + .bus_fmt = MEDIA_BUS_FMT_VUY8_1X24, + .drm_fmt = DRM_FORMAT_YUV444, + }, { + .bus_fmt = MEDIA_BUS_FMT_UYVY10_1X20, + .drm_fmt = DRM_FORMAT_P210, + }, + }; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(format_map); ++i) + if (format_map[i].bus_fmt == bus_format) + return format_map[i].drm_fmt; + + return DRM_FORMAT_INVALID; +} + /** * zynqmp_disp_layer_set_format - Set the layer format * @layer: The layer - * @info: The format info + * @drm_or_bus_format: DRM or media bus format * * Set the format for @layer to @info. The layer must be disabled. */ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, - const struct drm_format_info *info) + u32 drm_or_bus_format) { unsigned int i; - layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); - layer->drm_fmt = info; - + layer->disp_fmt = zynqmp_disp_layer_find_format(layer, drm_or_bus_format); zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) + drm_or_bus_format = zynqmp_disp_reference_drm_format(drm_or_bus_format); + + layer->drm_fmt = drm_format_info(drm_or_bus_format); + if (!layer->drm_fmt) + return; + if (layer->mode == ZYNQMP_DPSUB_LAYER_LIVE) return; @@ -1008,7 +1067,7 @@ void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, * Set pconfig for each DMA channel to indicate they're part of a * video group. */ - for (i = 0; i < info->num_planes; i++) { + for (i = 0; i < layer->drm_fmt->num_planes; i++) { struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; struct xilinx_dpdma_peripheral_config pconfig = { .video_group = true, diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.h b/drivers/gpu/drm/xlnx/zynqmp_disp.h index 88c285a12e23..9f9a5f50ffbc 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_disp.h +++ b/drivers/gpu/drm/xlnx/zynqmp_disp.h @@ -55,7 +55,7 @@ u32 *zynqmp_disp_layer_formats(struct zynqmp_disp_layer *layer, void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer); void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, - const struct drm_format_info *info); + u32 drm_or_bus_format); int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, struct drm_plane_state *state); diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index a0d169ac48c0..fc6b1d783c28 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -1281,7 +1281,8 @@ static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, { enum zynqmp_dpsub_layer_id layer_id; struct zynqmp_disp_layer *layer; - const struct drm_format_info *info; + struct drm_bridge_state *bridge_state; + u32 bus_fmt; if (dp->dpsub->connected_ports & BIT(ZYNQMP_DPSUB_PORT_LIVE_VIDEO)) layer_id = ZYNQMP_DPSUB_LAYER_VID; @@ -1291,10 +1292,14 @@ static void zynqmp_dp_disp_enable(struct zynqmp_dp *dp, return; layer = dp->dpsub->layers[layer_id]; + bridge_state = drm_atomic_get_new_bridge_state(old_bridge_state->base.state, + old_bridge_state->bridge); + if (WARN_ON(!bridge_state)) + return; + + bus_fmt = bridge_state->input_bus_cfg.format; + zynqmp_disp_layer_set_format(layer, bus_fmt); - /* TODO: Make the format configurable. */ - info = drm_format_info(DRM_FORMAT_YUV422); - zynqmp_disp_layer_set_format(layer, info); zynqmp_disp_layer_enable(layer); if (layer_id == ZYNQMP_DPSUB_LAYER_GFX) diff --git a/drivers/gpu/drm/xlnx/zynqmp_kms.c b/drivers/gpu/drm/xlnx/zynqmp_kms.c index bf9fba01df0e..d96b3f3f2e3a 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_kms.c +++ b/drivers/gpu/drm/xlnx/zynqmp_kms.c @@ -111,7 +111,7 @@ static void zynqmp_dpsub_plane_atomic_update(struct drm_plane *plane, if (old_state->fb) zynqmp_disp_layer_disable(layer); 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Tue, 12 Mar 2024 19:55:12 -0500 Received: from xsjanatoliy50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 12 Mar 2024 19:55:10 -0500 From: Anatoliy Klymenko Date: Tue, 12 Mar 2024 17:55:03 -0700 Subject: [PATCH v2 6/8] drm/atomic-helper: Add select_output_bus_format callback Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240312-dp-live-fmt-v2-6-a9c35dc5c50d@amd.com> References: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> In-Reply-To: <20240312-dp-live-fmt-v2-0-a9c35dc5c50d@amd.com> To: Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Michal Simek , Andrzej Hajda , Neil Armstrong , Robert Foss , Jonas Karlman , Jernej Skrabec , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab CC: , , , , , Anatoliy Klymenko X-Mailer: b4 0.13.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD75:EE_|SJ1PR12MB6123:EE_ X-MS-Office365-Filtering-Correlation-Id: 817388a4-6e32-4bc5-ac05-08dc42f83d5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 00:55:12.7948 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 817388a4-6e32-4bc5-ac05-08dc42f83d5c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD75.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6123 Add optional drm_crtc_helper_funcs.select_output_bus_format callback. This callback allows to negotiate compatible media bus format on the link between CRTC and connected DRM encoder or DRM bridge chain. A good usage example is the CRTC implemented as FPGA soft IP. This kind of CRTC will most certainly support a single output media bus format, as supporting multiple runtime options consumes extra FPGA resources. A variety of options for the FPGA designs are usually achieved by synthesizing IP with different parameters. Add drm_helper_crtc_select_output_bus_format that wraps drm_crtc_helper_funcs.select_output_bus_format. Incorporate select_output_bus_format callback into the format negotiation stage to fix the input bus format of the first DRM bridge in the chain. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/drm_bridge.c | 14 +++++++++++-- drivers/gpu/drm/drm_crtc_helper.c | 36 ++++++++++++++++++++++++++++++++ include/drm/drm_crtc_helper.h | 5 +++++ include/drm/drm_modeset_helper_vtables.h | 30 ++++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_bridge.c b/drivers/gpu/drm/drm_bridge.c index 521a71c61b16..955ca108cd4b 100644 --- a/drivers/gpu/drm/drm_bridge.c +++ b/drivers/gpu/drm/drm_bridge.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -879,7 +880,8 @@ static int select_bus_fmt_recursive(struct drm_bridge *first_bridge, unsigned int i, num_in_bus_fmts = 0; struct drm_bridge_state *cur_state; struct drm_bridge *prev_bridge; - u32 *in_bus_fmts; + struct drm_crtc *crtc = crtc_state->crtc; + u32 *in_bus_fmts, in_fmt; int ret; prev_bridge = drm_bridge_get_prev_bridge(cur_bridge); @@ -933,7 +935,15 @@ static int select_bus_fmt_recursive(struct drm_bridge *first_bridge, return -ENOMEM; if (first_bridge == cur_bridge) { - cur_state->input_bus_cfg.format = in_bus_fmts[0]; + in_fmt = drm_helper_crtc_select_output_bus_format(crtc, + crtc_state, + in_bus_fmts, + num_in_bus_fmts); + if (!in_fmt) { + kfree(in_bus_fmts); + return -ENOTSUPP; + } + cur_state->input_bus_cfg.format = in_fmt; cur_state->output_bus_cfg.format = out_bus_fmt; kfree(in_bus_fmts); return 0; diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c index 2dafc39a27cb..f2e12a3c4e5f 100644 --- a/drivers/gpu/drm/drm_crtc_helper.c +++ b/drivers/gpu/drm/drm_crtc_helper.c @@ -1055,3 +1055,39 @@ int drm_helper_force_disable_all(struct drm_device *dev) return ret; } EXPORT_SYMBOL(drm_helper_force_disable_all); + +/** + * drm_helper_crtc_select_output_bus_format - Select output media bus format + * @crtc: The CRTC to query + * @crtc_state: The new CRTC state + * @supported_fmts: List of media bus format options to pick from + * @num_supported_fmts: Number of media bus formats in @supported_fmts list + * + * Encoder drivers may call this helper to give the connected CRTC a chance to + * select compatible or preffered media bus format to use over the CRTC encoder + * link. Encoders should provide list of supported input MEDIA_BUS_FMT_* for + * CRTC to pick from. CRTC driver is expected to select preferred media bus + * format from the list and, once enabled, generate the signal accordingly. + * + * Returns: + * Selected preferred media bus format or 0 if CRTC does not support any from + * @supported_fmts list. + */ +u32 drm_helper_crtc_select_output_bus_format(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + const u32 *supported_fmts, + unsigned int num_supported_fmts) +{ + if (!crtc || !supported_fmts || !num_supported_fmts) + return 0; + + if (!crtc->helper_private || + !crtc->helper_private->select_output_bus_format) + return supported_fmts[0]; + + return crtc->helper_private->select_output_bus_format(crtc, + crtc_state, + supported_fmts, + num_supported_fmts); +} +EXPORT_SYMBOL(drm_helper_crtc_select_output_bus_format); diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h index 8c886fc46ef2..b7eb52f3ce41 100644 --- a/include/drm/drm_crtc_helper.h +++ b/include/drm/drm_crtc_helper.h @@ -38,6 +38,7 @@ struct drm_atomic_state; struct drm_connector; struct drm_crtc; +struct drm_crtc_state; struct drm_device; struct drm_display_mode; struct drm_encoder; @@ -61,5 +62,9 @@ int drm_helper_connector_dpms(struct drm_connector *connector, int mode); void drm_helper_resume_force_mode(struct drm_device *dev); int drm_helper_force_disable_all(struct drm_device *dev); +u32 drm_helper_crtc_select_output_bus_format(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + const u32 *supported_fmts, + unsigned int num_supported_fmts); #endif diff --git a/include/drm/drm_modeset_helper_vtables.h b/include/drm/drm_modeset_helper_vtables.h index 881b03e4dc28..6d5a081e21a4 100644 --- a/include/drm/drm_modeset_helper_vtables.h +++ b/include/drm/drm_modeset_helper_vtables.h @@ -489,6 +489,36 @@ struct drm_crtc_helper_funcs { bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); + + /** + * @select_output_bus_format + * + * Called by the connected DRM encoder to negotiate input media bus + * format. CRTC is expected to pick preferable media formats from the + * list provided by the DRM encoder. + * + * This callback is optional. + * + * Parameters: + * + * crtc: + * The CRTC. + * crcs_state: + * New CRTC state. + * supported_fmts: + * List of input bus formats supported by the encoder. + * num_supported_fmts: + * Number of formats in the list. + * + * Returns: + * + * Preferred bus format from the list or 0 if CRTC doesn't support any + * from the provided list. + */ + u32 (*select_output_bus_format)(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state, + const u32 *supported_fmts, + unsigned int num_supported_fmts); }; /** From patchwork Wed Mar 13 00:55:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Klymenko, Anatoliy" X-Patchwork-Id: 13590805 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DAB7A14AAE; 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REFERENCE ONLY. Add binding for AMD/Xilinx Video Timing Controller and Test Pattern Generator. Copy media-bus-formats.h into dt-bindings/media to suplement TPG DT node. Signed-off-by: Anatoliy Klymenko --- .../bindings/display/xlnx/xlnx,v-tpg.yaml | 87 ++++++++++ .../devicetree/bindings/display/xlnx/xlnx,vtc.yaml | 65 ++++++++ include/dt-bindings/media/media-bus-format.h | 177 +++++++++++++++++++++ 3 files changed, 329 insertions(+) diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,v-tpg.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,v-tpg.yaml new file mode 100644 index 000000000000..df5ee5b547cf --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,v-tpg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/xlnx/xlnx,v-tpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Video Test Pattern Generator (TPG) + +description: + AMD/Xilinx Video Test Pattern Generator IP is a soft IP designed to + generate test video signal in AXI4-Stream Video format. + https://docs.xilinx.com/r/en-US/pg103-v-tpg + +maintainers: + - Anatoliy Klymenko + +properties: + compatible: + description: + TPG versions backward-compatible with previous versions should list all + compatible versions in the newer to older order. + enum: ["xlnx,v-tpg-8.0", "xlnx,v-tpg-8.2"] + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + bus-format: + description: Output media bus format, one of MEDIA_BUS_FMT_* + maxItems: 1 + + xlnx,bridge: + description: Reference to Video Timing Controller + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: + Connections from and to external components in the video pipeline. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Sink port connected to downstream video IP. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Source port to connect to optional video signal source. + + required: + - port@0 + +required: + - compatible + - reg + - interrupts + - bus-format + - xlnx,bridge + - ports + +additionalProperties: false + +examples: + - | + #include + + tpg_0: tpg@40050000 { + compatible = "xlnx,v-tpg-8.0"; + reg = <0x40050000 0x10000>; + interrupts = <0 89 4>; + xlnx,bridge = <&vtc_3>; + bus-format = ; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + tpg_out: endpoint { + remote-endpoint = <&dp_encoder>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.yaml new file mode 100644 index 000000000000..51eb12cdcfdc --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,vtc.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/xlnx/xlnx,vtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Device-Tree for Xilinx Video Timing Controller(VTC) + +description: + Xilinx VTC is a general purpose video timing generator and detector. + The input side of this core automatically detects horizontal and + vertical synchronization, pulses, polarity, blanking timing and active pixels. + While on the output, it generates the horizontal and vertical blanking and + synchronization pulses used with a standard video system including support + for programmable pulse polarity. + + The core is commonly used with Video in to AXI4-Stream core to detect the + format and timing of incoming video data or with AXI4-Stream to Video out core + to generate outgoing video timing for downstream sinks like a video monitor. + + For details please refer to + https://docs.xilinx.com/r/en-US/pg016_v_tc + +maintainers: + - Sagar Vishal + +properties: + compatible: + const: "xlnx,bridge-v-tc-6.1" + + reg: + maxItems: 1 + + xlnx,pixels-per-clock: + description: Pixels per clock of the stream. + enum: [1, 2, 4] + + clocks: + minItems: 2 + + clock-names: + items: + - const: clk + - const: s_axi_aclk + +required: + - compatible + - reg + - xlnx,pixels-per-clock + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + v_tc_0: v_tc@80010000 { + clock-names = "clk", "s_axi_aclk"; + clocks = <&clk_wiz_0>, <&misc_clk_0>; + compatible = "xlnx,bridge-v-tc-6.1"; + xlnx,pixels-per-clock = <1>; + reg = <0x80010000 0x10000>; + }; + +... diff --git a/include/dt-bindings/media/media-bus-format.h b/include/dt-bindings/media/media-bus-format.h new file mode 100644 index 000000000000..60fc6e11dabc --- /dev/null +++ b/include/dt-bindings/media/media-bus-format.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Media Bus API header + * + * Copyright (C) 2009, Guennadi Liakhovetski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __LINUX_MEDIA_BUS_FORMAT_H +#define __LINUX_MEDIA_BUS_FORMAT_H + +/* + * These bus formats uniquely identify data formats on the data bus. Format 0 + * is reserved, MEDIA_BUS_FMT_FIXED shall be used by host-client pairs, where + * the data format is fixed. Additionally, "2X8" means that one pixel is + * transferred in two 8-bit samples, "BE" or "LE" specify in which order those + * samples are transferred over the bus: "LE" means that the least significant + * bits are transferred first, "BE" means that the most significant bits are + * transferred first, and "PADHI" and "PADLO" define which bits - low or high, + * in the incomplete high byte, are filled with padding bits. + * + * The bus formats are grouped by type, bus_width, bits per component, samples + * per pixel and order of subsamples. Numerical values are sorted using generic + * numerical sort order (8 thus comes before 10). + * + * As their value can't change when a new bus format is inserted in the + * enumeration, the bus formats are explicitly given a numerical value. The next + * free values for each category are listed below, update them when inserting + * new pixel codes. + */ + +#define MEDIA_BUS_FMT_FIXED 0x0001 + +/* RGB - next is 0x1026 */ +#define MEDIA_BUS_FMT_RGB444_1X12 0x1016 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE 0x1001 +#define MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE 0x1002 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE 0x1003 +#define MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE 0x1004 +#define MEDIA_BUS_FMT_RGB565_1X16 0x1017 +#define MEDIA_BUS_FMT_BGR565_2X8_BE 0x1005 +#define MEDIA_BUS_FMT_BGR565_2X8_LE 0x1006 +#define MEDIA_BUS_FMT_RGB565_2X8_BE 0x1007 +#define MEDIA_BUS_FMT_RGB565_2X8_LE 0x1008 +#define MEDIA_BUS_FMT_RGB666_1X18 0x1009 +#define MEDIA_BUS_FMT_RGB666_2X9_BE 0x1025 +#define MEDIA_BUS_FMT_BGR666_1X18 0x1023 +#define MEDIA_BUS_FMT_RBG888_1X24 0x100e +#define MEDIA_BUS_FMT_RGB666_1X24_CPADHI 0x1015 +#define MEDIA_BUS_FMT_BGR666_1X24_CPADHI 0x1024 +#define MEDIA_BUS_FMT_RGB565_1X24_CPADHI 0x1022 +#define MEDIA_BUS_FMT_RGB666_1X7X3_SPWG 0x1010 +#define MEDIA_BUS_FMT_BGR888_1X24 0x1013 +#define MEDIA_BUS_FMT_BGR888_3X8 0x101b +#define MEDIA_BUS_FMT_GBR888_1X24 0x1014 +#define MEDIA_BUS_FMT_RGB888_1X24 0x100a +#define MEDIA_BUS_FMT_RGB888_2X12_BE 0x100b +#define MEDIA_BUS_FMT_RGB888_2X12_LE 0x100c +#define MEDIA_BUS_FMT_RGB888_3X8 0x101c +#define MEDIA_BUS_FMT_RGB888_3X8_DELTA 0x101d +#define MEDIA_BUS_FMT_RGB888_1X7X4_SPWG 0x1011 +#define MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA 0x1012 +#define MEDIA_BUS_FMT_RGB666_1X30_CPADLO 0x101e +#define MEDIA_BUS_FMT_RGB888_1X30_CPADLO 0x101f +#define MEDIA_BUS_FMT_ARGB8888_1X32 0x100d +#define MEDIA_BUS_FMT_RGB888_1X32_PADHI 0x100f +#define MEDIA_BUS_FMT_RGB101010_1X30 0x1018 +#define MEDIA_BUS_FMT_RGB666_1X36_CPADLO 0x1020 +#define MEDIA_BUS_FMT_RGB888_1X36_CPADLO 0x1021 +#define MEDIA_BUS_FMT_RGB121212_1X36 0x1019 +#define MEDIA_BUS_FMT_RGB161616_1X48 0x101a + +/* YUV (including grey) - next is 0x202f */ +#define MEDIA_BUS_FMT_Y8_1X8 0x2001 +#define MEDIA_BUS_FMT_UV8_1X8 0x2015 +#define MEDIA_BUS_FMT_UYVY8_1_5X8 0x2002 +#define MEDIA_BUS_FMT_VYUY8_1_5X8 0x2003 +#define MEDIA_BUS_FMT_YUYV8_1_5X8 0x2004 +#define MEDIA_BUS_FMT_YVYU8_1_5X8 0x2005 +#define MEDIA_BUS_FMT_UYVY8_2X8 0x2006 +#define MEDIA_BUS_FMT_VYUY8_2X8 0x2007 +#define MEDIA_BUS_FMT_YUYV8_2X8 0x2008 +#define MEDIA_BUS_FMT_YVYU8_2X8 0x2009 +#define MEDIA_BUS_FMT_Y10_1X10 0x200a +#define MEDIA_BUS_FMT_Y10_2X8_PADHI_LE 0x202c +#define MEDIA_BUS_FMT_UYVY10_2X10 0x2018 +#define MEDIA_BUS_FMT_VYUY10_2X10 0x2019 +#define MEDIA_BUS_FMT_YUYV10_2X10 0x200b +#define MEDIA_BUS_FMT_YVYU10_2X10 0x200c +#define MEDIA_BUS_FMT_Y12_1X12 0x2013 +#define MEDIA_BUS_FMT_UYVY12_2X12 0x201c +#define MEDIA_BUS_FMT_VYUY12_2X12 0x201d +#define MEDIA_BUS_FMT_YUYV12_2X12 0x201e +#define MEDIA_BUS_FMT_YVYU12_2X12 0x201f +#define MEDIA_BUS_FMT_Y14_1X14 0x202d +#define MEDIA_BUS_FMT_Y16_1X16 0x202e +#define MEDIA_BUS_FMT_UYVY8_1X16 0x200f +#define MEDIA_BUS_FMT_VYUY8_1X16 0x2010 +#define MEDIA_BUS_FMT_YUYV8_1X16 0x2011 +#define MEDIA_BUS_FMT_YVYU8_1X16 0x2012 +#define MEDIA_BUS_FMT_YDYUYDYV8_1X16 0x2014 +#define MEDIA_BUS_FMT_UYVY10_1X20 0x201a +#define MEDIA_BUS_FMT_VYUY10_1X20 0x201b +#define MEDIA_BUS_FMT_YUYV10_1X20 0x200d +#define MEDIA_BUS_FMT_YVYU10_1X20 0x200e +#define MEDIA_BUS_FMT_VUY8_1X24 0x2024 +#define MEDIA_BUS_FMT_YUV8_1X24 0x2025 +#define MEDIA_BUS_FMT_UYYVYY8_0_5X24 0x2026 +#define MEDIA_BUS_FMT_UYVY12_1X24 0x2020 +#define MEDIA_BUS_FMT_VYUY12_1X24 0x2021 +#define MEDIA_BUS_FMT_YUYV12_1X24 0x2022 +#define MEDIA_BUS_FMT_YVYU12_1X24 0x2023 +#define MEDIA_BUS_FMT_YUV10_1X30 0x2016 +#define MEDIA_BUS_FMT_UYYVYY10_0_5X30 0x2027 +#define MEDIA_BUS_FMT_AYUV8_1X32 0x2017 +#define MEDIA_BUS_FMT_UYYVYY12_0_5X36 0x2028 +#define MEDIA_BUS_FMT_YUV12_1X36 0x2029 +#define MEDIA_BUS_FMT_YUV16_1X48 0x202a +#define MEDIA_BUS_FMT_UYYVYY16_0_5X48 0x202b + +/* Bayer - next is 0x3021 */ +#define MEDIA_BUS_FMT_SBGGR8_1X8 0x3001 +#define MEDIA_BUS_FMT_SGBRG8_1X8 0x3013 +#define MEDIA_BUS_FMT_SGRBG8_1X8 0x3002 +#define MEDIA_BUS_FMT_SRGGB8_1X8 0x3014 +#define MEDIA_BUS_FMT_SBGGR10_ALAW8_1X8 0x3015 +#define MEDIA_BUS_FMT_SGBRG10_ALAW8_1X8 0x3016 +#define MEDIA_BUS_FMT_SGRBG10_ALAW8_1X8 0x3017 +#define MEDIA_BUS_FMT_SRGGB10_ALAW8_1X8 0x3018 +#define MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 0x300b +#define MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 0x300c +#define MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 0x3009 +#define MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 0x300d +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE 0x3003 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE 0x3004 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE 0x3005 +#define MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE 0x3006 +#define MEDIA_BUS_FMT_SBGGR10_1X10 0x3007 +#define MEDIA_BUS_FMT_SGBRG10_1X10 0x300e +#define MEDIA_BUS_FMT_SGRBG10_1X10 0x300a +#define MEDIA_BUS_FMT_SRGGB10_1X10 0x300f +#define MEDIA_BUS_FMT_SBGGR12_1X12 0x3008 +#define MEDIA_BUS_FMT_SGBRG12_1X12 0x3010 +#define MEDIA_BUS_FMT_SGRBG12_1X12 0x3011 +#define MEDIA_BUS_FMT_SRGGB12_1X12 0x3012 +#define MEDIA_BUS_FMT_SBGGR14_1X14 0x3019 +#define MEDIA_BUS_FMT_SGBRG14_1X14 0x301a +#define MEDIA_BUS_FMT_SGRBG14_1X14 0x301b +#define MEDIA_BUS_FMT_SRGGB14_1X14 0x301c +#define MEDIA_BUS_FMT_SBGGR16_1X16 0x301d +#define MEDIA_BUS_FMT_SGBRG16_1X16 0x301e +#define MEDIA_BUS_FMT_SGRBG16_1X16 0x301f +#define MEDIA_BUS_FMT_SRGGB16_1X16 0x3020 + +/* JPEG compressed formats - next is 0x4002 */ +#define MEDIA_BUS_FMT_JPEG_1X8 0x4001 + +/* Vendor specific formats - next is 0x5002 */ + +/* S5C73M3 sensor specific interleaved UYVY and JPEG */ +#define MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8 0x5001 + +/* HSV - next is 0x6002 */ +#define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 + +/* + * This format should be used when the same driver handles + * both sides of the link and the bus format is a fixed + * metadata format that is not configurable from userspace. + * Width and height will be set to 0 for this format. + */ +#define MEDIA_BUS_FMT_METADATA_FIXED 0x7001 + +#endif /* __LINUX_MEDIA_BUS_FORMAT_H */ From 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REFERENCE ONLY. Add CRTC driver based on AMD/Xilinx Video Test Pattern Generator IP. TPG based FPGA design represents minimalistic harness useful for testing links between FPGA based CRTC and external DRM encoders, both FPGA and hardened IP based. Add driver for AMD/Xilinx Video Timing Controller. The VTC, working in generator mode, suplements TPG with video timing signals. Signed-off-by: Anatoliy Klymenko --- drivers/gpu/drm/xlnx/Kconfig | 21 + drivers/gpu/drm/xlnx/Makefile | 4 + drivers/gpu/drm/xlnx/xlnx_tpg.c | 854 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/xlnx/xlnx_vtc.c | 452 ++++++++++++++++++ drivers/gpu/drm/xlnx/xlnx_vtc.h | 101 +++++ drivers/gpu/drm/xlnx/xlnx_vtc_list.c | 160 +++++++ 6 files changed, 1592 insertions(+) diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index 68ee897de9d7..c40e98c1a5e6 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -15,3 +15,24 @@ config DRM_ZYNQMP_DPSUB This is a DRM/KMS driver for ZynqMP DisplayPort controller. Choose this option if you have a Xilinx ZynqMP SoC with DisplayPort subsystem. + +config DRM_XLNX_BRIDGE_VTC + bool "Xilinx DRM VTC Driver" + depends on OF + help + DRM brige driver for Xilinx Video Timing Controller. Choose + this option to make VTC a part of the CRTC in display pipeline. + Currently the support is added to the Xilinx Video Mixer and + Xilinx PL display CRTC drivers. This driver provides ability + to generate timings through the bridge layer. + +config DRM_XLNX_TPG + bool "Xilinx DRM TPG Driver" + depends on DRM && OF + select DRM_XLNX_BRIDGE_VTC + select VIDEOMODE_HELPERS + help + CRTC driver based on AMD/Xilinx Test Pattern Generator IP. Choose + this driver to enable Test Pattern Generator CRTC. This driver + implements simplistic CRTC with the single plane and is perfect for + testing PL to PS and PL to PL display output pipelines. diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index ea1422a39502..26fb3ad21fa9 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,6 @@ zynqmp-dpsub-y := zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o zynqmp_kms.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) += zynqmp-dpsub.o +xlnx-tpg-objs := xlnx_tpg.o +xlnx-tpg-$(CONFIG_DRM_XLNX_BRIDGE_VTC) += xlnx_vtc_list.o +obj-$(CONFIG_DRM_XLNX_TPG) += xlnx-tpg.o +obj-$(CONFIG_DRM_XLNX_BRIDGE_VTC) += xlnx_vtc.o diff --git a/drivers/gpu/drm/xlnx/xlnx_tpg.c b/drivers/gpu/drm/xlnx/xlnx_tpg.c new file mode 100644 index 000000000000..297a65fdb289 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_tpg.c @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx logicore test pattern generator driver + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + * + * Author: Anatoliy Klymenko + * + * This driver introduces support for the test CRTC based on AMD/Xilinx + * Test Pattern Generator IP. The main goal of the driver is to enable + * simplistic FPGA design that could be used to test FPGA CRTC to external + * encoder IP connectivity. + * Reference: https://docs.xilinx.com/r/en-US/pg103-v-tpg + */ + +#include "xlnx_vtc.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include