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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066E9.mail.protection.outlook.com (10.167.249.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Wed, 13 Mar 2024 10:00:47 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 13 Mar 2024 05:00:39 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v7 1/6] cpufreq:amd-pstate: fix the nominal freq value set Date: Wed, 13 Mar 2024 17:59:13 +0800 Message-ID: <08ed1f9f76a6a1c401efd8f426bdeb9681c4b4e9.1710323410.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E9:EE_|PH7PR12MB9125:EE_ X-MS-Office365-Filtering-Correlation-Id: ff210852-c70b-422e-a409-08dc434474f4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:00:47.6450 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff210852-c70b-422e-a409-08dc434474f4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9125 Address an untested error where the nominal_freq was returned in KHz instead of the correct MHz units, this oversight led to a wrong nominal_freq set and resued, it will cause the max frequency of core to be initialized with a wrong frequency value. Cc: stable@vger.kernel.org Fixes: ec437d71db7 ("cpufreq: amd-pstate: Introduce a new AMD P-State driver to support future processors") Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2015c9fcc3c9..3faa895b77b7 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -647,8 +647,7 @@ static int amd_get_nominal_freq(struct amd_cpudata *cpudata) if (ret) return ret; - /* Switch to khz */ - return cppc_perf.nominal_freq * 1000; + return cppc_perf.nominal_freq; } static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) From patchwork Wed Mar 13 09:59:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13591184 Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2059.outbound.protection.outlook.com [40.107.212.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3DAE3A1B5; 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Wed, 13 Mar 2024 05:00:42 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v7 2/6] cpufreq:amd-pstate: initialize nominal_freq of each cpudata Date: Wed, 13 Mar 2024 17:59:14 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E9:EE_|DM6PR12MB4299:EE_ X-MS-Office365-Filtering-Correlation-Id: 9b0468f7-8752-4e09-ec55-08dc4344757e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EwsjtZ+MdT6W5U3U8SIPTS6ny5OpjzLJ4FFb8bRIJMhpAeN8l9Y7Nb4h7kUs3xaPXt9EsbneXr2dYHVW4Z5yl5xoSQTsWfsJieY1OafPUz4WRfyScF6PDDY1vK0OzhizjdyCmUem5+W8frt4Wd1RhpVqXLnLtq9T3E16Wki9r8fVw/7rgom6nf0KLpqkzY1XKYsUUjXdYK3tsgLCVUCmvK6ooK2TOrtL+/nzH4M2mNorlEreiyskSwnwMfRR0ZxCZWB16A1VflZ9QvH28+tBBx8B+8i1sT0RWHbRmoVKTxSkn6rRB6MmzvGP31KJKU5LxGNCG00Vuw632fVEsewst/uIYVQ9G99l99WOWG0mwRZVUfG10VzUfZfnr47OXjzCEQfBMQzFnEWmSLK0zAoXp9jfVFpSsecO6vhT1cNWpNh0S5nKjX61J077D1rhfHmTcyucpq6N0PdHRwVOlUnxUsCTpAPFoFcW0sAtndswAtMpQ1a/qtkgtMWmWpD0fZhAcXNgHqml9tM9Prs65ag8pWx1TBRhYtTPMCe6dpYEH67KaHpTSuSBcMPnsaqq8GPHjRPG2a3+UW2q9JeJ9bUroWk29tKf1r/iLpAMO9EXvAaHJ1H8BYuiQrkSn0r1nZxbdcunreOapZMNt7ixEz+o6kpDCzAWhA6cL4BTyLG6FihzgGDQCUxVDQzEvGBQLCdpCH2OhRlNihZf1c401t/JTnlpR6JVS8tPQszGGSZ8rNaTr9scJvUyQsOxfqTfJc/2 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(82310400014)(1800799015)(36860700004)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:00:48.5513 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b0468f7-8752-4e09-ec55-08dc4344757e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4299 Optimizes the process of retrieving the nominal frequency by utilizing 'cpudata->nominal_freq' instead of repeatedly accessing the cppc_acpi interface. To enhance efficiency and reduce the CPU load, shifted to using 'cpudata->nominal_freq'. It allows for the nominal frequency to be accessed directly from the cached data in 'cpudata' of each CPU. It will also slightly reduce the frequency change latency while using pstate driver passive mode. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3faa895b77b7..6db9256f42c0 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -626,7 +626,7 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) if (ret) return ret; - nominal_freq = cppc_perf.nominal_freq; + nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); @@ -661,7 +661,7 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) if (ret) return ret; - nominal_freq = cppc_perf.nominal_freq; + nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; @@ -855,13 +855,14 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); + cpudata->nominal_freq = nominal_freq; + max_freq = amd_get_max_freq(cpudata); lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); - if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { - dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", - min_freq, max_freq); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq || nominal_freq == 0) { + dev_err(dev, "min_freq(%d) or max_freq(%d) or nominal_freq(%d) is incorrect\n", + min_freq, max_freq, nominal_freq); ret = -EINVAL; goto free_cpudata1; } @@ -900,7 +901,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->min_freq = min_freq; cpudata->max_limit_freq = max_freq; cpudata->min_limit_freq = min_freq; - cpudata->nominal_freq = nominal_freq; cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; @@ -1317,12 +1317,13 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; min_freq = amd_get_min_freq(cpudata); - max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); + cpudata->nominal_freq = nominal_freq; + max_freq = amd_get_max_freq(cpudata); lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); - if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { - dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", - min_freq, max_freq); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq || nominal_freq == 0) { + dev_err(dev, "min_freq(%d) or max_freq(%d) or nominal_freq(%d) is incorrect\n", + min_freq, max_freq, nominal_freq); ret = -EINVAL; goto free_cpudata1; } @@ -1335,7 +1336,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) /* Initial processor data capability frequencies */ cpudata->max_freq = max_freq; cpudata->min_freq = min_freq; - cpudata->nominal_freq = nominal_freq; cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; policy->driver_data = cpudata; From patchwork Wed Mar 13 09:59:15 2024 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000066E9.mail.protection.outlook.com (10.167.249.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7386.12 via Frontend Transport; Wed, 13 Mar 2024 10:00:49 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 13 Mar 2024 05:00:45 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v7 3/6] cpufreq:amd-pstate: get pstate transition delay and latency value from ACPI tables Date: Wed, 13 Mar 2024 17:59:15 +0800 Message-ID: <705e1a21a6a9d91a7ac67526c55c2961318ad678.1710323410.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066E9:EE_|DM6PR12MB4370:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a097344-77e2-4d22-d106-08dc43447625 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:00:49.7232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a097344-77e2-4d22-d106-08dc43447625 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066E9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4370 make pstate driver initially retrieve the P-state transition delay and latency values from the BIOS ACPI tables which has more reasonable delay and latency values according to the platform design and requirements. Previously there values were hardcoded at specific value which may have conflicted with platform and it might not reflect the most accurate or optimized setting for the processor. [054h 0084 8] Preserve Mask : FFFFFFFF00000000 [05Ch 0092 8] Write Mask : 0000000000000001 [064h 0100 4] Command Latency : 00000FA0 [068h 0104 4] Maximum Access Rate : 0000EA60 [06Ch 0108 2] Minimum Turnaround Time : 0000 Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6db9256f42c0..ec6259957d25 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -827,6 +827,36 @@ static void amd_pstate_update_limits(unsigned int cpu) mutex_unlock(&amd_pstate_driver_lock); } +/** + * Get pstate transition delay time from ACPI tables that firmware set + * instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) +{ + u32 transition_delay_ns; + + transition_delay_ns = cppc_get_transition_latency(cpu); + if (transition_delay_ns == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_DELAY; + + return transition_delay_ns / NSEC_PER_USEC; +} + +/** + * Get pstate transition latency value from ACPI tables that firmware set + * instead of using hardcode value directly. + */ +static u32 amd_pstate_get_transition_latency(unsigned int cpu) +{ + u32 transition_latency; + + transition_latency = cppc_get_transition_latency(cpu); + if (transition_latency == CPUFREQ_ETERNAL) + return AMD_PSTATE_TRANSITION_LATENCY; + + return transition_latency; +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -867,8 +897,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) goto free_cpudata1; } - policy->cpuinfo.transition_latency = AMD_PSTATE_TRANSITION_LATENCY; - policy->transition_delay_us = AMD_PSTATE_TRANSITION_DELAY; + policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); + policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); policy->min = min_freq; policy->max = max_freq; From patchwork Wed Mar 13 09:59:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13591186 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC26F3B789; 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Wed, 13 Mar 2024 05:00:48 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v7 4/6] cppc_acpi: print error message if CPPC is unsupported Date: Wed, 13 Mar 2024 17:59:16 +0800 Message-ID: <4bb45bd64bfdf3a8f5a3bffdd8b5475474d9609e.1710323410.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|MN2PR12MB4407:EE_ X-MS-Office365-Filtering-Correlation-Id: d4b20645-7bb6-4cc8-7088-08dc434477ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: z7sREojZoxKunMTVilBH5bQPXLErFoUwyn5nxPUR3sVaeS0tLUHlrrKRePDJsWR0zMvG0iVx32ngkL3ms7F3KI5MeICn/cnTNaOdsIto5cHKaAyCN8IfzDPZM+8lKUJak1nlIKtqPFd541KLbiMwNM0yWXM3ItvMT/N+TT6xJqc44ubwQVKNN0HI4UC1l0VGVSGKlrX9kyNU604PPSc3Lq5Bs6RxDQErhUSswJ2QHaineUqqJ38HS1tBa2lF+//nu1AW+FXalgyoaMzQmcKn9hq3bIfyueh1IpVge6GNABDow7cl7UOcaOWzmtlqsYfsb32s/DyvmRUvFsEB/7r9Z/VN96/piAkry2LPrzsXQ9WsVb7dOypSf84bab8cirPPAXdGLHxfGWAb0PV4QWfy//rMyQ/PoqqdybUdDnFqJPeD//uehABNpfa5BXW/t/bi9og5mqP4//gO+OlNrUQworV/9rnYtvgQkcWX6Cyg+aL5joFMlhz8D3aFU+LIYq02GYDNbmlHHqkW6D5XtsL6XVHoEzt+ww5+UaibMBoMzCHsWUjyn3pLN43S8sKf6hlUzDOOZjVu9KgCjjJfh7KwCoZ9nQmlKBkT2EMvEEQLh80x4IDHWTJ1l3Tymu76MSxP6RUGRYbM7v5YGSiboz9A5h7FSJTb5lhkeZS2c7K6ciD/V8NugciyQVr8ivF1cxqY9P72VTJWgZ76Q75N//llxPvAFvAl9lBYjZdBupAOQM/iIAmBP0jxP+Zb1PPuTZtp X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(376005)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:00:52.7313 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d4b20645-7bb6-4cc8-7088-08dc434477ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4407 to be more clear what is wrong with CPPC when pstate driver failed to load which has dependency on the CPPC capabilities. Add one more debug message to notify user if CPPC is not supported by the CPU, then it will be easy to find out what need to fix for pstate driver loading issue. [ 0.477523] amd_pstate: the _CPC object is not present in SBIOS or ACPI disabled Above message is not clear enough to verify whether CPPC is not supported. Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/acpi/cppc_acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 4bfbe55553f4..3134101f31b6 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -686,8 +686,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr) if (!osc_sb_cppc2_support_acked) { pr_debug("CPPC v2 _OSC not acked\n"); - if (!cpc_supported_by_cpu()) + if (!cpc_supported_by_cpu()) { + pr_debug("CPPC is not supported by the CPU\n"); return -ENODEV; + } } /* Parse the ACPI _CPC table for this CPU. */ From patchwork Wed Mar 13 09:59:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 13591187 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2058.outbound.protection.outlook.com [40.107.243.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C7DE3B798; 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Wed, 13 Mar 2024 05:00:52 -0500 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v7 5/6] cpufreq:amd-pstate: add quirk for the pstate CPPC capabilities missing Date: Wed, 13 Mar 2024 17:59:17 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|CY8PR12MB7124:EE_ X-MS-Office365-Filtering-Correlation-Id: fdc227f5-4c84-4f38-6c0a-08dc434479f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qKp9HjC795ST3/pVxGX5BIE/CdQxlHtU6/yKxmj50bKqyEfls5BOv5/A2M5Q42id1yHRxYn5mP5XXYueJsRADOMZ5mnQ00VfFPnZaVe7LhX1C2KWfik5quO6W4u84BbivD+E5TCgrRYcxIUWZtWshQ6XrlAAeBIyu2ENnh8Y5vwzlbLdFawMjWlLYNONSH4inpzyyji2kt1Egg0k7Ays4AfI/X08eJvySFdYxwZJ4/FrszbeaHpals5AHXM2+TrSfByL9EQI9RFTHt1TBnvYDd/b1vZJTyN0MBbJRJz/0p+CrWvOQE8WNE0Yecn2B2AbcEXJxcnuOSr5slLsEFfyBLSQho2K9w8YRmilF8XsHm3Y3g0IxzLx+/GIzTUUrNQgab4aLlFcah+4yRGZ96LNgx6pyzc8Fm0kBRoweL7cQWpPs0sA/X1WguB3F6bar0ea/sxuyE8gdHBuLU7h7kd3pnGjohej1cvhgpzuOE+y4wLBEGf7knC9JWeOQuhr6yo7Yk5ThAYMSxJqEbLX/zL3M85e67eJOcjKJPYzqRRCZ+9YPhdZTPvC/U9EZSUbxHJFNH349/GjlEN33XeG4Lwfs7kJpKnzrbeQ/qGy+O+TKroxGx4aJtN9JaHLS9eNCvEgWGpe7GBq7PrTwZdkuSP7p5sd2At1wr0OTcPq85FumERVQ5GZTrsJlzKBMa0unt3TDqb0SsUs4j2rTrd+dd7xCE5g0hm8ciJD+NdJD018wuM1grT6KClN3u/wKQcAxP8C X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(376005)(82310400014)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Mar 2024 10:00:56.0907 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fdc227f5-4c84-4f38-6c0a-08dc434479f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7124 Add quirks table to get CPPC capabilities issue fixed by providing correct perf or frequency values while driver loading. If CPPC capabilities are not defined in the ACPI tables or wrongly defined by platform firmware, it needs to use quick to get those issues fixed with correct workaround values to make pstate driver can be loaded even though there are CPPC capabilities errors. The workaround will match the broken BIOS which lack of CPPC capabilities nominal_freq and lowest_freq definition in the ACPI table. $ cat /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_freq 0 $ cat /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_freq 0 Reviewed-by: Mario Limonciello Signed-off-by: Perry Yuan Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 57 ++++++++++++++++++++++++++++++++++-- include/linux/amd-pstate.h | 6 ++++ 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ec6259957d25..59bcdf829c93 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -67,6 +67,7 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; static bool amd_pstate_prefcore = true; +static struct quirk_entry *quirks; /* * AMD Energy Preference Performance (EPP) @@ -111,6 +112,41 @@ static unsigned int epp_values[] = { typedef int (*cppc_mode_transition_fn)(int); +static struct quirk_entry quirk_amd_7k62 = { + .nominal_freq = 2600, + .lowest_freq = 550, +}; + +static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) +{ + /** + * match the broken bios for family 17h processor support CPPC V2 + * broken BIOS lack of nominal_freq and lowest_freq capabilities + * definition in ACPI tables + */ + if (boot_cpu_has(X86_FEATURE_ZEN2)) { + quirks = dmi->driver_data; + pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); + return 1; + } + + return 0; +} + +static const struct dmi_system_id amd_pstate_quirks_table[] __initconst = { + { + .callback = dmi_matched_7k62_bios_bug, + .ident = "AMD EPYC 7K62", + .matches = { + DMI_MATCH(DMI_BIOS_VERSION, "5.14"), + DMI_MATCH(DMI_BIOS_RELEASE, "12/12/2019"), + }, + .driver_data = &quirk_amd_7k62, + }, + {} +}; +MODULE_DEVICE_TABLE(dmi, amd_pstate_quirks_table); + static inline int get_mode_idx_from_str(const char *str, size_t size) { int i; @@ -607,13 +643,19 @@ static void amd_pstate_adjust_perf(unsigned int cpu, static int amd_get_min_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u32 lowest_freq; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; + if (quirks && quirks->lowest_freq) + lowest_freq = quirks->lowest_freq; + else + lowest_freq = cppc_perf.lowest_freq; + /* Switch to khz */ - return cppc_perf.lowest_freq * 1000; + return lowest_freq * 1000; } static int amd_get_max_freq(struct amd_cpudata *cpudata) @@ -642,12 +684,18 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) static int amd_get_nominal_freq(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; + u32 nominal_freq; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - return cppc_perf.nominal_freq; + if (quirks && quirks->nominal_freq) + nominal_freq = quirks->nominal_freq; + else + nominal_freq = cppc_perf.nominal_freq; + + return nominal_freq; } static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) @@ -1685,6 +1733,11 @@ static int __init amd_pstate_init(void) if (cpufreq_get_current_driver()) return -EEXIST; + quirks = NULL; + + /* check if this machine need CPPC quirks */ + dmi_check_system(amd_pstate_quirks_table); + switch (cppc_state) { case AMD_PSTATE_UNDEFINED: /* Disable on the following configs by default: diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index d21838835abd..7b2cbb892fd9 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -124,4 +124,10 @@ static const char * const amd_pstate_mode_string[] = { [AMD_PSTATE_GUIDED] = "guided", NULL, }; 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It can avoid duplicate calls to cppc_get_perf_caps function. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 43 ++++++++++++++---------------------- include/linux/amd-pstate.h | 1 + 2 files changed, 18 insertions(+), 26 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 59bcdf829c93..3877d4ecb5d4 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -330,12 +330,18 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; u32 highest_perf; + struct cppc_perf_caps cppc_perf; + int ret; - int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, + ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; + ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + if (ret) + return ret; + /* For platforms that do not support the preferred core feature, the * highest_pef may be configured with 166 or 255, to avoid max frequency * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as @@ -353,6 +359,9 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->min_limit_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->lowest_freq, cppc_perf.lowest_freq); + WRITE_ONCE(cpudata->nominal_freq, cppc_perf.nominal_freq); + return 0; } @@ -360,8 +369,9 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; u32 highest_perf; + int ret; - int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); + ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; @@ -378,6 +388,8 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); WRITE_ONCE(cpudata->min_limit_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->lowest_freq, cppc_perf.lowest_freq); + WRITE_ONCE(cpudata->nominal_freq, cppc_perf.nominal_freq); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -642,17 +654,12 @@ static void amd_pstate_adjust_perf(unsigned int cpu, static int amd_get_min_freq(struct amd_cpudata *cpudata) { - struct cppc_perf_caps cppc_perf; u32 lowest_freq; - int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); - if (ret) - return ret; - if (quirks && quirks->lowest_freq) lowest_freq = quirks->lowest_freq; else - lowest_freq = cppc_perf.lowest_freq; + lowest_freq = READ_ONCE(cpudata->lowest_freq); /* Switch to khz */ return lowest_freq * 1000; @@ -660,14 +667,9 @@ static int amd_get_min_freq(struct amd_cpudata *cpudata) static int amd_get_max_freq(struct amd_cpudata *cpudata) { - struct cppc_perf_caps cppc_perf; u32 max_perf, max_freq, nominal_freq, nominal_perf; u64 boost_ratio; - int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); - if (ret) - return ret; - nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); @@ -683,36 +685,25 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) static int amd_get_nominal_freq(struct amd_cpudata *cpudata) { - struct cppc_perf_caps cppc_perf; u32 nominal_freq; - int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); - if (ret) - return ret; - if (quirks && quirks->nominal_freq) nominal_freq = quirks->nominal_freq; else - nominal_freq = cppc_perf.nominal_freq; + nominal_freq = READ_ONCE(cpudata->nominal_freq); return nominal_freq; } static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) { - struct cppc_perf_caps cppc_perf; u32 lowest_nonlinear_freq, lowest_nonlinear_perf, nominal_freq, nominal_perf; u64 lowest_nonlinear_ratio; - int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); - if (ret) - return ret; - nominal_freq = READ_ONCE(cpudata->nominal_freq); nominal_perf = READ_ONCE(cpudata->nominal_perf); - - lowest_nonlinear_perf = cppc_perf.lowest_nonlinear_perf; + lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); lowest_nonlinear_ratio = div_u64(lowest_nonlinear_perf << SCHED_CAPACITY_SHIFT, nominal_perf); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 7b2cbb892fd9..1fbbe75c3dcc 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -88,6 +88,7 @@ struct amd_cpudata { u32 min_freq; u32 nominal_freq; u32 lowest_nonlinear_freq; + u32 lowest_freq; struct amd_aperf_mperf cur; struct amd_aperf_mperf prev;