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Wed, 13 Mar 2024 13:27:20 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 814851800D6A; Wed, 13 Mar 2024 14:27:19 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Tom Lendacky , Marcelo Tosatti , Paolo Bonzini , kvm@vger.kernel.org, Gerd Hoffmann Subject: [PATCH v3 1/3] [debug] log kvm supported cpuid Date: Wed, 13 Mar 2024 14:27:17 +0100 Message-ID: <20240313132719.939417-2-kraxel@redhat.com> In-Reply-To: <20240313132719.939417-1-kraxel@redhat.com> References: <20240313132719.939417-1-kraxel@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 --- target/i386/kvm/kvm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e68cbe929302..2f5e3b9febf9 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -276,6 +276,20 @@ static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) exit(1); } } + + { + int i; + + for (i = 0; i < cpuid->nent; i++) { + fprintf(stderr, "cpuid: %8x/%d - %8x %8x %8x %8x\n", + cpuid->entries[i].function, + cpuid->entries[i].index, + cpuid->entries[i].eax, + cpuid->entries[i].ebx, + cpuid->entries[i].ecx, + cpuid->entries[i].edx); + } + } return cpuid; } From patchwork Wed Mar 13 13:27:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gerd Hoffmann X-Patchwork-Id: 13591409 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53A463E49D for ; Wed, 13 Mar 2024 13:27:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710336450; cv=none; b=BegyICchn6FRjBr43jM/Il2LQiFceWiT2VbpPWICHuxZbrDYX1fUApabm2XN2KBbZ+k6aY/3otsUx163FiF0eMq7rNjBea1fDGe8iLsJUpdZYBUMO4Ka//OnpZxmmIcxzblk4e8iheysnn8oXXeyyh6ebnmxUbTNBw+B+yf8BIY= ARC-Message-Signature: i=1; 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Wed, 13 Mar 2024 13:27:22 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.160]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 532D740C6CB2; Wed, 13 Mar 2024 13:27:22 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 9D2931801494; Wed, 13 Mar 2024 14:27:19 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Tom Lendacky , Marcelo Tosatti , Paolo Bonzini , kvm@vger.kernel.org, Gerd Hoffmann Subject: [PATCH v3 2/3] kvm: add support for guest physical bits Date: Wed, 13 Mar 2024 14:27:18 +0100 Message-ID: <20240313132719.939417-3-kraxel@redhat.com> In-Reply-To: <20240313132719.939417-1-kraxel@redhat.com> References: <20240313132719.939417-1-kraxel@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.2 Query kvm for supported guest physical address bits, in cpuid function 80000008, eax[23:16]. Usually this is identical to host physical address bits. With NPT or EPT being used this might be restricted to 48 (max 4-level paging address space size) even if the host cpu supports more physical address bits. When set pass this to the guest, using cpuid too. Guest firmware can use this to figure how big the usable guest physical address space is, so PCI bar mapping are actually reachable. Signed-off-by: Gerd Hoffmann --- target/i386/cpu.h | 1 + target/i386/cpu.c | 1 + target/i386/kvm/kvm-cpu.c | 32 +++++++++++++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 952174bb6f52..d427218827f6 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2026,6 +2026,7 @@ struct ArchCPU { /* Number of physical address bits supported */ uint32_t phys_bits; + uint32_t guest_phys_bits; /* in order to simplify APIC support, we leave this pointer to the user */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9a210d8d9290..c88c895a5b3e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6570,6 +6570,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { /* 64 bit processor */ *eax |= (cpu_x86_virtual_addr_width(env) << 8); + *eax |= (cpu->guest_phys_bits << 16); } *ebx = env->features[FEAT_8000_0008_EBX]; if (cs->nr_cores * cs->nr_threads > 1) { diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 9c791b7b0520..a2b7bfaeadf8 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -18,10 +18,36 @@ #include "kvm_i386.h" #include "hw/core/accel-cpu.h" +static void kvm_set_guest_phys_bits(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + uint32_t eax, guest_phys_bits; + + if (!cpu->host_phys_bits) { + return; + } + + eax = kvm_arch_get_supported_cpuid(cs->kvm_state, 0x80000008, 0, R_EAX); + guest_phys_bits = (eax >> 16) & 0xff; + if (!guest_phys_bits) { + return; + } + + if (cpu->guest_phys_bits == 0 || + cpu->guest_phys_bits > guest_phys_bits) { + cpu->guest_phys_bits = guest_phys_bits; + } + + if (cpu->guest_phys_bits > cpu->host_phys_bits_limit) { + cpu->guest_phys_bits = cpu->host_phys_bits_limit; + } +} + static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) { X86CPU *cpu = X86_CPU(cs); CPUX86State *env = &cpu->env; + bool ret; /* * The realize order is important, since x86_cpu_realize() checks if @@ -50,7 +76,11 @@ static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) MSR_IA32_UCODE_REV); } } - return host_cpu_realizefn(cs, errp); + ret = host_cpu_realizefn(cs, errp); + + kvm_set_guest_phys_bits(cs); + + return ret; } static bool lmce_supported(void) From patchwork Wed Mar 13 13:27:19 2024 Content-Type: text/plain; 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Wed, 13 Mar 2024 13:27:22 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id AA0851801A91; Wed, 13 Mar 2024 14:27:19 +0100 (CET) From: Gerd Hoffmann To: qemu-devel@nongnu.org Cc: Tom Lendacky , Marcelo Tosatti , Paolo Bonzini , kvm@vger.kernel.org, Gerd Hoffmann Subject: [PATCH v3 3/3] target/i386: add guest-phys-bits cpu property Date: Wed, 13 Mar 2024 14:27:19 +0100 Message-ID: <20240313132719.939417-4-kraxel@redhat.com> In-Reply-To: <20240313132719.939417-1-kraxel@redhat.com> References: <20240313132719.939417-1-kraxel@redhat.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.1 Allows to set guest-phys-bits (cpuid leaf 80000008, eax[23:16]) via -cpu $model,guest-phys-bits=$nr. Signed-off-by: Gerd Hoffmann --- target/i386/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c88c895a5b3e..e0d73b6ec654 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7380,6 +7380,14 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) if (cpu->phys_bits == 0) { cpu->phys_bits = TCG_PHYS_ADDR_BITS; } + if (cpu->guest_phys_bits && + (cpu->guest_phys_bits > cpu->phys_bits || + cpu->guest_phys_bits < 32)) { + error_setg(errp, "guest-phys-bits should be between 32 and %u " + " (but is %u)", + cpu->phys_bits, cpu->guest_phys_bits); + return; + } } else { /* For 32 bit systems don't use the user set value, but keep * phys_bits consistent with what we tell the guest. @@ -7388,6 +7396,10 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) error_setg(errp, "phys-bits is not user-configurable in 32 bit"); return; } + if (cpu->guest_phys_bits != 0) { + error_setg(errp, "guest-phys-bits is not user-configurable in 32 bit"); + return; + } if (env->features[FEAT_1_EDX] & (CPUID_PSE36 | CPUID_PAE)) { cpu->phys_bits = 36; @@ -7888,6 +7900,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), + DEFINE_PROP_UINT32("guest-phys-bits", X86CPU, guest_phys_bits, 0), DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),