From patchwork Thu Mar 14 00:02:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591987 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E95D54C96 for ; Thu, 14 Mar 2024 00:02:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374542; cv=none; b=egndeoshpupAHqciYi+5S0+GrJSD8I8XIlwV/72EEY3W3jc9K8ORYql1teEvqC7Cn1iLkRYmcjIrIORgD3yenaDlAj7OazAI1/A7YL8IPQDk0+gG3bYaI1en/q4AulJ+Ic/QiNORCJGo6ugfAFVahfnYv3UK/prU9Cy+NSsqqC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374542; c=relaxed/simple; bh=0syM6MsQMypRFGFHFNL5wKa4GlrUlRZdqzFcwD7jVoo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HjiuaTGQJ4Ta30xwTQiWn8nDXUMcIMJXkWP0TUkhoa0e3fN59TUyCAaHJGQRl//x78hR1QTRu2TLeg7w1mEDoQ02CWaj/7YT1S1zqG1RnDOnWOqBxzlLXNanTgp2w8wZAryL28vlcOyRRtFtS/dJRhWrtKby2WeE1FPlCwvNQSA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rcLSPhmW; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rcLSPhmW" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-513a6416058so692542e87.1 for ; Wed, 13 Mar 2024 17:02:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374539; x=1710979339; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gj3lW7SJBVxAjQYikbiu5IXfqO7a39lu/HpAURIlMqg=; b=rcLSPhmWwObEZk+XA3leupFMQtIHVQw1Bih0gtKjsIQwWEueB9BNQahD/OujG7xaop S3AJ+c4ZC4O+gCHEI8oorBnUyA/LauKSPiICQRJ3A4Y0wTK4Oho0w26BAx1epb6gFsSL A3u1tFgvxP/LvgAOTY5SV8YRx2CsiWIL4EagiSDlQc+VUCwFjX2d3azT6VXF3k63tyta d58NBXXic7MLA6noG9YNIdsGQmPDMbvqVb+tPR9+JoXrO5pUmJDGLwY5SZUp5jikaCqw psTVY368mN0gvT3JcR9UdK6GazuhIKwWSKQpQveJHTSHyh5ue/aKPygZo5y39CZCPzeP UIPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374539; x=1710979339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gj3lW7SJBVxAjQYikbiu5IXfqO7a39lu/HpAURIlMqg=; b=xSdV3d0FGEPBUo78oZGpEuPci4OFlguFBZaYsMGKIS1aD325vPxF5z6ZuQfoUa0CJd 6DhujaSWL+8LGbmPDIGMaacDnwVtmZTuhNWdEGg0xEEtK8/QiRt7nLR1zdIfglsKZ+p4 R+SS1NOs+gM+A62HGk0HtyxxJLOhjwFaa/mf6XfM6cYachprCaHRYSANyqDt5EZVD+sa Yf2/j/NbMLIkm9q+8nP98A2c3brU4kzR4IbcYULVZHqQCJBSoLuhvQfNqLiotT9aNYFQ uApTLeYaGFFhZIku4CLRshhdMYr7KgYi8h682IggN9v8Dk/fPsepVtslOWIcPp4R0nH3 I41A== X-Forwarded-Encrypted: i=1; AJvYcCUIfXUbzae+GLremQJeqsA72tJIoXarsm5PGljM3a2F9GRL4B0IOS1cNS5SArxADGopZzch1zJ3DX4b512zfR03xjzruBi58jHLoJtu4A== X-Gm-Message-State: AOJu0Yw+dmtSzZmek1ILgGA1kVM++MsDHyEY4S4bJ7c6QBVe/jFb0XBX D05zCS06og6Edd79nPrSlVwzRYIlwNkvn3a7alwsAl+iDl+yseWfajcCF2LE8ig= X-Google-Smtp-Source: AGHT+IHvIoBT0iRAcOZiJAOvlSC6Oas+0qwTlsWhsEbNCVnMb3zY79S6PeoK2c0PRRLO+zTIkxwkcw== X-Received: by 2002:ac2:54ad:0:b0:513:cab1:354b with SMTP id w13-20020ac254ad000000b00513cab1354bmr37991lfk.41.1710374539020; Wed, 13 Mar 2024 17:02:19 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:18 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 01/13] drm/msm/dpu: take plane rotation into account for wide planes Date: Thu, 14 Mar 2024 02:02:04 +0200 Message-Id: <20240314000216.392549-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Take into account the plane rotation and flipping when calculating src positions for the wide plane parts. This is not an issue yet, because rotation is only supported for the UBWC planes and wide UBWC planes are rejected anyway because in parallel multirect case only the half of the usual width is supported for tiled formats. However it's better to fix this now rather than stumbling upon it later. Fixes: 80e8ae3b38ab ("drm/msm/dpu: add support for wide planes") Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index ff975ad51145..44f35ae09ba6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -862,6 +862,10 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; + drm_rect_rotate(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { /* @@ -911,6 +915,14 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; } + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if (r_pipe->sspp) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) return ret; From patchwork Thu Mar 14 00:02:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591988 Received: from mail-lf1-f54.google.com (mail-lf1-f54.google.com [209.85.167.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8990F5256 for ; Thu, 14 Mar 2024 00:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374543; cv=none; b=usDs6pMK9qJrN0ogqZiGPtKtxIkM/MRGFnd1HT+IbzmrxU3InAetQTlkyw8Pure5QxcZdZOHjSkz8DEMmzACGgS4/iRPtmdmwJgJITc4/Rb2710bhWwnUFavq8Sl3igHkrEi3ke39ZxxXiPQeFPhp5qPwxTC3IV07uFqThUBO+c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374543; c=relaxed/simple; bh=XCBs9m2CvzQ6fJy7OLc41Y94osXveFW+L7i+WiusLso=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ACNINNdmimBW52OivzaH7KaXLoW9l8M1BtbO6tl1EapMZbeHQ0Y47BWxlMMi5M01grrOx0rSbuu5ZbG2ZUPGe7ReSuTJiLPQQLd7cyUBwBuO2nl7ldwHukO+bo4IyUVflGFnUtVIVz6PTVTS/4UhlM2lecVlheZhOjaXlKAhovM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Ku+ZbwC6; arc=none smtp.client-ip=209.85.167.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ku+ZbwC6" Received: by mail-lf1-f54.google.com with SMTP id 2adb3069b0e04-513a6416058so692550e87.1 for ; Wed, 13 Mar 2024 17:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374539; x=1710979339; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dRoAz+CmhNjrfdAdzTuoudY5YtPxIo6KTnpc/4/7Msk=; b=Ku+ZbwC6hPk2sCtvNjTLEUIGMadsh8H1KRW1mMoq3mRES5I+uI+w4MsmOaEemZeOy4 OjTF6oisA4/fc8w23P16Gu/CfkrYlkHaPEqjUUq5QyJL4ukUiB0xXJbwsxFeaz+jNUVv /O2r+zw2z9fg1Nk9MDq1XE9C2GQlXSE2mWPhywJD24woECZwXXJQf+8BwhzBDZ7QsYLn 2UDDcPykP3DCrDPQuJfPmTrk4GW4i1hYpFlltl95S1xqwnjerij6zSfhgKWJWsWRofD4 /ee29aAsEaOZZkzKigL1lFwspKJciFffKsB4AW6AhvoFigYb4+v2Je8SjhCPvQQ2SYbc MK9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374539; x=1710979339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dRoAz+CmhNjrfdAdzTuoudY5YtPxIo6KTnpc/4/7Msk=; b=Dlr+cRmve96bwHo5IJ7PbUMldLZHI14KTB9qjv5R4JTnKmoXrr58WWuc/zId+2PVdu NSvBEFF73wHVSiNv2TODUQgbgKRmya4JDQEBZer+TU6POcnfVO22rSoCv4bsaRsOhdV9 QwapMo1dPDLsUcqJ2b3OaTPu18nfchnt6Bjqw5VK3ZYNZuPIpCTPsFnblcZ20LGRbF4n cOxESaoY31sPyBIhf07sZZi0SmSfY0HUVmIwsfGa0SPGXbbCgTHtgoEHqYGC6S+5ui/I vq7iehS0nkqQM8AC7E1nKLPGhpqJwvLfuSedVSrTdBcumZmEEKN4VNgvgkZfZCv0Jcjp +BdQ== X-Forwarded-Encrypted: i=1; AJvYcCVv7Hz6zCMKmmPSjdH2inLR0lHMplGurhcfuqN+fZWR7FNjN9y5pZpo0KVYZ+Gi0n++vi2pZAMHHGBAXrHpkb2rSM0OPYwyUXIf2JhAjg== X-Gm-Message-State: AOJu0YwHxYjjbpSFtvgNowhufOLUvFRM/K12UB80KkVQSOWZBgq+6kLH uf31CbxIlYSxTzn3nOPdaLDFZsxDiy1iEczFXKJ+XdhG0rLEXlNdfcI+mfuC5lI= X-Google-Smtp-Source: AGHT+IFof1jodr968Rtad36DFoDLNMwGgycfHRg3fwZPFnqXAtPT2DoN1hDgJKoSQ6oe2hRjTrQBmw== X-Received: by 2002:a05:6512:54e:b0:513:c17b:1426 with SMTP id h14-20020a056512054e00b00513c17b1426mr51650lfl.11.1710374539755; Wed, 13 Mar 2024 17:02:19 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:19 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 02/13] drm/msm/dpu: use drm_rect_fp_to_int() Date: Thu, 14 Mar 2024 02:02:05 +0200 Message-Id: <20240314000216.392549-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use the drm_rect_fp_to_int() helper instead of using the hand-written code. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 44f35ae09ba6..9c52fe3c0261 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -837,13 +837,8 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } - pipe_cfg->src_rect = new_plane_state->src; - /* state->src is 16.16, src_rect is not */ - pipe_cfg->src_rect.x1 >>= 16; - pipe_cfg->src_rect.x2 >>= 16; - pipe_cfg->src_rect.y1 >>= 16; - pipe_cfg->src_rect.y2 >>= 16; + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); pipe_cfg->dst_rect = new_plane_state->dst; From patchwork Thu Mar 14 00:02:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591989 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E3115CBD for ; Thu, 14 Mar 2024 00:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374544; cv=none; b=PPUd6rS+MKXcIO1qSZavV64jS3Y4JGJwmxwdlbWTzN1uh8mBMOhrBQi1LdAUVt9rG5hUBCTtncpsr+LGrrdV/NDuPiYQWkGDmhrM60EyIwf57x98aKVvSFzk5KIyuTd8GY9ez5ZHWCs1p1yIK1hOZx0ZWHv9Z7v1h0NRUTGsT30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374544; c=relaxed/simple; bh=+3QJuMwow+uAlv7JD46FjiD1VCz+STvRq5i3ATCqbhQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GUOZh47MZBEY3LXZl/6VQ9WJsX1lNh7wtLFe7A25Q/IjsQHPuk0s8QrvuZ1MqpWZFxoEQ+7Fkz/ksiW/hui+z05cptOWvb516R8dMx2cMAyeUWsMx2Of+kpgJvGSiPRZo67uHCS7O0SIVq3nN6OpktUNI2WPykhdOhIEE6vTzv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=NzELtxjK; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NzELtxjK" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-513173e8191so642637e87.1 for ; Wed, 13 Mar 2024 17:02:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374540; x=1710979340; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/XNr6KKW37IazWI0ZJpFV5pkj9zPRMLRzsCadh2vfcc=; b=NzELtxjKm1ULRYMl+6R8eUVh9/L5SIWmOkVeMECK1BxWjqaahWccMKlrCyJvxTI2Li hsy5T1etm/3c7tNUMdqS6ZR2Lg6FMBntKfWy2FtBSATARcUaVqf3OY5ryjmPsgElpDZI /3DrybYUS9TF4BbkeiDXGMsE68z9BPVBytyEyw/FWqJjVclBfgbU8rfX5yhsiB8uD9hh QYkEHU2D22KCl/s2C6kjip6HhkEfxMGfl8Po47JUVDSqj7G3ZjUK+HZ8EIhJsjTRNpkG 8134m0CgQh4jR1pVH2xNV5UmhWPBqAkCsyVtMHSvGnTcDGJKm88Qc8LOXKgEU6YWstgW GBOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374540; x=1710979340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/XNr6KKW37IazWI0ZJpFV5pkj9zPRMLRzsCadh2vfcc=; b=e/kkFhxJVq+We617a7neU2e7g0xuvf8gRa/tuOaHM15zZcAP3a8VTcnVis0Mvzm5q1 F/5JirWZpChKzPkDv+qSbuGQsmJUE0qQ95E0LKv/5Rz+yZduqCJwoCJoO3mHlV5KNgTh r5l/aXDJjAl5TOcVqPkXEcXNx1+TPrFdTpHecCWxZSFsYoEZZQ9iy2y/ZbZo3DhoLdkA 3rK6zba/Ja2KTxDrhWD/tktJXiLXjVR2Ytp7JoSpXmf22yEu2y9+vXney7cRtD5sUG+v F0Y1R6tC4osUdyRtWDyv2x546jx8SSRQmIzH5NJnRzUPLMcPcbCelEWi8QqHej1m700H jD7w== X-Forwarded-Encrypted: i=1; AJvYcCVj7i+jOK6P5xy6T7YCJZxS77z9i1PafCU0sKZJ57Is5FSpZWXSPRuERorMBVxynQ0M+m3WvzMb1dehes8pEo3KVvh8Z1vGpRzO+fcBtA== X-Gm-Message-State: AOJu0YzlxsR1fR/RDczmk5tCNq7TZGJndffn9ys4aXbBWMOLqVLDuqaa aYnsKsxgp8+DL9ILY8yNYbYrkWgecfl+Bg6Arwt7QwuC+O0GM7RsZXl7pO7Z+48= X-Google-Smtp-Source: AGHT+IGMZ6cQE2t+Zj2q16bpR1SktpXUJO2yjIiNo+IjHXUThHSVFo6j+i9y23ceYGZIyS/MkUo/RA== X-Received: by 2002:ac2:5b45:0:b0:513:c429:c04e with SMTP id i5-20020ac25b45000000b00513c429c04emr38800lfp.33.1710374540483; Wed, 13 Mar 2024 17:02:20 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:20 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 03/13] drm/msm/dpu: move pstate->pipe initialization to dpu_plane_atomic_check Date: Thu, 14 Mar 2024 02:02:06 +0200 Message-Id: <20240314000216.392549-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 In preparation for virtualized planes support, move pstate->pipe initialization from dpu_plane_reset() to dpu_plane_atomic_check(). In case of virtual planes the plane's pipe will not be known up to the point of atomic_check() callback. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 26 +++++++++++------------ 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 9c52fe3c0261..70d6a8989e1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -795,6 +795,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); struct dpu_sw_pipe *pipe = &pstate->pipe; struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; const struct drm_crtc_state *crtc_state = NULL; @@ -805,13 +806,22 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, uint32_t max_linewidth; unsigned int rotation; uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps = pstate->pipe.sspp->cap; - const struct dpu_sspp_sub_blks *sblk = pstate->pipe.sspp->cap->sblk; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; + + if (!pipe->sspp) + return -EINVAL; + + pipe_hw_caps = pipe->sspp->cap; + sblk = pipe->sspp->cap->sblk; + min_scale = FRAC_16_16(1, sblk->maxupscale); ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, @@ -828,7 +838,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - r_pipe->sspp = NULL; pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { @@ -1292,7 +1301,6 @@ static void dpu_plane_reset(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1314,16 +1322,6 @@ static void dpu_plane_reset(struct drm_plane *plane) return; } - /* - * Set the SSPP here until we have proper virtualized DPU planes. - * This is the place where the state is allocated, so fill it fully. - */ - pstate->pipe.sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - pstate->pipe.multirect_index = DPU_SSPP_RECT_SOLO; - pstate->pipe.multirect_mode = DPU_SSPP_MULTIRECT_NONE; - - pstate->r_pipe.sspp = NULL; - __drm_atomic_helper_plane_reset(plane, &pstate->base); } From patchwork Thu Mar 14 00:02:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591990 Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F31618BF8 for ; Thu, 14 Mar 2024 00:02:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374544; cv=none; b=sDRdCgLiPOTanjYhxi1rCiGt1LPUHg8XPDRXLIWbdpCBMluR4tr3qgf+F2GIgYhU3uNGtpPSbc+hSke3OrLOlblkUXZvwOaW4QKsXuzxgbCO+KC32KWQ7za09q880z9I9wJ35ao3kjQVHcKwhRqDx/Z0R42EqTUiojxHqxQVArc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374544; c=relaxed/simple; bh=KNldNFyPEEfzuAEtH1cnTT4X5jlP7dQNiCH2aZ9Uhok=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZO8iUqDPheC3UV87pxhNb2s8F6dmy34+Iji2xMdSr7cZpNVVlZ/nfO5P3jGi3BRl+ijYJAIeqUI/SpeEtTnPEZdWAtxQrcsh/K5fC2fvCJWNJ8zggt/6wxPLlkCQe7G3vUTEpc5ZZiKHTksX8VuJD1DtI++TlkMPEGJMSRGhVyk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=AMOn/niR; arc=none smtp.client-ip=209.85.167.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="AMOn/niR" Received: by mail-lf1-f51.google.com with SMTP id 2adb3069b0e04-5101cd91017so696719e87.2 for ; Wed, 13 Mar 2024 17:02:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374541; x=1710979341; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=clvqfuDuLHhOMDUpN28VXezisf/pvnw+VhoyO8COXfI=; b=AMOn/niRmZmk4FWG9D/oBEId2qt0g1H/zhHAEqvJUSS6Lqx0ml8jNiww2hD3u2M/c2 7d45K8I5zku+AwjdPiGQyP+9NOwscdIZ5hoI2N6dML1DOWijY0Oxk95BdiLgk6aDpJjv 28GC45xyxFK5ddO3rHziOlerjLJw/0lyP3QihQxM2wVGiiTrCt0x2tXL80up1l7hrA+o QNuKBaEkMGKZr8wUz9ugvCqGu8xHaz3Vwaq9xMc7cV0zLuhSOBzzMXHXVTbQ4XdVSqZF WfJ8yEtbchtz3fslxrWH14MuboMkBmyPMg89PYu0SZNkcTFpGJH31yBxAru8bZl+5E8z PYOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374541; x=1710979341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=clvqfuDuLHhOMDUpN28VXezisf/pvnw+VhoyO8COXfI=; b=QxEIca7yCIjff0FjJzOL3r/36Efr7y/UDgnT8bBu6YEjmibjmL6VuL3xxH0Ql/a9Ry OqydxAMk1DcMT7nfhi26bRHezuXtP3OEAMAIhV8qz8ueFW8hZojd+gYiMR8ynP81T//S tEaYMNRr4eRqgfDs2MnNmV7ttlxGAsy/mMIrwcA7BctNAw3YTh/Wr9vKyKT3HZBhon0z kFVkkL1/JLl4etepNOytA8QuLg+u8oN7Uv8IM4OLCKnJ7YCw/OmVW/wE7yTMCTab7jt0 CvzEtqkwHF20+hliiShZtCRU4rfr6t/y5/m4PzTLNe1m1qBCTykbjQa3VR+UXYonsb0G pO0w== X-Forwarded-Encrypted: i=1; AJvYcCXERMBzp4oD1XkxkZh9VhrEjHumBNufgQxEwSLckmBOR1iS/ND54BXG2PhjIhGZhsORhqPG/7IhMof146nH/JbJJKxPlqKZvgoq7pSvQw== X-Gm-Message-State: AOJu0YyRE1X0j4dL4P5/7i7vWJ/9kIdM6TxIzjmu5PcUQnAAj7Gleej7 RQQmg+xY0qLLsU/V9T54IJRgyWziXU35X4SHFVprPXDnpzIS4pTDp61RZaPiUaw= X-Google-Smtp-Source: AGHT+IGDNT6i0DXVmxw8bW/VTemWoJzET4Y18lYpr6RE06EgwiFAMctoBH25D0HuRmKi+lnoQc0Fkg== X-Received: by 2002:a19:ca51:0:b0:512:bf43:d786 with SMTP id h17-20020a19ca51000000b00512bf43d786mr55047lfj.10.1710374541287; Wed, 13 Mar 2024 17:02:21 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:20 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 04/13] drm/msm/dpu: drop virt_formats from SSPP subblock configuration Date: Thu, 14 Mar 2024 02:02:07 +0200 Message-Id: <20240314000216.392549-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The virt_formats / virt_num_formats are not used by the current driver and are not going to be used in future since formats for virtual planes are handled in a different way, by forbidding unsupported combinations during atomic_check. Drop those fields now. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ---- 2 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index f2b6eac7601d..a2e4832aa25d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -289,8 +289,6 @@ static const u32 wb2_formats_rgb_yuv[] = { .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ - .virt_format_list = plane_formats, \ - .virt_num_formats = ARRAY_SIZE(plane_formats), \ .rotation_cfg = NULL, \ } @@ -305,8 +303,6 @@ static const u32 wb2_formats_rgb_yuv[] = { .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ - .virt_format_list = plane_formats, \ - .virt_num_formats = ARRAY_SIZE(plane_formats), \ .rotation_cfg = rot_cfg, \ } @@ -316,8 +312,6 @@ static const u32 wb2_formats_rgb_yuv[] = { .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ - .virt_format_list = plane_formats, \ - .virt_num_formats = ARRAY_SIZE(plane_formats), \ } #define _DMA_SBLK() \ @@ -326,8 +320,6 @@ static const u32 wb2_formats_rgb_yuv[] = { .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ - .virt_format_list = plane_formats, \ - .virt_num_formats = ARRAY_SIZE(plane_formats), \ } static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index d1aef778340b..addf8e932d12 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -372,8 +372,6 @@ struct dpu_caps { * @csc_blk: * @format_list: Pointer to list of supported formats * @num_formats: Number of supported formats - * @virt_format_list: Pointer to list of supported formats for virtual planes - * @virt_num_formats: Number of supported formats for virtual planes * @dpu_rotation_cfg: inline rotation configuration */ struct dpu_sspp_sub_blks { @@ -386,8 +384,6 @@ struct dpu_sspp_sub_blks { const u32 *format_list; u32 num_formats; - const u32 *virt_format_list; - u32 virt_num_formats; const struct dpu_rotation_cfg *rotation_cfg; }; From patchwork Thu Mar 14 00:02:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591992 Received: from mail-lj1-f179.google.com (mail-lj1-f179.google.com [209.85.208.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07E72947B for ; Thu, 14 Mar 2024 00:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374546; cv=none; b=maRW/TfaKzp4xjrD8cyg79bO8pBvMrDIvm3S47JTcWsm+lLleOVYgAUGtlAwclclIOzlK+F71l6mY9ApFesE/HauOFJRj0ZfoTNNoO3FJjNX1DR6maniWvkD2hx2wdhaW0IrHyhXYq0v5BKs+hshHHttmXUl+tGJxZz7lsMcftk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374546; c=relaxed/simple; bh=oGhm2AfFpbwDUwQXJd23O5OpDvnVkCsnioPMvs7UQWw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fZ6vZKkrhKNu+ep3rVMhEr0GE2Oobq8LbivCONZaiNrqiRFFCZnZF3etKVEQegWsh9YMqNw5iwU9YCz0Z4c1NkIUISK41Tiy/VR6yZ1SHjYsEg/1t027iUEKIfBvhf9NBN78k8PiN6hv4DnurANf+KKs4C3J8ccAQG4p1OYySbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=bol4sS23; arc=none smtp.client-ip=209.85.208.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="bol4sS23" Received: by mail-lj1-f179.google.com with SMTP id 38308e7fff4ca-2d109e82bd0so4223821fa.3 for ; Wed, 13 Mar 2024 17:02:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374542; x=1710979342; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=omhQlSoxtqwZ2DMzUczrlWHRB9OlkJVlUrZG2hp78ts=; b=bol4sS23TlCee2NVorbumYlVFNCnVjhR/+8lOSCxWYtPagk0rv66dFftTAccY17MV/ r2fNL745fyC55RKCmFpKRRv7NrO+scFD1f1KoYYbYhLzGTYnS4WBnyVXdgH2lNskrKX+ rxxy6iKpdzwvdsdRfc6MzfYQwsKEMy2vUp493WPNg571JhuXKdM/CLblR9P0lBfaWTQQ n03CZmcqIH43Hti4XEppSFNLhHv4SG30U/MMRZ50xCDrPqbwBvKJzSHHWqdTF6O3FoFM EkbUEEIJWqWsij0fZF7Fw8w7mPGv1h1x20ZKxCZgL4SmBFx7agK0I1xWlEs0923DpIY9 t6jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374542; x=1710979342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=omhQlSoxtqwZ2DMzUczrlWHRB9OlkJVlUrZG2hp78ts=; b=Va882d7YKt6Yqu78brX446//ufkLcp6skqKaWhZcM2vHkSJZ7fGqBDgBF1JAtuw4q3 5tsH9k9Go6xLmV4dJznq1cHVepfgVn+Kq0zLJhxTiTf6M5fQxo5dTG2UGzyjCBzVgw1n 0DW+J8XaNYkE/7gUG6EYhGprYi+9GQtuaclvsJxIid9P98omL5NB4FDHeMzN6LE+aV9i 9qVuCMdXfUixhQZb0ghf+USzcLKEb0MY7PXhhwmhOmbxWhz+qEKOvIy6HsYZjzYeVUQT Wt1AYFWtppDZySUZysJS8vRZ/EHTZWhp3u3HnTF8wPXNkE8sl189Pa7KAR8AoEBQN7sZ zsNg== X-Forwarded-Encrypted: i=1; AJvYcCUMQIk/B3wvSjkh1Ix6sGZQ7ClVs9bo0IU5Tyu3sv05YtfpW44eCPCI+QMjrg3H0f5TbqReTsJDRMKUk/sxVVCN6mnxM8jwys0y5EZPMA== X-Gm-Message-State: AOJu0YwomN24wyvKkFUwvrG4kKqhRJ1A4Jt2ikd8DFiBc3IaZ38ny7WD 2fVxQm574F0ERKTb73fE6PYhh8+QmG/dYNqMbdTMhPlRwmqSzfjn3r665pCFOk4= X-Google-Smtp-Source: AGHT+IFaWhVXOZSe75zGW3/qdv3Rp6jkv+9SmxpEyBltlIqwlLMBx+Ebzj6Tb8KVpz8Fk69lhkR/0A== X-Received: by 2002:ac2:5b9a:0:b0:513:c9a6:46ce with SMTP id o26-20020ac25b9a000000b00513c9a646cemr51945lfn.9.1710374542109; Wed, 13 Mar 2024 17:02:22 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:21 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 05/13] drm/msm/dpu: move scaling limitations out of the hw_catalog Date: Thu, 14 Mar 2024 02:02:08 +0200 Message-Id: <20240314000216.392549-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Max upscale / downscale factors are constant between platforms. In preparation to adding support for virtual planes and allocating SSPP blocks on demand move max scaling factors out of the HW catalog and handle them in the dpu_plane directly. If any of the scaling blocks gets different limitations, this will have to be handled separately, after the plane refactoring. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 ------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 +++++++++++++--- 3 files changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index a2e4832aa25d..47fd8baf53e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -113,10 +113,6 @@ #define MAX_HORZ_DECIMATION 4 #define MAX_VERT_DECIMATION 4 -#define MAX_UPSCALE_RATIO 20 -#define MAX_DOWNSCALE_RATIO 4 -#define SSPP_UNITY_SCALE 1 - #define STRCAT(X, Y) (X Y) static const uint32_t plane_formats[] = { @@ -280,8 +276,6 @@ static const u32 wb2_formats_rgb_yuv[] = { /* SSPP common configuration */ #define _VIG_SBLK(scaler_ver) \ { \ - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ - .maxupscale = MAX_UPSCALE_RATIO, \ .scaler_blk = {.name = "scaler", \ .version = scaler_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -294,8 +288,6 @@ static const u32 wb2_formats_rgb_yuv[] = { #define _VIG_SBLK_ROT(scaler_ver, rot_cfg) \ { \ - .maxdwnscale = MAX_DOWNSCALE_RATIO, \ - .maxupscale = MAX_UPSCALE_RATIO, \ .scaler_blk = {.name = "scaler", \ .version = scaler_ver, \ .base = 0xa00, .len = 0xa0,}, \ @@ -308,16 +300,12 @@ static const u32 wb2_formats_rgb_yuv[] = { #define _VIG_SBLK_NOSCALE() \ { \ - .maxdwnscale = SSPP_UNITY_SCALE, \ - .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats_yuv, \ .num_formats = ARRAY_SIZE(plane_formats_yuv), \ } #define _DMA_SBLK() \ { \ - .maxdwnscale = SSPP_UNITY_SCALE, \ - .maxupscale = SSPP_UNITY_SCALE, \ .format_list = plane_formats, \ .num_formats = ARRAY_SIZE(plane_formats), \ } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index addf8e932d12..fc7da6e1feeb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -364,8 +364,6 @@ struct dpu_caps { /** * struct dpu_sspp_sub_blks : SSPP sub-blocks * common: Pointer to common configurations shared by sub blocks - * @maxdwnscale: max downscale ratio supported(without DECIMATION) - * @maxupscale: maxupscale ratio supported * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @qseed_ver: qseed version * @scaler_blk: @@ -375,8 +373,6 @@ struct dpu_caps { * @dpu_rotation_cfg: inline rotation configuration */ struct dpu_sspp_sub_blks { - u32 maxdwnscale; - u32 maxupscale; u32 max_per_pipe_bw; u32 qseed_ver; struct dpu_scaler_blk scaler_blk; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 70d6a8989e1a..6360052523b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -785,12 +785,15 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return 0; } +#define MAX_UPSCALE_RATIO 20 +#define MAX_DOWNSCALE_RATIO 4 + static int dpu_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); - int ret = 0, min_scale; + int ret = 0, min_scale, max_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; @@ -822,10 +825,17 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, pipe_hw_caps = pipe->sspp->cap; sblk = pipe->sspp->cap->sblk; - min_scale = FRAC_16_16(1, sblk->maxupscale); + if (sblk->scaler_blk.len) { + min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); + max_scale = MAX_DOWNSCALE_RATIO << 16; + } else { + min_scale = 1 << 16; + max_scale = 1 << 16; + } + ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, - sblk->maxdwnscale << 16, + max_scale, true, true); if (ret) { DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret); From patchwork Thu Mar 14 00:02:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591991 Received: from mail-lf1-f52.google.com (mail-lf1-f52.google.com [209.85.167.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D75A3946F for ; Thu, 14 Mar 2024 00:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374546; cv=none; b=WJ4Z/Mm7vEzuttdB6h8oTqYr3adfmioovbIGsu9Uw4jgL2JWdLXhvMnarFHtsY/s/fNZUiDwGPzYnpkRFU1ZrW/cEKGLoC14UJkGhXcCGbIxpyfWM3Jnu6EL60CV0aVNjkYuDe0jiUeR51mrq7M0EKS149IdKwvM8aJ4L78ZzZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374546; c=relaxed/simple; bh=3GY7qKjRqJifsf7UWPXIr+wDQO1rzmwi27+F2JI66kk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a5sYTocDELsK+4FLLL4CmvognRXzMwT3Mcw2SnCQjiKrJWYc6OWXAqalkQKEp3fP+OUtabG/3d7rTU3y/HvldS5Z5DWgJPY8paE98M0yJrrjdARYCub9qp1/r+AyerdDOd1SR0R1ipQ1MpLOA0Mfdj58eOPUkNMa1dlN+5Z0jik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=h9QDkMRE; arc=none smtp.client-ip=209.85.167.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="h9QDkMRE" Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-513c53ed3d8so602911e87.3 for ; Wed, 13 Mar 2024 17:02:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374543; x=1710979343; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zbW5IRvzlbg37aGOBqwcmdzmZ6eMhDw8NOLguxq0OBQ=; b=h9QDkMREFWeLFZsLWxaQMJFwtbtGNjIAcselr3XhwUKGc/s6D6B5lBN90a4hlCxd8b yBThzRQ5D2i4NsoZtP8IRzDnQSA7Erw66AzwtFpriwx+h6JGkdOhfTe0tqEQ2nsRh0yr wo55Gs8Zb+5bCdZehR2oZ8ZgX3gyNWBZPHheW5tCI6SYNbyTkbeKSWvJypfjcau8ts8f Gmi103T7NtFyjdMvS28CwpnwKuERsgkdYvWFa8eWfZFOd2x2jlpjmxBbPwUVVWPu4MAV pbiJ0m7Y7bSfTEiNfv3J3HaPNa7+kV2v3pV589j187oLYIusU2Ryav3Jnd+lBrAW/g1k yGag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374543; x=1710979343; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zbW5IRvzlbg37aGOBqwcmdzmZ6eMhDw8NOLguxq0OBQ=; b=aBXiZU8sWhFL4JtqjL9nWV8280uxaH7IXqgQwfh3gYP2NjSovzPurw7XpJ9kxkQUsb IDUwdh6JeVZ5MwhOtIZHPE7Ht7B77k8ChUPKx1AQQphrSuL1fwNO5INySeEn7syz0SyU EIo/eWFEbg3mWDlmRqKxUaYjVZPVvxwZW9V+o5iLAop2JkqOF8uxbxpuxgerTPJEVt5Q 92+2lhnxkWpia2L4vlUDOGQiHm9IVhynDR0kovq+N5p6MjYrIw2NWLGDU1GbD7kfldst ymq4rwAhs3p4ieUw1CAUPtbDvJHDbWuNtt2YC1BINNmGZ2ASvqCNlW5ahqLGUUlR5vDm IM8g== X-Forwarded-Encrypted: i=1; AJvYcCUuH3GzNCJ0GShK/a3u9pZL1+yOZ4B7A3vheFvl/kKKyVV8mM2HCj2/9M/MvZFjk9NWC113rNxBHfX0SucO2fYHZiuJdi2xZXHG5U6b8w== X-Gm-Message-State: AOJu0Yw62/SXGzQDTS7wZ56rXRxzwzS+x20J1Q+F2GK1oUsyjvLWDfKr XgTlgyxDl1p+ZE9C55dS2BAAqxSn871jMx0hVcVu8rjzh7tI6Ikc1ycm0veRRmU= X-Google-Smtp-Source: AGHT+IEiIaXzM6guY9lVj9tAa5dx2lwvHcKyXs6W04Sx8VdvE9zXuqtvl2Ap/T8Kog2xgp5nrR8fNA== X-Received: by 2002:a19:914f:0:b0:513:cff2:fe4e with SMTP id y15-20020a19914f000000b00513cff2fe4emr42255lfj.8.1710374543069; Wed, 13 Mar 2024 17:02:23 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:22 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 06/13] drm/msm/dpu: split dpu_plane_atomic_check() Date: Thu, 14 Mar 2024 02:02:09 +0200 Message-Id: <20240314000216.392549-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Split dpu_plane_atomic_check() function into two pieces: dpu_plane_atomic_check_nopipe() performing generic checks on the pstate, without touching the associated pipe, and dpu_plane_atomic_check_pipes(), which takes into account used pipes. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 184 ++++++++++++++-------- 1 file changed, 117 insertions(+), 67 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 6360052523b5..187ac2767a2b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -788,50 +788,22 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, #define MAX_UPSCALE_RATIO 20 #define MAX_DOWNSCALE_RATIO 4 -static int dpu_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, + struct drm_plane_state *new_plane_state, + const struct drm_crtc_state *crtc_state) { - struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, - plane); int ret = 0, min_scale, max_scale; struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); - struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe = &pstate->pipe; - struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; - const struct drm_crtc_state *crtc_state = NULL; - const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; struct drm_rect fb_rect = { 0 }; uint32_t max_linewidth; - unsigned int rotation; - uint32_t supported_rotations; - const struct dpu_sspp_cfg *pipe_hw_caps; - const struct dpu_sspp_sub_blks *sblk; - if (new_plane_state->crtc) - crtc_state = drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); - - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp = NULL; - - if (!pipe->sspp) - return -EINVAL; - - pipe_hw_caps = pipe->sspp->cap; - sblk = pipe->sspp->cap->sblk; - - if (sblk->scaler_blk.len) { - min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); - max_scale = MAX_DOWNSCALE_RATIO << 16; - } else { - min_scale = 1 << 16; - max_scale = 1 << 16; - } + min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO); + max_scale = MAX_DOWNSCALE_RATIO << 16; ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state, min_scale, @@ -844,11 +816,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { DPU_ERROR("> %d plane stages assigned\n", @@ -872,8 +839,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - max_linewidth = pdpu->catalog->caps->max_linewidth; drm_rect_rotate(&pipe_cfg->src_rect, @@ -882,6 +847,83 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) { + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + *r_pipe_cfg = *pipe_cfg; + pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; + pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; + r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; + } else { + memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); + } + + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + if (r_pipe_cfg->src_rect.x1 != 0) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, new_plane_state->fb->height, + new_plane_state->rotation); + + pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); + + return 0; +} + +static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, + struct drm_atomic_state *state, + const struct drm_crtc_state *crtc_state) +{ + struct drm_plane_state *new_plane_state = + drm_atomic_get_new_plane_state(state, plane); + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct dpu_format *fmt; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; + uint32_t max_linewidth; + unsigned int rotation; + uint32_t supported_rotations; + const struct dpu_sspp_cfg *pipe_hw_caps; + const struct dpu_sspp_sub_blks *sblk; + int ret = 0; + + pipe_hw_caps = pipe->sspp->cap; + sblk = pipe->sspp->cap->sblk; + + /* + * We already have verified scaling against platform limitations. + * Now check if the SSPP supports scaling at all. + */ + if (!sblk->scaler_blk.len && + ((drm_rect_width(&new_plane_state->src) >> 16 != + drm_rect_width(&new_plane_state->dst)) || + (drm_rect_height(&new_plane_state->src) >> 16 != + drm_rect_height(&new_plane_state->dst)))) + return -ERANGE; + + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); + + max_linewidth = pdpu->catalog->caps->max_linewidth; + + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, + &crtc_state->adjusted_mode); + if (ret) + return ret; + + if (r_pipe_cfg->src_rect.x1 != 0) { /* * In parallel multirect case only the half of the usual width * is supported for tiled formats. If we are here, we know that @@ -895,12 +937,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return -E2BIG; } - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && @@ -922,26 +958,6 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, r_pipe->multirect_index = DPU_SSPP_RECT_1; r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - *r_pipe_cfg = *pipe_cfg; - pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1; - pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1; - r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2; - } - - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (r_pipe->sspp) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - - ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); - if (ret) - return ret; - - if (r_pipe->sspp) { ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) @@ -964,11 +980,45 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, } pstate->rotation = rotation; - pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state); return 0; } +static int dpu_plane_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, + plane); + int ret = 0; + struct dpu_plane *pdpu = to_dpu_plane(plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state); + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + const struct drm_crtc_state *crtc_state = NULL; + + if (new_plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + new_plane_state->crtc); + + if (pdpu->pipe != SSPP_NONE) { + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; + } + + if (!pipe->sspp) + return -EINVAL; + + ret = dpu_plane_atomic_check_nopipe(plane, new_plane_state, crtc_state); + if (ret) + return ret; + + if (!new_plane_state->visible) + return 0; + + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); +} + static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) { const struct dpu_format *format = From patchwork Thu Mar 14 00:02:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591993 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE69624 for ; Thu, 14 Mar 2024 00:02:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374547; cv=none; b=a7i+7/d31W6xjVzEj35H6sGN2mJOwN3lDZGP7q8kIwkeeFWbiF/k/3y/rXf/6+T2iz+dck6mKtd5KSbIjdTRDsnBJAVlcZjWNp4di3JE4j6hUnlxvJMTDvzCasj5fPq0GTSZc5dKYPWVRve4v+FHLmCsayuhpAEa1S3Rtf4ic/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374547; c=relaxed/simple; bh=EJP+betVeTZVy5V+QQRPkJ8awZnAUMBYKjPBAF4j0Zg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tVydNKIUFeeZBMVz654IqkY71L48jFv4KWNKCf3Ax5RVRD0UJdOTgTxAZ6VVjUEcxfxAF7EGStUsh6J7YNDT9ZKIz53mrYuMXXxPqeR2mhilBpqjQsDHlqGib6m1l0Rw5lPX40kFHDotGqlyE1nYanrLKPxoKT5lJTwu4iBaKYc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=CsfFtr6R; arc=none smtp.client-ip=209.85.167.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="CsfFtr6R" Received: by mail-lf1-f50.google.com with SMTP id 2adb3069b0e04-512b3b04995so453338e87.3 for ; Wed, 13 Mar 2024 17:02:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374544; x=1710979344; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SMjERx5gJlPYsm3RKep9YqViik8n/JwZ5+oV+Ch5MHY=; b=CsfFtr6Re+jazbcm11URx8+4BsDlqrHP/7e1wpkceqDZJSLwXtxhboD71Zjq56inQz y6RH3GFVn7ydPmNY2jREtDGm6leaaFfQvlH757EBVfkSidYzht41Zfm0FkSk4HehZYOy XYJNKDQ8bTlotDa6edueZRepk9i8Vu03TUTpRVhRCwe9cVQOgy2XnBZUkFi3ecZeL6Y4 YJm5UhpX4C/shYdfZjX1N2jCB+aQmlyo+wnv5zj78ETVEq5d/JLIsrgU+5z6SIhN4bMH caH6xadS4cQPj1t6zbg9d9nIVCYGq1FMHvLeOHJd/0BRqrj1r7LyhHMZSvWcbd8gn8r1 dQcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374544; x=1710979344; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SMjERx5gJlPYsm3RKep9YqViik8n/JwZ5+oV+Ch5MHY=; b=TXT39UwraFcuRFxL+66s9zAQgDtYjY+p6Yj9Gk7BGPat+UeTh2VyZPkMLbZzFUhSyn eU0odfvx8qyJK2yARkhHuAgjz6WvvBgCoIMMORcYuT29LXFj7zr1tDlz8Q9fpII1Xxlc qSnjIi/gYWYkLlFnaOepNDWzlT1WVKV/ZdeP7ZUxFl7OExeaVvZfT3GVzjsp6ueGlw/5 8iqKEPuIyQmA0cmbx94gqn9z0uYfktUyPgpBX7+ic/YCAy7ZqQToM6iS+EgLZPOA/zji AvjAS04650PD+FM6kWrg944DD/kmRLUnIxQr3vokyfRD5Fr4ir1cuMXoXTVlXJZ3Hk5v FFig== X-Forwarded-Encrypted: i=1; AJvYcCVH41FKq3HdsVk+dr8LbPXMyzLFRzub6zaSUCSjQmWkIhoJOhbInP0J178hFp89gfzndzSX7KQABbqA+3W7jKKD8BTNr8j2JHjqWW975A== X-Gm-Message-State: AOJu0YxYN8q192WUsXVnFJbYLzkk1nFCNo5Ul7Er8AekBKmkUqpHD2tj A1W/u/6EWrhusb5GFdUOFkbEnKcb3+TUZSxcGzKraRMR6TMAzXB1NcZD9KgkHBU= X-Google-Smtp-Source: AGHT+IH2VqAAWgzBXiDTrFuh8IYTuEEuZV+tSPCwKo5+NizDb/JgmhRwMXMnY/s7YH+fjsSPMFhe5w== X-Received: by 2002:a19:ae0a:0:b0:513:572f:88f0 with SMTP id f10-20020a19ae0a000000b00513572f88f0mr45961lfc.41.1710374544250; Wed, 13 Mar 2024 17:02:24 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:23 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 07/13] drm/msm/dpu: move rot90 checking to dpu_plane_atomic_check_pipe() Date: Thu, 14 Mar 2024 02:02:10 +0200 Message-Id: <20240314000216.392549-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move a call to dpu_plane_check_inline_rotation() to the dpu_plane_atomic_check_pipe() function, so that the rot90 constraints are checked for both pipes. Also move rotation field from struct dpu_plane_state to struct dpu_sw_pipe_cfg. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 55 +++++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 2 - 3 files changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index b7dc52312c39..a774404b42b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -142,10 +142,12 @@ struct dpu_hw_pixel_ext { * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. + * @rotation: simplified drm rotation hint */ struct dpu_sw_pipe_cfg { struct drm_rect src_rect; struct drm_rect dst_rect; + unsigned int rotation; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 187ac2767a2b..a41ffa2d774b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -527,8 +527,7 @@ static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe, static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, const struct dpu_format *fmt, bool color_fill, - struct dpu_sw_pipe_cfg *pipe_cfg, - unsigned int rotation) + struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_hw_sspp *pipe_hw = pipe->sspp; const struct drm_format_info *info = drm_format_info(fmt->base.pixel_format); @@ -551,7 +550,7 @@ static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe, dst_height, &scaler3_cfg, fmt, info->hsub, info->vsub, - rotation); + pipe_cfg->rotation); /* configure pixel extension based on scalar config */ _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext, @@ -603,7 +602,7 @@ static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate, if (pipe->sspp->ops.setup_rects) pipe->sspp->ops.setup_rects(pipe, &pipe_cfg); - _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg, pstate->rotation); + _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg); } /** @@ -703,12 +702,17 @@ static void dpu_plane_cleanup_fb(struct drm_plane *plane, } static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu, - const struct dpu_sspp_sub_blks *sblk, - struct drm_rect src, const struct dpu_format *fmt) + struct dpu_sw_pipe *pipe, + struct drm_rect src, + const struct dpu_format *fmt) { + const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk; size_t num_formats; const u32 *supported_formats; + if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features)) + return -EINVAL; + if (!sblk->rotation_cfg) { DPU_ERROR("invalid rotation cfg\n"); return -EINVAL; @@ -738,6 +742,7 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, { uint32_t min_src_size; struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base); + int ret; min_src_size = DPU_FORMAT_IS_YUV(fmt) ? 2 : 1; @@ -776,6 +781,12 @@ static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu, return -EINVAL; } + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) { + ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt); + if (ret) + return ret; + } + /* max clk check */ if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) { DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n"); @@ -889,7 +900,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; uint32_t max_linewidth; - unsigned int rotation; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -918,6 +928,15 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, max_linewidth = pdpu->catalog->caps->max_linewidth; + supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; + + if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) + supported_rotations |= DRM_MODE_ROTATE_90; + + pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation, + supported_rotations); + r_pipe_cfg->rotation = pipe_cfg->rotation; + ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) @@ -941,6 +960,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || + pipe_cfg->rotation & DRM_MODE_ROTATE_90 || DPU_FORMAT_IS_YUV(fmt)) { DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); @@ -964,23 +984,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, return ret; } - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; - - if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) - supported_rotations |= DRM_MODE_ROTATE_90; - - rotation = drm_rotation_simplify(new_plane_state->rotation, - supported_rotations); - - if ((pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) && - (rotation & DRM_MODE_ROTATE_90)) { - ret = dpu_plane_check_inline_rotation(pdpu, sblk, pipe_cfg->src_rect, fmt); - if (ret) - return ret; - } - - pstate->rotation = rotation; - return 0; } @@ -1120,14 +1123,14 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, pipe_cfg); } - _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg, pstate->rotation); + _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg); if (pipe->sspp->ops.setup_multirect) pipe->sspp->ops.setup_multirect( pipe); if (pipe->sspp->ops.setup_format) { - unsigned int rotation = pstate->rotation; + unsigned int rotation = pipe_cfg->rotation; src_flags = 0x0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index abd6b21a049b..a3ae45dc95d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -30,7 +30,6 @@ * @plane_fetch_bw: calculated BW per plane * @plane_clk: calculated clk per plane * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed - * @rotation: simplified drm rotation hint */ struct dpu_plane_state { struct drm_plane_state base; @@ -47,7 +46,6 @@ struct dpu_plane_state { u64 plane_clk; bool needs_dirtyfb; - unsigned int rotation; }; #define to_dpu_plane_state(x) \ From patchwork Thu Mar 14 00:02:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591994 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C47710F7 for ; Thu, 14 Mar 2024 00:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374549; cv=none; b=dIHT1oYzQbNMqBdjsDKX7jqRTl/2KVwI+7xFqcSmh2w2h7bV+APPkJgR9bG+Zn2Ru4M14JJA10G8YS+xAxUqftqLybWmZ4GbibgdSE5f6XwhaBB0CCAeEFkywZTjwGLLCih+4cRR77DbeXMK4Kj7T0Cx8pj6Zpo9WXfestK1iEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374549; c=relaxed/simple; bh=mr6no92h2hdO98Vz+R1d4SE+wz0Hb+GwWiX9PwArM14=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o/3QmtgA4BG1zmO7E8tJmJboVhTAXOH8+vOLIoqVeYziE0YDcqmmv2z0U1IEE+AeYYncjM7T2BM2XSZJ1CE2kEmQndejEuLpbPsY89/30tkb1nrwbgWCxxAxx5P3cIRkoh/PogxAwnd2GH1NRZpLZgBXT0QJJItn1y/8V4ba+Zo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fLthYQf+; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fLthYQf+" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-513cfd48224so174114e87.2 for ; Wed, 13 Mar 2024 17:02:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374545; x=1710979345; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g09xNDIM/a80W/BtZu/idQFJ47jJWtTLSzparqcCdCM=; b=fLthYQf+8UjFRPNcki58IEfW56z1+HL+C6AwJzApOxgCy1E4vl3hn+YQKX7c0ZQ4up lXSl0O/5Oewv19e7DYT1AcoOwUX8j7di3TP9C3zn144VJeKOgADpOxEyCp8WZB+HvD3/ wQ+Vtdv1iYaqpY7uq7wI+yPuIe+uLEko1+yuHQAnvAE8zvpzPKJjLgkQdER23Npb/PWR KY4TFA6pOLkI+vqBhTt2jDmrO0cNTVjES7t+Cjms7mRrQCHWmP7FeGz3b++fVq00Icn/ c9nvXhwg89Ljx3JVQvBFK6xK7MyDmqOHU6cOfKtrx9vJhPx1E7mNC7GfJWiMKWfA0wbL lG7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374545; x=1710979345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g09xNDIM/a80W/BtZu/idQFJ47jJWtTLSzparqcCdCM=; b=JrMPZftAWoljkb+57GEmp0cy4cmpILslndYeskA/mbuQmej2SnQLhhQIUGWXNHBvAS duScNGTfqaNDT1laPJ7pPCQjNvV2/8NIDtJlXdtW6intaXKP3ePADSoO6qsNPfodFVuR poIpJDwNTJYv1DdWgt4S42dUhOxZRZ26JmFAiQWldfBtL0EloPX9fZijE7CSOZXXNfzo qpoD3t7kAzuiTWycixRLfao4vEmbEYzbFcbviCBGiIZ1ZBBfd7mW8ID60JZxOQVOirb1 8mGlGmQ9gCOn9eWmbWHP3hWyW/uV+70s6Z5Ue6E1BkCHt1xFLtP5kBDswnVnlm//fD1S JLJg== X-Forwarded-Encrypted: i=1; AJvYcCXvzQkEU3HkTl9+bge7q4xfjKHexvt8d3PRv0EsgT9S4fmpgeqFEog5MwTkPpF5NdUsOM5xkVCC5wAW9+R0ZgpyhfWBl7boaSEDHQFf6A== X-Gm-Message-State: AOJu0Yy0nSJ3flgHdVjTdw4ssFDfb0jIQEjKK5rV4M9u1o6HA34XhUa1 6RVuuiQ10LLdwvqzZ8bUpFNZ8uQ6Tn7Unih2dZAP2ymkgSiInNBNcDdt6kdwffw= X-Google-Smtp-Source: AGHT+IFV4gdUvw4Y34oHHTmjeg0zs7Fg6hhx41uiLK92cTqhnfs0vWNe4VttwTz3BLpvUivVs8Z9Tw== X-Received: by 2002:a19:9142:0:b0:513:ca40:fafc with SMTP id y2-20020a199142000000b00513ca40fafcmr42430lfj.11.1710374545060; Wed, 13 Mar 2024 17:02:25 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 08/13] drm/msm/dpu: add support for virtual planes Date: Thu, 14 Mar 2024 02:02:11 +0200 Message-Id: <20240314000216.392549-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Only several SSPP blocks support such features as YUV output or scaling, thus different DRM planes have different features. Properly utilizing all planes requires the attention of the compositor, who should prefer simpler planes to YUV-supporting ones. Otherwise it is very easy to end up in a situation when all featureful planes are already allocated for simple windows, leaving no spare plane for YUV playback. To solve this problem make all planes virtual. Each plane is registered as if it supports all possible features, but then at the runtime during the atomic_check phase the driver selects backing SSPP block for each plane. Note, this does not provide support for using two different SSPP blocks for a single plane or using two rectangles of an SSPP to drive two planes. Each plane still gets its own SSPP and can utilize either a solo rectangle or both multirect rectangles depending on the resolution. Note #2: By default support for virtual planes is turned off and the driver still uses old code path with preallocated SSPP block for each plane. To enable virtual planes, pass 'msm.dpu_use_virtual_planes=1' kernel parameter. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 50 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 10 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 230 +++++++++++++++++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 19 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 77 ++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 28 +++ 7 files changed, 390 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 88c2e51ab166..794c5643584f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1168,6 +1168,49 @@ static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) return false; } +static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) +{ + int total_planes = crtc->dev->mode_config.num_total_plane; + struct drm_atomic_state *state = crtc_state->state; + struct dpu_global_state *global_state; + struct drm_plane_state **states; + struct drm_plane *plane; + int ret; + + global_state = dpu_kms_get_global_state(crtc_state->state); + if (IS_ERR(global_state)) + return PTR_ERR(global_state); + + dpu_rm_release_all_sspp(global_state, crtc); + + if (!crtc_state->enable) + return 0; + + states = kcalloc(total_planes, sizeof(*states), GFP_KERNEL); + if (!states) + return -ENOMEM; + + drm_atomic_crtc_state_for_each_plane(plane, crtc_state) { + struct drm_plane_state *plane_state = + drm_atomic_get_plane_state(state, plane); + + if (IS_ERR(plane_state)) { + ret = PTR_ERR(plane_state); + goto done; + } + + states[plane_state->normalized_zpos] = plane_state; + } + + ret = dpu_assign_plane_resources(global_state, state, crtc, states, total_planes); + +done: + kfree(states); + return ret; + + return 0; +} + static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) { @@ -1183,6 +1226,13 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); + if (dpu_use_virtual_planes && + (crtc_state->planes_changed || crtc_state->zpos_changed)) { + rc = dpu_crtc_reassign_planes(crtc, crtc_state); + if (rc < 0) + return rc; + } + if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) { DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", crtc->base.id, crtc_state->enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 9a1fe6868979..becdd98f3c40 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -51,6 +51,9 @@ #define DPU_DEBUGFS_DIR "msm_dpu" #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask" +bool dpu_use_virtual_planes = false; +module_param(dpu_use_virtual_planes, bool, 0); + static int dpu_kms_hw_init(struct msm_kms *kms); static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms); @@ -770,8 +773,11 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) type, catalog->sspp[i].features, catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR)); - plane = dpu_plane_init(dev, catalog->sspp[i].id, type, - (1UL << max_crtc_count) - 1); + if (dpu_use_virtual_planes) + plane = dpu_plane_init_virtual(dev, type, (1UL << max_crtc_count) - 1); + else + plane = dpu_plane_init(dev, catalog->sspp[i].id, type, + (1UL << max_crtc_count) - 1); if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret = PTR_ERR(plane); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index e2adc937ea63..195257660057 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -64,6 +64,8 @@ #define ktime_compare_safe(A, B) \ ktime_compare(ktime_sub((A), (B)), ktime_set(0, 0)) +extern bool dpu_use_virtual_planes; + struct dpu_kms { struct msm_kms base; struct drm_device *dev; @@ -138,6 +140,8 @@ struct dpu_global_state { uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0]; uint32_t dsc_to_enc_id[DSC_MAX - DSC_0]; uint32_t cdm_to_enc_id; + + uint32_t sspp_to_crtc_id[SSPP_MAX - SSPP_NONE]; }; struct dpu_global_state diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index a41ffa2d774b..2961b809ccf3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -876,7 +876,7 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, drm_rect_rotate_inv(&pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); - if (r_pipe_cfg->src_rect.x1 != 0) + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) drm_rect_rotate_inv(&r_pipe_cfg->src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); @@ -942,7 +942,7 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, if (ret) return ret; - if (r_pipe_cfg->src_rect.x1 != 0) { + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { /* * In parallel multirect case only the half of the usual width * is supported for tiled formats. If we are here, we know that @@ -1022,6 +1022,113 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, return dpu_plane_atomic_check_pipes(plane, state, crtc_state); } +static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, + struct drm_atomic_state *state) +{ + struct drm_plane_state *plane_state = + drm_atomic_get_plane_state(state, plane); + struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state); + const struct dpu_format *format; + struct drm_crtc_state *crtc_state; + int ret; + + if (plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + ret = dpu_plane_atomic_check_nopipe(plane, plane_state, crtc_state); + if (ret) + return ret; + + if (!plane_state->visible) { + /* + * resources are freed by dpu_crtc_assign_plane_resources(), + * but clean them here. + */ + pstate->pipe.sspp = NULL; + pstate->r_pipe.sspp = NULL; + + return 0; + } + + format = to_dpu_format(msm_framebuffer_format(plane_state->fb)); + + /* force resource reallocation if the format of FB has changed */ + if (pstate->saved_fmt != format) { + crtc_state->planes_changed = true; + pstate->saved_fmt = format; + } + + return 0; +} + +static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, + struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_plane_state *plane_state) +{ + const struct drm_crtc_state *crtc_state = NULL; + struct drm_plane *plane = plane_state->plane; + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); + struct dpu_rm_sspp_requirements reqs; + struct dpu_plane_state *pstate; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe *r_pipe; + const struct dpu_format *fmt; + + if (plane_state->crtc) + crtc_state = drm_atomic_get_new_crtc_state(state, + plane_state->crtc); + + pstate = to_dpu_plane_state(plane_state); + pipe = &pstate->pipe; + r_pipe = &pstate->r_pipe; + + pipe->sspp = NULL; + r_pipe->sspp = NULL; + + if (!plane_state->fb) + return -EINVAL; + + fmt = to_dpu_format(msm_framebuffer_format(plane_state->fb)); + reqs.yuv = DPU_FORMAT_IS_YUV(fmt); + reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) || + (plane_state->src_h >> 16 != plane_state->crtc_h); + + reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); + + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!pipe->sspp) + return -ENODEV; + + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); +} + +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes) +{ + unsigned int i; + int ret; + + for (i = 0; i < num_planes; i++) { + struct drm_plane_state *plane_state = states[i]; + + if (!plane_state || + !plane_state->visible) + continue; + + ret = dpu_plane_virtual_assign_resources(crtc, global_state, + state, plane_state); + if (ret) + break; + } + + return ret; +} + static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe) { const struct dpu_format *format = @@ -1342,12 +1449,14 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p, drm_printf(p, "\tstage=%d\n", pstate->stage); - drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=%s\n", - dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); - drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + if (pipe->sspp) { + drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[0]=%s\n", dpu_get_multirect_mode(pipe->multirect_mode)); + drm_printf(p, "\tmultirect_index[0]=%s\n", + dpu_get_multirect_index(pipe->multirect_index)); + drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect)); + } if (r_pipe->sspp) { drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name); @@ -1436,31 +1545,29 @@ static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = { .atomic_update = dpu_plane_atomic_update, }; +static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = { + .prepare_fb = dpu_plane_prepare_fb, + .cleanup_fb = dpu_plane_cleanup_fb, + .atomic_check = dpu_plane_virtual_atomic_check, + .atomic_update = dpu_plane_atomic_update, +}; + /* initialize plane */ -struct drm_plane *dpu_plane_init(struct drm_device *dev, - uint32_t pipe, enum drm_plane_type type, - unsigned long possible_crtcs) +static struct drm_plane *dpu_plane_init_common(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs, + bool inline_rotation, + const uint32_t *format_list, + uint32_t num_formats, + enum dpu_sspp pipe) { struct drm_plane *plane = NULL; - const uint32_t *format_list; struct dpu_plane *pdpu; struct msm_drm_private *priv = dev->dev_private; struct dpu_kms *kms = to_dpu_kms(priv->kms); - struct dpu_hw_sspp *pipe_hw; - uint32_t num_formats; uint32_t supported_rotations; int ret; - /* initialize underlying h/w driver */ - pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); - if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { - DPU_ERROR("[%u]SSPP is invalid\n", pipe); - return ERR_PTR(-EINVAL); - } - - format_list = pipe_hw->cap->sblk->format_list; - num_formats = pipe_hw->cap->sblk->num_formats; - pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base, 0xff, &dpu_plane_funcs, format_list, num_formats, @@ -1486,7 +1593,7 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; - if (pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION)) + if (inline_rotation) supported_rotations |= DRM_MODE_ROTATE_MASK; drm_plane_create_rotation_property(plane, @@ -1494,10 +1601,81 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, drm_plane_enable_fb_damage_clips(plane); - /* success! finalize initialization */ + DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, + pipe, plane->base.id); + return plane; +} + +struct drm_plane *dpu_plane_init(struct drm_device *dev, + uint32_t pipe, enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane = NULL; + struct msm_drm_private *priv = dev->dev_private; + struct dpu_kms *kms = to_dpu_kms(priv->kms); + struct dpu_hw_sspp *pipe_hw; + + /* initialize underlying h/w driver */ + pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe); + if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) { + DPU_ERROR("[%u]SSPP is invalid\n", pipe); + return ERR_PTR(-EINVAL); + } + + + plane = dpu_plane_init_common(dev, type, possible_crtcs, + pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION), + pipe_hw->cap->sblk->format_list, + pipe_hw->cap->sblk->num_formats, + pipe); + if (IS_ERR(plane)) + return plane; + drm_plane_helper_add(plane, &dpu_plane_helper_funcs); DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name, pipe, plane->base.id); + + return plane; +} + +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs) +{ + struct drm_plane *plane = NULL; + struct msm_drm_private *priv = dev->dev_private; + struct dpu_kms *kms = to_dpu_kms(priv->kms); + bool has_inline_rotation = false; + const u32 *format_list = NULL; + u32 num_formats = 0; + int i; + + /* Determine the largest configuration that we can implement */ + for (i = 0; i < kms->catalog->sspp_count; i++) { + const struct dpu_sspp_cfg *cfg = &kms->catalog->sspp[i]; + + if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features)) + has_inline_rotation = true; + + if (!format_list || + cfg->sblk->csc_blk.len) { + format_list = cfg->sblk->format_list; + num_formats = cfg->sblk->num_formats; + } + } + + plane = dpu_plane_init_common(dev, type, possible_crtcs, + has_inline_rotation, + format_list, + num_formats, + SSPP_NONE); + if (IS_ERR(plane)) + return plane; + + drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs); + + DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id); + return plane; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index a3ae45dc95d0..15f7d60d8b85 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -30,6 +30,7 @@ * @plane_fetch_bw: calculated BW per plane * @plane_clk: calculated clk per plane * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed + * @saved_fmt: format used by the plane's FB, saved for for virtual plane support */ struct dpu_plane_state { struct drm_plane_state base; @@ -46,6 +47,8 @@ struct dpu_plane_state { u64 plane_clk; bool needs_dirtyfb; + + const struct dpu_format *saved_fmt; }; #define to_dpu_plane_state(x) \ @@ -75,6 +78,16 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, enum drm_plane_type type, unsigned long possible_crtcs); +/** + * dpu_plane_init_virtual - create new dpu virtualized plane + * @dev: Pointer to DRM device + * @type: Plane type - PRIMARY/OVERLAY/CURSOR + * @possible_crtcs: bitmask of crtc that can be attached to the given pipe + */ +struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev, + enum drm_plane_type type, + unsigned long possible_crtcs); + /** * dpu_plane_color_fill - enables color fill on plane * @plane: Pointer to DRM plane object @@ -91,4 +104,10 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable); static inline void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) {} #endif +int dpu_assign_plane_resources(struct dpu_global_state *global_state, + struct drm_atomic_state *state, + struct drm_crtc *crtc, + struct drm_plane_state **states, + unsigned int num_planes); + #endif /* _DPU_PLANE_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 44938ba7a2b7..7264a4d44a14 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -694,6 +694,83 @@ int dpu_rm_reserve( return ret; } +struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + uint32_t crtc_id = crtc->base.id; + unsigned int weight, best_weght = UINT_MAX; + struct dpu_hw_sspp *hw_sspp; + unsigned long mask = 0; + int i, best_idx = -1; + + /* + * Don't take cursor feature into consideration until there is proper support for SSPP_CURSORn. + */ + mask |= BIT(DPU_SSPP_CURSOR); + + if (reqs->scale) + mask |= BIT(DPU_SSPP_SCALER_RGB) | + BIT(DPU_SSPP_SCALER_QSEED2) | + BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE); + + if (reqs->yuv) + mask |= BIT(DPU_SSPP_CSC) | + BIT(DPU_SSPP_CSC_10BIT); + + if (reqs->rot90) + mask |= BIT(DPU_SSPP_INLINE_ROTATION); + + for (i = 0; i < ARRAY_SIZE(rm->hw_sspp); i++) { + if (!rm->hw_sspp[i]) + continue; + + if (global_state->sspp_to_crtc_id[i]) + continue; + + hw_sspp = rm->hw_sspp[i]; + + /* skip incompatible planes */ + if (reqs->scale && !hw_sspp->cap->sblk->scaler_blk.len) + continue; + + if (reqs->yuv && !hw_sspp->cap->sblk->csc_blk.len) + continue; + + if (reqs->rot90 && !(hw_sspp->cap->features & DPU_SSPP_INLINE_ROTATION)) + continue; + + /* + * For non-yuv, non-scaled planes prefer simple (DMA or RGB) + * plane, falling back to VIG only if there are no such planes. + * + * This way we'd leave VIG sspps to be later used for YUV formats. + */ + weight = hweight64(hw_sspp->cap->features & ~mask); + if (weight < best_weght) { + best_weght = weight; + best_idx = i; + } + } + + if (best_idx < 0) + return NULL; + + global_state->sspp_to_crtc_id[best_idx] = crtc_id; + + return rm->hw_sspp[best_idx]; +} + +void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, + struct drm_crtc *crtc) +{ + uint32_t crtc_id = crtc->base.id; + + _dpu_rm_clear_mapping(global_state->sspp_to_crtc_id, + ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); +} + int dpu_rm_get_assigned_resources(struct dpu_rm *rm, struct dpu_global_state *global_state, uint32_t enc_id, enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index e63db8ace6b9..bf9110547385 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -37,6 +37,12 @@ struct dpu_rm { struct dpu_hw_blk *cdm_blk; }; +struct dpu_rm_sspp_requirements { + bool yuv; + bool scale; + bool rot90; +}; + /** * dpu_rm_init - Read hardware catalog and create reservation tracking objects * for all HW blocks. @@ -82,6 +88,28 @@ int dpu_rm_reserve(struct dpu_rm *rm, void dpu_rm_release(struct dpu_global_state *global_state, struct drm_encoder *enc); +/** + * dpu_rm_reserve_sspp - Reserve the required SSPP for the provided CRTC + * @rm: DPU Resource Manager handle + * @global_state: private global state + * @crtc: DRM CRTC handle + * @reqs: SSPP required features + */ +struct dpu_hw_sspp *dpu_rm_reserve_sspp(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs); + +/** + * dpu_rm_release_all_sspp - Given the CRTC, release all SSPP + * blocks previously reserved for that use case. + * @rm: DPU Resource Manager handle + * @crtc: DRM CRTC handle + * @Return: 0 on Success otherwise -ERROR + */ +void dpu_rm_release_all_sspp(struct dpu_global_state *global_state, + struct drm_crtc *crtc); + /** * Get hw resources of the given type that are assigned to this encoder. */ From patchwork Thu Mar 14 00:02:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591995 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 940FF20EB for ; Thu, 14 Mar 2024 00:02:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374549; cv=none; b=aeSyn6appqHnjHyp8AoGLHohclJPgEJm9+cIZ0l7Xoz48Ug8enuYQG6uTR1OzMxS6tOImub1kmdl3Q2zbBcKTojlwCw51ytHzkwmgsYOgsEL/NttcrWvIEk3GrCC2FNfKKMUrcWsQp0hoErkvqJvZRcon0nd0hAjvMX1gS3noYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374549; c=relaxed/simple; bh=lui5sL0//8wS1sIzmzf52EzIt+mQozQiUxZheo+n73I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a5M7K9W/imOpsDXzE3dcufRUHT8R4l2MX8hgdclCXAiSlqvZaiHl8JaMkk9XGrrqf3yXh4pW3RMqvLTSMlWjsm4qRD0cNHabOipf5f4YYSHEhUKc5fXcUmkCWyP5uPd205woj50NUwaMAuoSz3h9QGVz0jy+yC6oKSTrH/e51gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zG50xUkI; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zG50xUkI" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-513a81b717cso564033e87.0 for ; Wed, 13 Mar 2024 17:02:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374546; x=1710979346; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2PjrhT6a27c234XDd1UAZn9+fAuU0fdQoiJECkOgv0E=; b=zG50xUkIDsNWvMOmrWAk8iN7Iw5HB4pLO6NnOfOmXvrPosxOTdOw8GPnFJaOWWwMjf f2Rx35HHKDDEXkank+BEkP8aiVWJE5kkfiY8Us2DwnlDysG1UYstScWTl/lVrxhUhgxf 4y1EcP/jQ6h/ju7nGMMu22mVC53hjVjvF0dEHotTS3RRms2WPZ25uXVD7jvhvEBxDLiP NwDpdm/lHcrnRAHNovqUVDHfv1LjwGOCrmM/n/6xi/EdOPe5j2dVvkPzvdWPux8Q50XW k+9eFiuHzJYgXr+z7ZAb0dzk30pPxEqx+Tq0Ng3vd63S4iOXmtIOluYTQIpTPsngFeEn iWZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374546; x=1710979346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2PjrhT6a27c234XDd1UAZn9+fAuU0fdQoiJECkOgv0E=; b=kq7p2zzexLhD+CbTcbkfVFKEb1KiBxuNj5d1MiUt/T40II2ufE5eTanK9ODNwkqqQw TnBRqtqvRIUOJXPn6MmPtJBS5ze1h9TZFYU2jmnrFth79iBjkWrwD46ecqRLTjSURy7m 2P+FzHUmRa4k5QR68CfYXiqfzbzzWG/zSbF5t//91vRh8WbcKujxVD4lqRvAu7UdDaLy oJ2UgAJ9ahoIMH29GS4dvX/fXGG2SgO6XvNgKOON5Im9NkAcmo3dreCrHGa5PzKdsn4p gi/SqAiHDLnjZzVj2AwnbzKIZA9w8B/atuMJBTc+O22xG90RjvSZoiguL5GgtGDduZ9x 0zDw== X-Forwarded-Encrypted: i=1; AJvYcCWWmAsnx/cSCjU2RpJj8gs3LRm4MkDN4C4a+g6mFzeIc2fa/FV9fTHr9fkTsIe+PEAYko2jnqk/QN2wBW7Fre2OIEo2BmthBnieufLpNg== X-Gm-Message-State: AOJu0YyvelXndaQ2TSsrZDk8J8MXvrRZhBjfQeBVOsoVQCDwOlvp1p8A odg2q0VpaY08MZjLdQSb3toePYnAQy98UPHDnrM0fMZRij7LPsILk3jGTk8sKzx4C7O4vTB2O8S W X-Google-Smtp-Source: AGHT+IGuKR8qVbwIuDszsiEvTR2T5e9+glIc5undJ9V4gEe8zTE7KxKSDhoXQT50ghsOysn7iVRtxw== X-Received: by 2002:a19:5f54:0:b0:513:cf61:6847 with SMTP id a20-20020a195f54000000b00513cf616847mr43488lfj.22.1710374545873; Wed, 13 Mar 2024 17:02:25 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:25 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 09/13] drm/msm/dpu: allow using two SSPP blocks for a single plane Date: Thu, 14 Mar 2024 02:02:12 +0200 Message-Id: <20240314000216.392549-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Virtual wide planes give high amount of flexibility, but it is not always enough: In parallel multirect case only the half of the usual width is supported for tiled formats. Thus the whole width of two tiled multirect rectangles can not be greater than max_linewidth, which is not enough for some platforms/compositors. Another example is as simple as wide YUV plane. YUV planes can not use multirect, so currently they are limited to max_linewidth too. Now that the planes are fully virtualized, add support for allocating two SSPP blocks to drive a single DRM plane. This fixes both mentioned cases and allows all planes to go up to 2*max_linewidth (at the cost of making some of the planes unavailable to the user). Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 172 ++++++++++++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 8 + 2 files changed, 131 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 2961b809ccf3..cde20c1fa90d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -886,6 +886,28 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, return 0; } +static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + uint32_t max_linewidth) +{ + if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || + drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect)) + return false; + + if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) + return false; + + if (DPU_FORMAT_IS_YUV(fmt)) + return false; + + if (DPU_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) + return false; + + return true; +} + static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, struct drm_atomic_state *state, const struct drm_crtc_state *crtc_state) @@ -899,7 +921,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, const struct dpu_format *fmt; struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; - uint32_t max_linewidth; uint32_t supported_rotations; const struct dpu_sspp_cfg *pipe_hw_caps; const struct dpu_sspp_sub_blks *sblk; @@ -919,15 +940,8 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, drm_rect_height(&new_plane_state->dst)))) return -ERANGE; - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; - fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); - max_linewidth = pdpu->catalog->caps->max_linewidth; - supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0; if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION)) @@ -943,41 +957,6 @@ static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, return ret; if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { - /* - * In parallel multirect case only the half of the usual width - * is supported for tiled formats. If we are here, we know that - * full width is more than max_linewidth, thus each rect is - * wider than allowed. - */ - if (DPU_FORMAT_IS_UBWC(fmt) && - drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - - if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || - drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect) || - (!test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) && - !test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features)) || - pipe_cfg->rotation & DRM_MODE_ROTATE_90 || - DPU_FORMAT_IS_YUV(fmt)) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; - } - - /* - * Use multirect for wide plane. We do not support dynamic - * assignment of SSPPs, so we know the configuration. - */ - pipe->multirect_index = DPU_SSPP_RECT_0; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - - r_pipe->sspp = pipe->sspp; - r_pipe->multirect_index = DPU_SSPP_RECT_1; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt, &crtc_state->adjusted_mode); if (ret) @@ -998,16 +977,16 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); struct dpu_sw_pipe *pipe = &pstate->pipe; struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg; const struct drm_crtc_state *crtc_state = NULL; if (new_plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); - if (pdpu->pipe != SSPP_NONE) { - pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); - r_pipe->sspp = NULL; - } + pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe); + r_pipe->sspp = NULL; if (!pipe->sspp) return -EINVAL; @@ -1019,6 +998,52 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) { + uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth; + const struct dpu_format *fmt; + + fmt = to_dpu_format(msm_framebuffer_format(new_plane_state->fb)); + + /* + * In parallel multirect case only the half of the usual width + * is supported for tiled formats. If we are here, we know that + * full width is more than max_linewidth, thus each rect is + * wider than allowed. + */ + if (DPU_FORMAT_IS_UBWC(fmt) && + drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, tiled format\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + r_pipe->sspp = pipe->sspp; + + if (!dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) || + !dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) || + !(test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u, can't use split source\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + /* + * Use multirect for wide plane. We do not support dynamic + * assignment of SSPPs, so we know the configuration. + */ + pipe->multirect_index = DPU_SSPP_RECT_0; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->multirect_index = DPU_SSPP_RECT_1; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + } + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); } @@ -1053,10 +1078,18 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, format = to_dpu_format(msm_framebuffer_format(plane_state->fb)); - /* force resource reallocation if the format of FB has changed */ - if (pstate->saved_fmt != format) { + /* force resource reallocation if the format of FB or src/dst have changed */ + if (pstate->saved_fmt != format || + pstate->saved_src_w != plane_state->src_w || + pstate->saved_src_h != plane_state->src_h || + pstate->saved_src_w != plane_state->src_w || + pstate->saved_crtc_h != plane_state->crtc_h) { crtc_state->planes_changed = true; pstate->saved_fmt = format; + pstate->saved_src_w = plane_state->src_w; + pstate->saved_src_h = plane_state->src_h; + pstate->saved_crtc_w = plane_state->crtc_w; + pstate->saved_crtc_h = plane_state->crtc_h; } return 0; @@ -1074,7 +1107,10 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_plane_state *pstate; struct dpu_sw_pipe *pipe; struct dpu_sw_pipe *r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct dpu_format *fmt; + uint32_t max_linewidth; if (plane_state->crtc) crtc_state = drm_atomic_get_new_crtc_state(state, @@ -1083,6 +1119,8 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, pstate = to_dpu_plane_state(plane_state); pipe = &pstate->pipe; r_pipe = &pstate->r_pipe; + pipe_cfg = &pstate->pipe_cfg; + r_pipe_cfg = &pstate->r_pipe_cfg; pipe->sspp = NULL; r_pipe->sspp = NULL; @@ -1097,10 +1135,46 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation); + max_linewidth = dpu_kms->catalog->caps->max_linewidth; + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); if (!pipe->sspp) return -ENODEV; + if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + r_pipe->sspp = NULL; + } else { + if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) && + dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) && + (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &pipe->sspp->cap->features))) { + r_pipe->sspp = pipe->sspp; + + pipe->multirect_index = DPU_SSPP_RECT_0; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + r_pipe->multirect_index = DPU_SSPP_RECT_1; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + } else { + /* multirect is not possible, use two SSPP blocks */ + r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!r_pipe->sspp) + return -ENODEV; + + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + } + } + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index 15f7d60d8b85..5522f9035d68 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -31,6 +31,10 @@ * @plane_clk: calculated clk per plane * @needs_dirtyfb: whether attached CRTC needs pixel data explicitly flushed * @saved_fmt: format used by the plane's FB, saved for for virtual plane support + * @saved_src_w: cached value of plane's src_w, saved for for virtual plane support + * @saved_src_h: cached value of plane's src_h, saved for for virtual plane support + * @saved_crtc_w: cached value of plane's crtc_w, saved for for virtual plane support + * @saved_crtc_h: cached value of plane's crtc_h, saved for for virtual plane support */ struct dpu_plane_state { struct drm_plane_state base; @@ -49,6 +53,10 @@ struct dpu_plane_state { bool needs_dirtyfb; const struct dpu_format *saved_fmt; + uint32_t saved_src_w; + uint32_t saved_src_h; + uint32_t saved_crtc_w; + uint32_t saved_crtc_h; }; #define to_dpu_plane_state(x) \ From patchwork Thu Mar 14 00:02:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591996 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFA552C9E for ; Thu, 14 Mar 2024 00:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374550; cv=none; b=AkzZ1BbgzCEmcNBtiLk5VWnLOc9LYDP+rzkJHFJceGJMbzIoTv5LBfM6lM3ZNaD5cSEHsiJDK6bqlzNAkkIn6ZjmVWU3dTHJxbDs/7EDV/oqsIzJ25iGVEG9VoS0vAeeWGcvhBg80+kgVo+SgINUk3ra7W5QTpBdZyJQCddSE3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374550; c=relaxed/simple; bh=z3LLg/VK4BmRUmO+6IS3pr7tlicD+N6PzqCBonXL4rw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R8mAsVbe06QKFbCvCwGxJXJSVajzmZhCiYovLqPOg59S1pa0MzEB974D/Rk52nsMoAm0T6NomItF1ju76XJHmxQ3pEzIuIVRDu/+AZMeRfn3bCVRnhBH7Q4xjUrMUpVay5JPnYasCb5pNoP/ZzKJPj/dCEirs1UOH1HHRh7H21s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=yloCWQay; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="yloCWQay" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-513382f40e9so485602e87.2 for ; Wed, 13 Mar 2024 17:02:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374547; x=1710979347; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pkVn674vUD7EPt+lgPohg2m9UJkSbMPId/q0P1tsdBY=; b=yloCWQayQ6smHcIIHbUbh+LRBnTDiMHU7qTMCtKQz/AGdqEidPcwRtNbLAm8JiCAKG AG8ik1+vbJFdaY5X0cTouaxwP7bbF9r8hvDSImjJIMmh1TPToAkUwSGjZ93HN5ZVX5JJ //Qq9UNwGvG2CtsCdTIuGPnTs2T8w77Io8B2Hgex5wLjsk/hRCkuUQroltFnTtuPThTB 6h1vHiOC/6y3g3xGxP7h3gdLi/g6Gtb5UJOUrGP1LKn809oOZBm6nWRWqvOFSq+HAWWB SaqqdbF2ONh1jTpzHJTx5YdngAyG1fhLpIzK1HJ6IQSq5lIWrmLAtAiZFQtcrO0qt2dx duuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374547; x=1710979347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pkVn674vUD7EPt+lgPohg2m9UJkSbMPId/q0P1tsdBY=; b=DGqfNbBUji4vS3FEvzvuhIbmhRcD9Wc6PUhgmIRxPVl7v1X7kmNkv6l/Km/pTfSxsO OaUBUlsaHeAzZX7QBhhfDH2SmUEpY7s0eKx7X3RexGjWACGaorvxNWYWyVZgjfdC3fzd vMsVtRaKZ6KaYLzkwkJjUp/ULmNUwEs6cvnlmqA7/z6AwyukWI+XVkFGt9Ah6L7e2w11 831YJbwwRZdlhlPAwZ2swtNRK7CIn8+MRNthNU7yiGiFVoocbjfS1PKh27OaKYeh0lJO /WjZs6dfObWD4nh84XalODE+RwaP3ylsm3407bb6fxL8TQo6BMcS4RP4NtPeJvM0kSaB Tcdg== X-Forwarded-Encrypted: i=1; AJvYcCXjU29wRPZskQPaqOU/w4pCIqrH7ERqgIAGhJDgtUzQpyLS9oAOoK+LwvULHWH0tyPy+sGEwGfpzI87T3XKzalxxM9t8xiaqaC3tqS/ww== X-Gm-Message-State: AOJu0YxiCa8GZ9tpCmT6Ki48gEKowfpBODBxU3p95IjmKf3ZGPhFc/7B 7U4Yc0rUfGdpr42Kb6fQ5MXgoLdyLk19WA3l6PnZIRyPaSZq1CaB00w8YC1fEpg= X-Google-Smtp-Source: AGHT+IGjyhST2MEHmYm8qVlyj0FWIeE/08ge6huKoEyo0olLDE/jvx+pxdZ6fNV30wgDZS8F53SIJQ== X-Received: by 2002:a05:6512:3095:b0:513:c174:c3f6 with SMTP id z21-20020a056512309500b00513c174c3f6mr41441lfd.40.1710374546958; Wed, 13 Mar 2024 17:02:26 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:26 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 10/13] drm/msm/dpu: allow sharing SSPP between planes Date: Thu, 14 Mar 2024 02:02:13 +0200 Message-Id: <20240314000216.392549-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since SmartDMA planes provide two rectangles, it is possible to use them to drive two different DRM planes, first plane getting the rect_0, another one using rect_1 of the same SSPP. The sharing algorithm is pretty simple, it requires that each of the planes can be driven by the single rectangle and only consequetive planes are considered. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 128 +++++++++++++++++++--- 1 file changed, 112 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index cde20c1fa90d..2e1c544efc4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -886,10 +886,9 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, return 0; } -static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe, - struct dpu_sw_pipe_cfg *pipe_cfg, - const struct dpu_format *fmt, - uint32_t max_linewidth) +static int dpu_plane_is_multirect_capable(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt) { if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) || drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect)) @@ -901,6 +900,13 @@ static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe, if (DPU_FORMAT_IS_YUV(fmt)) return false; + return true; +} + +static int dpu_plane_is_parallel_capable(struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + uint32_t max_linewidth) +{ if (DPU_FORMAT_IS_UBWC(fmt) && drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2) return false; @@ -908,6 +914,82 @@ static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe, return true; } +static int dpu_plane_is_multirect_parallel_capable(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + const struct dpu_format *fmt, + uint32_t max_linewidth) +{ + return dpu_plane_is_multirect_capable(pipe, pipe_cfg, fmt) && + dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); +} + + +static int dpu_plane_try_multirect(struct dpu_plane_state *pstate, + struct dpu_plane_state *prev_pstate, + const struct dpu_format *fmt, + uint32_t max_linewidth) +{ + struct dpu_sw_pipe *pipe = &pstate->pipe; + struct dpu_sw_pipe *r_pipe = &pstate->r_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg; + struct dpu_sw_pipe *prev_pipe = &prev_pstate->pipe; + struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_pstate->pipe_cfg; + const struct dpu_format *prev_fmt = + to_dpu_format(msm_framebuffer_format(prev_pstate->base.fb)); + u16 max_tile_height = 1; + + if (prev_pstate->r_pipe.sspp != NULL || + prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE) + return false; + + if (!dpu_plane_is_multirect_capable(pipe, pipe_cfg, fmt) || + !dpu_plane_is_multirect_capable(prev_pipe, prev_pipe_cfg, prev_fmt) || + !(test_bit(DPU_SSPP_SMART_DMA_V1, &prev_pipe->sspp->cap->features) || + test_bit(DPU_SSPP_SMART_DMA_V2, &prev_pipe->sspp->cap->features))) + return false; + + if (DPU_FORMAT_IS_UBWC(fmt)) + max_tile_height = max(max_tile_height, fmt->tile_height); + + if (DPU_FORMAT_IS_UBWC(prev_fmt)) + max_tile_height = max(max_tile_height, prev_fmt->tile_height); + + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + r_pipe->sspp = NULL; + + if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && + dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) && + (pipe_cfg->dst_rect.x1 >= prev_pipe_cfg->dst_rect.x2 || + prev_pipe_cfg->dst_rect.x1 >= pipe_cfg->dst_rect.x2)) { + pipe->sspp = prev_pipe->sspp; + + pipe->multirect_index = DPU_SSPP_RECT_1; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + prev_pipe->multirect_index = DPU_SSPP_RECT_0; + prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + + return true; + } + + if (pipe_cfg->dst_rect.y1 >= prev_pipe_cfg->dst_rect.y2 + 2 * max_tile_height || + prev_pipe_cfg->dst_rect.y1 >= pipe_cfg->dst_rect.y2 + 2 * max_tile_height) { + pipe->sspp = prev_pipe->sspp; + + pipe->multirect_index = DPU_SSPP_RECT_1; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; + + prev_pipe->multirect_index = DPU_SSPP_RECT_0; + prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; + + return true; + } + + return false; +} + static int dpu_plane_atomic_check_pipes(struct drm_plane *plane, struct drm_atomic_state *state, const struct drm_crtc_state *crtc_state) @@ -1098,13 +1180,14 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane, static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, - struct drm_plane_state *plane_state) + struct drm_plane_state *plane_state, + struct drm_plane_state *prev_plane_state) { const struct drm_crtc_state *crtc_state = NULL; struct drm_plane *plane = plane_state->plane; struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; - struct dpu_plane_state *pstate; + struct dpu_plane_state *pstate, *prev_pstate; struct dpu_sw_pipe *pipe; struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; @@ -1117,6 +1200,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, plane_state->crtc); pstate = to_dpu_plane_state(plane_state); + prev_pstate = prev_plane_state ? to_dpu_plane_state(prev_plane_state) : NULL; pipe = &pstate->pipe; r_pipe = &pstate->r_pipe; pipe_cfg = &pstate->pipe_cfg; @@ -1137,19 +1221,27 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, max_linewidth = dpu_kms->catalog->caps->max_linewidth; - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); - if (!pipe->sspp) - return -ENODEV; - if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { - pipe->multirect_index = DPU_SSPP_RECT_SOLO; - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + if (!prev_pstate || + !dpu_plane_try_multirect(pstate, prev_pstate, fmt, max_linewidth)) { + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!pipe->sspp) + return -ENODEV; - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + r_pipe->sspp = NULL; + + pipe->multirect_index = DPU_SSPP_RECT_SOLO; + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; + } - r_pipe->sspp = NULL; } else { + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs); + if (!pipe->sspp) + return -ENODEV; + if (dpu_plane_is_multirect_parallel_capable(pipe, pipe_cfg, fmt, max_linewidth) && dpu_plane_is_multirect_parallel_capable(r_pipe, r_pipe_cfg, fmt, max_linewidth) && (test_bit(DPU_SSPP_SMART_DMA_V1, &pipe->sspp->cap->features) || @@ -1186,6 +1278,7 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state, { unsigned int i; int ret; + struct drm_plane_state *prev_plane_state = NULL; for (i = 0; i < num_planes; i++) { struct drm_plane_state *plane_state = states[i]; @@ -1195,9 +1288,12 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state, continue; ret = dpu_plane_virtual_assign_resources(crtc, global_state, - state, plane_state); + state, plane_state, + prev_plane_state); if (ret) break; + + prev_plane_state = plane_state; } return ret; From patchwork Thu Mar 14 00:02:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591997 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B22252CA9 for ; Thu, 14 Mar 2024 00:02:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374551; cv=none; b=hF88/zIZ1M/DLC+N0eOWCjgQ5u6tU1gNnTy0hfULgTCVTzXjzyOpErvXHmb0DqEOSlx1BmQ72lAYftLh6BFO/nZPpABHjXJmkpc5jDQgCcwWKKZ1FBS9CQcVLS0zfm/Gb6MohI7T8BzO5/LYtE0FPGlmj5y5TB0ZfmyGzRVeTYQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374551; c=relaxed/simple; bh=6ZwnFtVdtOactYP4jjDN2vjwZ76xsNeJ2fEShISJGW0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QB4ZTCJKLA+e6FrdqblNkaUzKlFpyUY0HkcAVxZnEkkGD4OYFqqAE6AUIAnWh7zXytRa8gpM57ncl/hWJRmQG8XqAYknRCTGmc3Uol9LyhXp6h1R8RxdSLsI2nUAVA6DboWLxdq+23u+nSRIBJd1Nxm+bgkqx/z/2Qy04iVbd5g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=G8qsFdjh; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G8qsFdjh" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-513c847c24dso616724e87.1 for ; Wed, 13 Mar 2024 17:02:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374548; x=1710979348; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2GfLHKk51yokbHFsUy9rW9NS1Ye+I79+zYu8xgq0djI=; b=G8qsFdjhE+3zXnCCflb+kaZBZk32sCelgK97HkajsFAeiFb1kZdz8xIluZ/Mwz0XOM OsVy9m7wktbrCrjai2joYNKZq4+8D11+/F46LW+ZVqbk8c20w0R6dsge5a8v8VkxGAZE Dmqq9M5avuxTwdfP3/fYr5tGNq4VD9J52cVXPSBVcBV/RnBJS1fdlvBwCZZ7/69sdPP+ F/BkVkxIrHTB0kmWmtjruxnSyJZ9Qh9vHEfOTHXJ4ojvyz/U245eXz9r/vQkPCWUxKtI TEnC8ly2TRPR2sgaudtwmXaWuPecG+I7BydoQSOPikk0O7M9AIbVI5WwyWQiLIe88OX4 iFiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374548; x=1710979348; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2GfLHKk51yokbHFsUy9rW9NS1Ye+I79+zYu8xgq0djI=; b=Uxp42/4haqhK/niJYMr4xAyC5SQw6IzqRILXsmCl/Yco+j7OA1aCaKnFOW7dnqGZry 1TE2LI7IsvRc+jS4qC3mnldwP0g15sOfPBGp4YqCFaXbIkE5uSOhmblY1OG61/Uq/lhP xniLsqZuIHf+ZoOHCDOEjSVjEnq3CZsZou1mPCMgyjEbpzHITeG70Opl+btR8wkQEPNF MMVqCDOXV+efsTbbrMEh8EdTzz4ttClf1bRSCkgO+eo4lv7yMk0f8pnmAESfk8JUEuYi /D9RyIoqrmM888y4BhGPgHOL4mX6T8V0wPDvt3R5NehDQkYx0LjUe6swfXKgvB+ziK4Z luvg== X-Forwarded-Encrypted: i=1; AJvYcCXfYafDaPfZDCmNRv68BQ0LCvnnbsb4+O/XB65I59iYT1eju7zVD2051mMZvFL/mSyUcszUABnjjaiRhDxseTvdbgiruH3IFrmxIsiXOQ== X-Gm-Message-State: AOJu0YxnjJ6znnD/qpIc0C3q16UStT4NFOox+7r3oyGLaMREpZJkTB8m ZFcMOGh6ReGyL69kH4B1jVMmqblZtkV95qtUDsopJSz9Hwoy9HEoykgHGD55nZMWu8umIYF+1cF B X-Google-Smtp-Source: AGHT+IG9l6RhjTY3xnURjv28dBhN0Wrft+Gt8dYaSXwfs+xcisrHiNLdYNeZ8YPsIqGLHokWYXweCQ== X-Received: by 2002:a19:ad02:0:b0:513:1385:c943 with SMTP id t2-20020a19ad02000000b005131385c943mr41947lfc.40.1710374547993; Wed, 13 Mar 2024 17:02:27 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:27 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 11/13] drm/msm/dpu: create additional virtual planes Date: Thu, 14 Mar 2024 02:02:14 +0200 Message-Id: <20240314000216.392549-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since we have enabled sharing of SSPP blocks between two planes, it is now possible to use twice as much planes as there are hardware SSPP blocks. Create additional overlay planes. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index becdd98f3c40..feb4d3bae0cf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -790,6 +790,18 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) primary_planes[primary_planes_idx++] = plane; } + if (dpu_use_virtual_planes) { + for (i = 0; i < catalog->sspp_count; i++) { + plane = dpu_plane_init_virtual(dev, DRM_PLANE_TYPE_OVERLAY, + (1UL << max_crtc_count) - 1); + if (IS_ERR(plane)) { + DPU_ERROR("dpu_plane_init failed\n"); + ret = PTR_ERR(plane); + return ret; + } + } + } + max_crtc_count = min(max_crtc_count, primary_planes_idx); /* Create one CRTC per encoder */ From patchwork Thu Mar 14 00:02:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591999 Received: from mail-lf1-f42.google.com (mail-lf1-f42.google.com [209.85.167.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 860FB5CBD for ; Thu, 14 Mar 2024 00:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374553; cv=none; b=KlFzDIjYuOqiP7MesCZ1TJ9CB+0pCZzPdsymNp3bPEKPE4p9hpwPwL2Mc0zt/Amo3+Sbd6H7ZdGfocDC1pnUaoCal/DwjTMSIwrSaSYia3QTjpG9h8pDv+uSVWcq60dol5+ddzXEnZ5f6Uy85C+YuS8QhC/WsrI+M1oFiVC+9KU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374553; c=relaxed/simple; bh=nnnDM+qoR3qJPNpNVPRWSJgz922JczbdcF0MsCeaFAE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H7EOWK7dJsZhTANOgijkP455yBscRRlgLz+aRr9hjjGJJ8IyJ6zKV//TyXU4Eee0TFIOin01aF6+K796T82jCHE+DXFjqYeNGxTxuSnYNPtAjgHFEt3eX2yta1UqB8jLv5dg0I9xkNlSnPDh5L32f5zN9+yGRj8GpcRN5o3BZ5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=mIeDXIFX; arc=none smtp.client-ip=209.85.167.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mIeDXIFX" Received: by mail-lf1-f42.google.com with SMTP id 2adb3069b0e04-513ccc70a6dso611922e87.1 for ; Wed, 13 Mar 2024 17:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374549; x=1710979349; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/NyH70gBQ0VtdOLbmQIMNFH5hau07nRJ94ccmDkurCw=; b=mIeDXIFXDge11BSk5QRl0YHxCeMz4xQcKrgb3rgRvzGwbP/HkXmWnU1I+ITKrTkte2 owdcomt/l5Dpjxwuj++MBx+IlGs6uTNduxLEzjR0AriMxxq1yHejkWj5QGZmHqUjG+dL 0yJM/iwFy/NSkABywIMEgFlZSzBt3H1T/YC3iC45skViSlXi6LdlE5yfWoy2yW7SXMUf opXV/CO/J/hP/AeRkT5ZS2L5Teb2p9QmvcyP5ZtsxdKvJbeyWrNusZuJqjJkKPb6flsi 3Am19+6znsHGAfUiz6tqOYg8V1TKRc3ghZZzF1tQl4h+6x4UkPtGtdM2TX6vOTawadUh dtIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374549; x=1710979349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/NyH70gBQ0VtdOLbmQIMNFH5hau07nRJ94ccmDkurCw=; b=ijNwdi0AmZrLYB5UIXvZbuJk4CNZ0l1b1BD/8MX9Sky3C0p/gF4V/undAuNxN0Tz52 1P4DY5BUzf2EZDSFdWxO9PGt0OXOLuBiUsxFqk5EfndaGuwb1DdFfGoCH8QwIclTcjhV Ma3UoyxQIwrfbpjjWvlJAdqw+VUp19MUNktRNQj2IRabJZeYJnKEEPPJ7kbOEWl7dmur oSyGCkcmwJQiPs3LT9/dJG4sjs7hzS+dv4d3WSMwSsS48dLUEoXK+L+OlBX3w8jctiyR 78yjEG2L1yT5pd+3CK1B6jpNNYUR/LrPz32ftECbojjwhyjB4ZumQNC4EnyYzmY5c9VI eOeg== X-Forwarded-Encrypted: i=1; AJvYcCVWzuVbPcEnM/NwnWJikkCvErQuq/cBKctljKIJAgXfC2TalTm+8FVqB1N2P0y+fk1Zmn730rBeTmPwwqCkR7W1qXg/AJwlsbVj4/r2fw== X-Gm-Message-State: AOJu0YyR7++TpatcpirE2czn2RkyT0c6FvddolXdCN2fVjFunCT8iG7I Kjc68e19R5r+TATS7KwLxjX70/pVDYtaike4ZGkpDXwZPFYcjmbQ9aZDzb0h4uQ= X-Google-Smtp-Source: AGHT+IFA3Dx5ozpGCZSWbfbx6oCBjyOBUbhWSz/XnE08IlR2N2DP/AnfA6vuDd6fnf0H52M4mNbo3A== X-Received: by 2002:a19:8c13:0:b0:513:c2e3:226e with SMTP id o19-20020a198c13000000b00513c2e3226emr57801lfd.8.1710374548954; Wed, 13 Mar 2024 17:02:28 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:28 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 12/13] drm/msm/dpu: allow sharing of blending stages Date: Thu, 14 Mar 2024 02:02:15 +0200 Message-Id: <20240314000216.392549-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 It is possible to slightly bend the limitations of the HW blender. If two rectangles are contiguous (like two rectangles of a single plane) they can be blended using a single LM blending stage, allowing one to blend more planes via a single LM. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 ++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 37 ++++++++++++++++++----- 2 files changed, 37 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 794c5643584f..fbbd7f635d04 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -445,6 +445,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, uint32_t lm_idx; bool bg_alpha_enable = false; + unsigned int stage_indices[DPU_STAGE_MAX] = {}; DECLARE_BITMAP(fetch_active, SSPP_MAX); memset(fetch_active, 0, sizeof(fetch_active)); @@ -469,7 +470,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); + &pstate->pipe, + stage_indices[pstate->stage]++, + stage_cfg); if (pstate->r_pipe.sspp) { set_bit(pstate->r_pipe.sspp->idx, fetch_active); @@ -477,7 +480,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->r_pipe, + stage_indices[pstate->stage]++, + stage_cfg); } /* blend config update */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 2e1c544efc4a..43dfe13eb298 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -827,13 +827,6 @@ static int dpu_plane_atomic_check_nopipe(struct drm_plane *plane, if (!new_plane_state->visible) return 0; - pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; - if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { - DPU_ERROR("> %d plane stages assigned\n", - pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); - return -EINVAL; - } - /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); @@ -971,6 +964,18 @@ static int dpu_plane_try_multirect(struct dpu_plane_state *pstate, prev_pipe->multirect_index = DPU_SSPP_RECT_0; prev_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; + if (pipe_cfg->dst_rect.y1 == prev_pipe_cfg->dst_rect.y1 && + pipe_cfg->dst_rect.y2 == prev_pipe_cfg->dst_rect.y2 && + pipe_cfg->dst_rect.x1 == prev_pipe_cfg->dst_rect.x2) { + pstate->stage = prev_pstate->stage; + } else if (pipe_cfg->dst_rect.y1 == prev_pipe_cfg->dst_rect.y1 && + pipe_cfg->dst_rect.y2 == prev_pipe_cfg->dst_rect.y2 && + pipe_cfg->dst_rect.x2 == prev_pipe_cfg->dst_rect.x1) { + pstate->stage = prev_pstate->stage; + pipe->multirect_index = DPU_SSPP_RECT_0; + prev_pipe->multirect_index = DPU_SSPP_RECT_1; + } + return true; } @@ -1080,6 +1085,13 @@ static int dpu_plane_atomic_check(struct drm_plane *plane, if (!new_plane_state->visible) return 0; + pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane stages assigned\n", + pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + return -EINVAL; + } + pipe->multirect_index = DPU_SSPP_RECT_SOLO; pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE; r_pipe->multirect_index = DPU_SSPP_RECT_SOLO; @@ -1221,6 +1233,11 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, max_linewidth = dpu_kms->catalog->caps->max_linewidth; + if (prev_pstate) + pstate->stage = prev_pstate->stage + 1; + else + pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos; + if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) { if (!prev_pstate || !dpu_plane_try_multirect(pstate, prev_pstate, fmt, max_linewidth)) { @@ -1267,6 +1284,12 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, } } + if (pstate->stage >= dpu_kms->catalog->caps->max_mixer_blendstages) { + DPU_ERROR("> %d plane stages assigned\n", + dpu_kms->catalog->caps->max_mixer_blendstages - DPU_STAGE_0); + return -EINVAL; + } + return dpu_plane_atomic_check_pipes(plane, state, crtc_state); } From patchwork Thu Mar 14 00:02:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13591998 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6256B5256 for ; Thu, 14 Mar 2024 00:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374553; cv=none; b=RZo0QXP5HQp3qkUJuI2k4pcW/xItfartox9Dz57K2cE1Fz5DgnPoxQJ8LO/3x9j2sU5jMSKSYVTvPOcf2rJUDiFfbAOa8VyhO3psnnV+x8EidaBLmi1Zo9j23o7pOapdvNvg5nb/CWDoXR5VsCXKULl8kjEcrICzSxrpvLFlY3c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1710374553; c=relaxed/simple; bh=sy4hXVNcsUTC75IEPue3Qh0lptrgkYLpP7TJaFh5TAE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SmnlZSqdfrOMCQAJ3vMHtCrAhENWHznSnLtFUMSPWtRUT2kB4dcFxvB1Gc6N17AnnO2KOvE358Vezi9Nu2AjZ9Rx6UGKNjXruJJmD7PfxpJy4U07ySiag7VSz4Xrkl+3S7HBv1e+Hz3QS9PX0Ko3VwoqEEtG3noh914PYED7iLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eml2S07q; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eml2S07q" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-51325c38d10so1406201e87.1 for ; Wed, 13 Mar 2024 17:02:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1710374549; x=1710979349; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PAS0pluJVyXsp6jVYhZTGdSQ3udV3IrTqeal2WShYuU=; b=eml2S07qBIIBFYtIh+XW+jDdyvua+BOpNxesR9O/5dV9ph7M2AfjayoFH07Qbqd9Cw FiucXMQIofA2S1iCOwd6bIpYlBwY1BP8XsKFqAVkSR4b/0QIVnuAXOo/NbidvoOoeW9+ reBmIaePRDpI3GgkDtQJ1RyRgBxdPs8MemM7kOklWVDnj/Vbgu8I2qjYaddwfh4bmGZC 61jdbIvQhsjbKw9B+0G0XGf8TbpEgTvvuM6QhfJzDIMrsUk3vZQuRyq9EyDw70njPsVR gg9TY5UxHm9ofttg64dBufimOZN6C+vjG17myC9MqFgfV6JMNiH6o1ppNDeghuV9Y03y 5+7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710374549; x=1710979349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PAS0pluJVyXsp6jVYhZTGdSQ3udV3IrTqeal2WShYuU=; b=cemmsQsNpT8JFCq+MZJr1frjGzQTr5Y3zr5dOptG0kdTp8vUi3MjnSvyFnkYdOeuOZ /bOHa5s+RCWibFVGGXpRF7CZ8Ns8D/T/vC+MsvcTlXH7ejdGDYBZy4e2P95vspeqbmZw HspKCD1xudO+JsgZd2ya/k5cRsFDcqNpoICPVIGfG39Sy8UTHn1MqU1kJCn0vNR/OM3m DrCn7bOw2BxrNI47qfPUNbowG3q0pP5I3AOUPmJ8PZGMuS3J5tOL+38U8MwKEG2ITB6J UINn6xQ/t3csRqCpIFmVK8lID1I3lFQOZKCoSNOcWe2uWo//qNxISdYmPGySQH/JHNzy qM+g== X-Forwarded-Encrypted: i=1; AJvYcCVEY3o5Y5/q2BYPo5SQPw/4sdS7DiRLLRRNSNqHeLJWzKHpozASyHBjXigLRBCI0DQKjmkmP4RSA8p7157h25ckHLh+lxg1Vw6fzUCV5g== X-Gm-Message-State: AOJu0YzKzewEhwxfm4QeTmusInuQaF7N1GcIZQzORTNTB+0kdpLxh4+R sYOlxJD823gXok0LMlGxCCD+H/77u8moNTuOKgM4tj13fWtZc9t2mXL4N3WO1Jg= X-Google-Smtp-Source: AGHT+IEdie8MACkhAj7NV2jIC3MvktUrsBN4mHTmfGXCaNUNwtX842uUnkuTTJA+Vg3GTr7xjJ8Yfg== X-Received: by 2002:a19:9109:0:b0:513:cdde:2f6 with SMTP id t9-20020a199109000000b00513cdde02f6mr308457lfd.32.1710374549755; Wed, 13 Mar 2024 17:02:29 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id x5-20020a19e005000000b00513360ebd22sm46111lfg.118.2024.03.13.17.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Mar 2024 17:02:29 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v4 13/13] drm/msm/dpu: include SSPP allocation state into the dumped state Date: Thu, 14 Mar 2024 02:02:16 +0200 Message-Id: <20240314000216.392549-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> References: <20240314000216.392549-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Make dpu_rm_print_state() also output the SSPP allocation state. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 7264a4d44a14..7997df340f72 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -890,4 +890,11 @@ void dpu_rm_print_state(struct drm_printer *p, dpu_rm_print_state_helper(p, rm->cdm_blk, global_state->cdm_to_enc_id); drm_puts(p, "\n"); + + drm_puts(p, "\tsspp="); + /* skip SSPP_NONE and start from the next index */ + for (i = SSPP_NONE + 1; i < ARRAY_SIZE(global_state->sspp_to_crtc_id); i++) + dpu_rm_print_state_helper(p, rm->hw_sspp[i] ? &rm->hw_sspp[i]->base : NULL, + global_state->sspp_to_crtc_id[i]); + drm_puts(p, "\n"); }