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Thu, 14 Mar 2024 06:12:26 +0000 Received: from BJXPR01MB0838.CHNPR01.prod.partner.outlook.cn ([fe80::a038:3f49:b470:9207]) by BJXPR01MB0838.CHNPR01.prod.partner.outlook.cn ([fe80::a038:3f49:b470:9207%4]) with mapi id 15.20.7386.017; Thu, 14 Mar 2024 06:12:26 +0000 From: Joshua Yeong To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, geert+renesas@glider.be, joshua.yeong@starfivetech.com, prabhakar.mahadev-lad.rj@bp.renesas.com, conor.dooley@microchip.com, alexghiti@rivosinc.com, evan@rivosinc.com, ajones@ventanamicro.com, heiko@sntech.de, guoren@kernel.org, uwu@icenowy.me, jszhang@kernel.org, conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, leyfoon.tan@starfivetech.com, jeeheng.sia@starfivetech.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 1/4] riscv: asm: vendorid_list: Add StarFive Technology to vendors list Date: Thu, 14 Mar 2024 14:12:02 +0800 Message-Id: <20240314061205.26143-2-joshua.yeong@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314061205.26143-1-joshua.yeong@starfivetech.com> References: <20240314061205.26143-1-joshua.yeong@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0015.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::9) To BJXPR01MB0838.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:1b::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0838:EE_|BJXPR01MB0711:EE_ X-MS-Office365-Filtering-Correlation-Id: 86e21904-5731-4c34-d9fd-08dc43edb85b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add StarFive Technology to the vendors list. Signed-off-by: Joshua Yeong --- arch/riscv/include/asm/vendorid_list.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h index e55407ace0c3..8c8f19ea505f 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -7,6 +7,7 @@ #define ANDESTECH_VENDOR_ID 0x31e #define SIFIVE_VENDOR_ID 0x489 +#define STARFIVE_VENDOR_ID 0x67e #define THEAD_VENDOR_ID 0x5b7 #endif From patchwork Thu Mar 14 06:12:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Yeong X-Patchwork-Id: 13592119 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4601DC54E5D for ; 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Thu, 14 Mar 2024 06:12:31 +0000 From: Joshua Yeong To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, geert+renesas@glider.be, joshua.yeong@starfivetech.com, prabhakar.mahadev-lad.rj@bp.renesas.com, conor.dooley@microchip.com, alexghiti@rivosinc.com, evan@rivosinc.com, ajones@ventanamicro.com, heiko@sntech.de, guoren@kernel.org, uwu@icenowy.me, jszhang@kernel.org, conor@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, leyfoon.tan@starfivetech.com, jeeheng.sia@starfivetech.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] riscv: errata: Add StarFive alternative ports Date: Thu, 14 Mar 2024 14:12:03 +0800 Message-Id: <20240314061205.26143-3-joshua.yeong@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240314061205.26143-1-joshua.yeong@starfivetech.com> References: <20240314061205.26143-1-joshua.yeong@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0015.CHNPR01.prod.partner.outlook.cn (2406:e500:c510::9) To BJXPR01MB0838.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:1b::23) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0838:EE_|BJXPR01MB0711:EE_ X-MS-Office365-Filtering-Correlation-Id: 9ae60e8c-ccdc-4ee9-3c21-08dc43edbb5e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Joshua Yeong --- arch/riscv/Kconfig.errata | 21 ++++++ arch/riscv/errata/Makefile | 1 + arch/riscv/errata/starfive/Makefile | 1 + arch/riscv/errata/starfive/errata.c | 95 ++++++++++++++++++++++++++++ arch/riscv/include/asm/alternative.h | 3 + arch/riscv/include/asm/errata_list.h | 5 ++ arch/riscv/kernel/alternative.c | 5 ++ 7 files changed, 131 insertions(+) create mode 100644 arch/riscv/errata/starfive/Makefile create mode 100644 arch/riscv/errata/starfive/errata.c diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index 910ba8837add..1438dd09533b 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -53,6 +53,16 @@ config ERRATA_SIFIVE_CIP_1200 If you don't know what to do here, say "Y". +config ERRATA_STARFIVE + bool "StarFive errata" + depends on RISCV_ALTERNATIVE + help + All StarFive errata Kconfig depend on this Kconfig. Disabling + this Kconfig will disable all StarFive errata. Please say "Y" + here if your platform uses StarFive CPU cores. + + Otherwise, please say "N" here to avoid unnecessary overhead. + config ERRATA_STARFIVE_JH7100 bool "StarFive JH7100 support" depends on ARCH_STARFIVE @@ -72,6 +82,17 @@ config ERRATA_STARFIVE_JH7100 Say "Y" if you want to support the BeagleV Starlight and/or StarFive VisionFive V1 boards. +config ERRATA_STARFIVE_CMO + bool "Apply StarFive cache management errata" + depends on ERRATA_STARFIVE && MMU + select RISCV_DMA_NONCOHERENT + default y + help + This will apply the cache management errata to handle the + non-standard handling on non-coherent operations on StarFive cores. + + If you don't know what to do here, say "Y". + config ERRATA_THEAD bool "T-HEAD errata" depends on RISCV_ALTERNATIVE diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile index 8a2739485123..4713a686b9f7 100644 --- a/arch/riscv/errata/Makefile +++ b/arch/riscv/errata/Makefile @@ -4,4 +4,5 @@ endif obj-$(CONFIG_ERRATA_ANDES) += andes/ obj-$(CONFIG_ERRATA_SIFIVE) += sifive/ +obj-$(CONFIG_ERRATA_STARFIVE) += starfive/ obj-$(CONFIG_ERRATA_THEAD) += thead/ diff --git a/arch/riscv/errata/starfive/Makefile b/arch/riscv/errata/starfive/Makefile new file mode 100644 index 000000000000..2d644e19caef --- /dev/null +++ b/arch/riscv/errata/starfive/Makefile @@ -0,0 +1 @@ +obj-y += errata.o diff --git a/arch/riscv/errata/starfive/errata.c b/arch/riscv/errata/starfive/errata.c new file mode 100644 index 000000000000..3ee360cd5e81 --- /dev/null +++ b/arch/riscv/errata/starfive/errata.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Erratas to be applied for StarFive CPU cores + * + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd. + * + * Author: Joshua Yeong + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define STARFIVE_JH8100_DUBHE90_MARCHID 0x80000000DB000090UL +#define STARFIVE_JH8100_DUBHE90_MIMPID 0x0000000020230930UL +#define STARFIVE_JH8100_DUBHE80_MARCHID 0x80000000DB000080UL +#define STARFIVE_JH8100_DUBHE80_MIMPID 0x0000000020230831UL +#define STARFIVE_JH8100_L3 0x40 + +static bool errata_probe_cmo(unsigned int stage, unsigned long arch_id, + unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_STARFIVE_CMO)) + return false; + + if ((arch_id != STARFIVE_JH8100_DUBHE90_MARCHID || + impid != STARFIVE_JH8100_DUBHE90_MIMPID) && + (arch_id != STARFIVE_JH8100_DUBHE80_MARCHID || + impid != STARFIVE_JH8100_DUBHE80_MIMPID)) + return false; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return false; + + riscv_cbom_block_size = STARFIVE_JH8100_L3; + riscv_noncoherent_supported(); + + return true; +} + +static u32 starfive_errata_probe(unsigned int stage, + unsigned long archid, unsigned long impid) +{ + u32 cpu_req_errata = 0; + + if (errata_probe_cmo(stage, archid, impid)) + cpu_req_errata |= BIT(ERRATA_STARFIVE_CMO); + + return cpu_req_errata; +} + +void __init_or_module starfive_errata_patch_func(struct alt_entry *begin, + struct alt_entry *end, + unsigned long archid, + unsigned long impid, + unsigned int stage) +{ + struct alt_entry *alt; + u32 cpu_apply_errata = 0; + u32 tmp; + u32 cpu_req_errata; + + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + cpu_req_errata = starfive_errata_probe(stage, archid, impid); + + for (alt = begin; alt < end; alt++) { + if (alt->vendor_id != STARFIVE_VENDOR_ID) + continue; + if (alt->patch_id >= ERRATA_STARFIVE_NUMBER) + continue; + + tmp = (1U << alt->patch_id); + if (cpu_req_errata & tmp) { + mutex_lock(&text_mutex); + patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt), + alt->alt_len); + mutex_unlock(&text_mutex); + cpu_apply_errata |= tmp; + } + } + + if (stage != RISCV_ALTERNATIVES_MODULE && + cpu_apply_errata != cpu_req_errata) { + pr_warn("WARNING: Missing StarFive errata patches! \n"); + } +} diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h index 3c2b59b25017..8f5e6883db97 100644 --- a/arch/riscv/include/asm/alternative.h +++ b/arch/riscv/include/asm/alternative.h @@ -51,6 +51,9 @@ void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); +void starfive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, + unsigned long archid, unsigned long impid, + unsigned int stage); void thead_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned long archid, unsigned long impid, unsigned int stage); diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index ea33288f8a25..1cd5ba3a1466 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -22,6 +22,11 @@ #define ERRATA_SIFIVE_NUMBER 2 #endif +#ifdef CONFIG_ERRATA_STARFIVE +#define ERRATA_STARFIVE_CMO 0 +#define ERRATA_STARFIVE_NUMBER 1 +#endif + #ifdef CONFIG_ERRATA_THEAD #define ERRATA_THEAD_PBMT 0 #define ERRATA_THEAD_PMU 1 diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c index 319a1da0358b..deedd4b76472 100644 --- a/arch/riscv/kernel/alternative.c +++ b/arch/riscv/kernel/alternative.c @@ -52,6 +52,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info cpu_mfr_info->patch_func = sifive_errata_patch_func; break; #endif +#ifdef CONFIG_ERRATA_STARFIVE + case STARFIVE_VENDOR_ID: + cpu_mfr_info->patch_func = starfive_errata_patch_func; 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Signed-off-by: Joshua Yeong --- drivers/cache/Kconfig | 9 ++ drivers/cache/Makefile | 1 + drivers/cache/starlink500_cache.c | 137 ++++++++++++++++++++++++++++++ 3 files changed, 147 insertions(+) create mode 100644 drivers/cache/starlink500_cache.c diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 9345ce4976d7..e215379f6a73 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -14,4 +14,13 @@ config SIFIVE_CCACHE help Support for the composable cache controller on SiFive platforms. +config STARLINK_500_CACHE + bool "StarLink-500 Cache controller" + depends on RISCV_DMA_NONCOHERENT + depends on ERRATA_STARFIVE + select RISCV_NONSTANDARD_CACHE_OPS + default y + help + Support for the StarLink-500 cache controller on StarFive platforms. + endmenu diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile index 7657cff3bd6c..c515eb5714ea 100644 --- a/drivers/cache/Makefile +++ b/drivers/cache/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o +obj-$(CONFIG_STARLINK_500_CACHE) += starlink500_cache.o diff --git a/drivers/cache/starlink500_cache.c b/drivers/cache/starlink500_cache.c new file mode 100644 index 000000000000..eaf8303cb086 --- /dev/null +++ b/drivers/cache/starlink500_cache.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Non-coherent cache functions for StarFive's StarLink-500 cache controller + * + * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd. + * + * Author: Joshua Yeong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define STARFIVE_SL500_CMO_FLUSH_START_ADDR 0x0 +#define STARFIVE_SL500_CMO_FLUSH_END_ADDR 0x8 +#define STARFIVE_SL500_CMO_FLUSH_CTL 0x10 +#define STARFIVE_SL500_CMO_CACHE_ALIGN 0x40 + +#define STARFIVE_SL500_ADDRESS_RANGE_MASK GENMASK(39, 0) +#define STARFIVE_SL500_FLUSH_CTL_MODE_MASK GENMASK(2, 1) +#define STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK BIT(0) + +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE 0 +#define STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE 1 +#define STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED 2 + +struct starfive_sl500_cache_priv { + void __iomem *base_addr; +}; + +static struct starfive_sl500_cache_priv starfive_sl500_cache_priv; + +static void starfive_sl500_cmo_flush_complete(void) +{ + ktime_t timeout; + + volatile void __iomem *_ctl = starfive_sl500_cache_priv.base_addr + + STARFIVE_SL500_CMO_FLUSH_CTL; + timeout = ktime_add_ms(ktime_get(), 5000); + + do { + if(!(ioread64(_ctl) & STARFIVE_SL500_FLUSH_CTL_ENABLE_MASK)) + return; + msleep(50); + } while (ktime_before(ktime_get(), timeout)); + + pr_err("StarFive CMO operation timeout\n"); + dump_stack(); +} + +void starfive_sl500_dma_cache_wback(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, + STARFIVE_SL500_FLUSH_CTL_CLEAN_SHARED), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); + + starfive_sl500_cmo_flush_complete(); +} + +void starfive_sl500_dma_cache_invalidate(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, + STARFIVE_SL500_FLUSH_CTL_MAKE_INVALIDATE), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); + + starfive_sl500_cmo_flush_complete(); +} + +void starfive_sl500_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size) +{ + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_START_ADDR); + writeq(FIELD_PREP(STARFIVE_SL500_ADDRESS_RANGE_MASK, paddr + size), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_END_ADDR); + + mb(); + writeq(FIELD_PREP(STARFIVE_SL500_FLUSH_CTL_MODE_MASK, + STARFIVE_SL500_FLUSH_CTL_CLEAN_INVALIDATE), + starfive_sl500_cache_priv.base_addr + STARFIVE_SL500_CMO_FLUSH_CTL); + + starfive_sl500_cmo_flush_complete(); +} + +static const struct riscv_nonstd_cache_ops starfive_sl500_cmo_ops = { + .wback = &starfive_sl500_dma_cache_wback, + .inv = &starfive_sl500_dma_cache_invalidate, + .wback_inv = &starfive_sl500_dma_cache_wback_inv, +}; + +static const struct of_device_id starfive_sl500_cache_ids[] = { + { .compatible = "starfive,starlink-500-cache" }, + { /* sentinel */ } +}; + +static int __init starfive_sl500_cache_init(void) +{ + struct device_node *np; + struct resource res; + int ret; + + np = of_find_matching_node(NULL, starfive_sl500_cache_ids); + if (!of_device_is_available(np)) + return -ENODEV; + + ret = of_address_to_resource(np, 0, &res); + if (ret) + return ret; + + starfive_sl500_cache_priv.base_addr = ioremap(res.start, resource_size(&res)); + if (!starfive_sl500_cache_priv.base_addr) + return -ENOMEM; + + riscv_noncoherent_register_cache_ops(&starfive_sl500_cmo_ops); + + return 0; +} +early_initcall(starfive_sl500_cache_init); From patchwork Thu Mar 14 06:12:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joshua Yeong X-Patchwork-Id: 13592122 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB2E7C54E6A for ; Thu, 14 Mar 2024 06:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Signed-off-by: Joshua Yeong --- .../cache/starfive,starlink-500-cache.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml diff --git a/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml new file mode 100644 index 000000000000..97ddf7db39e9 --- /dev/null +++ b/Documentation/devicetree/bindings/cache/starfive,starlink-500-cache.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive StarLink-500 Cache Controller + +maintainers: + - Joshua Yeong + +description: + StarFive's StarLink-500 controller manages cache shared between clusters of + CPU cores. The cache driver provides mechanism to perform invalidate and write + back functionality to the shared memory. + +allOf: + - $ref: /schemas/cache-controller.yaml# + +# We need a select here so we don't match all nodes with 'cache' +select: + properties: + compatible: + contains: + enum: + - starfive,starlink-500-cache + + required: + - compatible + +properties: + compatible: + items: + - const: starfive,starlink-500-cache + - const: cache + + reg: + maxItems: 1 + + cache-size: true + cache-sets: true + cache-block-size: true + cache-level: true + cache-unified: true + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + cache-controller@15000000 { + compatible = "starfive,starlink-500-cache", "cache"; + reg = <0x15000000 0x278>; + cache-block-size = <64>; + cache-level = <3>; + cache-sets = <8192>; + cache-size = <0x400000>; + cache-unified; + };