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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:09 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@linux.alibaba.com, bjorn@kernel.org, Andy Chiu , Paul Walmsley , Albert Ou , Andrew Jones , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Charlie Jenkins , Yangyu Chen Subject: [v2, 1/7] riscv: vector: add a comment when calling riscv_setup_vsize() Date: Thu, 14 Mar 2024 22:25:36 +0800 Message-Id: <20240314142542.19957-2-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072611_394950_AFA31DA4 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The function would fail when it detects the calling hart's vlen doesn't match the first one's. The boot hart is the first hart calling this function during riscv_fill_hwcap, so it is impossible to fail here. Add a comment about this behavior. Signed-off-by: Andy Chiu --- Changelog v2: - update the comment (Conor) --- arch/riscv/kernel/cpufeature.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 89920f84d0a3..36efc8e77ace 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -671,6 +671,10 @@ void __init riscv_fill_hwcap(void) } if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + /* + * This callsite can't fail here. It cannot fail when called on + * the boot hart. + */ riscv_v_setup_vsize(); /* * ISA string in device tree might have 'v' flag, but From patchwork Thu Mar 14 14:25:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13592491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62820C54E60 for ; Thu, 14 Mar 2024 14:26:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=zgZISaMbNZxBY+YM1Tx6AsNaJB0bP1arGDWw+9Gd30s=; b=eNJG2hPrBMeZESe1viFTeyAL5h FQlVq4BUVOnMuUBWqSDQDN7vaC0JmaV3aVQ8gZQrLnt/Khx5+oCZ/oTXIAzOC5ub1E75KqVqQVDmH FhVf15R2VDg3mLgdYqprxGlj0efNom1SX8hHVJN6TZmQUE/HSeFKPqOJ6Xj+JetK3KpKCXB5rTTwk Rtoc+iDUrRbZyPhWiZKuz24i4aOa93YSYtqXRLVDQE8GNs07e1dOPeJdZjd+fbsdkgTYQe1L9OyJU fiSpMu/fWQFgs3Y7X5xW9Sxgp9fFE1aSxDrLA/rArVZbeIhBmGOX4/cGaNGCNIf27xZmvv3X2r+6w vaji03LQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkm2H-0000000Ecxz-0J4g; Thu, 14 Mar 2024 14:26:21 +0000 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkm2D-0000000Ecw1-1HbR for linux-riscv@lists.infradead.org; Thu, 14 Mar 2024 14:26:19 +0000 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-6e6ca2ac094so848281b3a.0 for ; Thu, 14 Mar 2024 07:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710426375; x=1711031175; darn=lists.infradead.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=7eIfPx3uV8lsUcBcwLRk+DN38YJd7k8Ey98w9r/NPtI=; b=YLx2XcRuZBODq00ssd9nxocvQeHJSVWlihLeU5KZ0/HaHCJfGwthHj8ou69l9QhPR5 S+Zg0ZCjAGIn4VJZQxFCig3wZKdDSi0vnsbUqIjphgX+pI21/Nqsyvl9A5LQoBvrXiCM eudjOWOvJ3EOmP1BD95NJ+1encO1qVrYLPDFcaus/YPoAaX5nwDuW4fddptXy3zPpo2Q XuwHbao19LnpVO2DRHcwm9qV/LzJXMuAMBcrzeOTnlT32wYX+Zj0G4Fb0wj1ukMlUFg8 OjkXZz2ygQ13sNNr+tbNjf9YBBxZMpTdyI7TvqadvAptbzpMJeJCVQW7TG/pe8IYZB4y f6rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710426375; x=1711031175; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7eIfPx3uV8lsUcBcwLRk+DN38YJd7k8Ey98w9r/NPtI=; b=HU/+0dDMZUN9P7c29/DNo8o+jaIEgodz2mx8KXwa3FPR9M+kdEE5mHtBijlXyXZjkZ YZ3jGOCXpkNGYvMi1gL8Ey/s0YvDLiHOt26uEo5ovgrTNxxw+eYmAPcJT5RsBzE/B8At 5mmQ5F3rPXO4Hawhp0uEVy3WD0qHlIkI+1iyD+UFFzI6VaWuC0XuUW2ZOjMsegz9Tjor 3u03Ek9VvFcQxV3Iw3XHBxxhDTtbbi+Yb5rpBoZdhDwELq8Xh2FxlNpWbFbNd84IyReO cx48hqYxfgUIMimnLzMYHezJNbUMLMK90rzWQYV3unTN/TylYPPguNKv1f4iLNMfu3b+ 3Hfw== X-Gm-Message-State: AOJu0YyNe00Bl8Etx7tQN9a955kcPIJFVEgt18I4RW77BYjHUg0lilw/ EQosvbGWULwDm+YV8kbm4lqC00+MptcBMTZXKwufukK6fSWYnMit3k+gU1BB6IGRf6GqHWzYBvk t3U2ZoDtX10hZP7hbuCCX2iG5tl1NTOdYfMzHMa9vPdrch9tIKGt4Tgj1ObSLsQR2ZB/w/xU8d5 R+NfMMh2gmCuTUEDiCmG2aUP4XwjXRsWdISCdm8HUAThsbAc+oDCI5 X-Google-Smtp-Source: AGHT+IFizZlIHpNGvrFzHn28G3FaiiV4YCqk3TNVOVImN+g2L15NfZGO4KvUMXvY+PWwzV/iYeDXzA== X-Received: by 2002:a05:6a00:2d90:b0:6e6:9471:9f83 with SMTP id fb16-20020a056a002d9000b006e694719f83mr2383367pfb.8.1710426374793; Thu, 14 Mar 2024 07:26:14 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:14 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Subject: [v2, 2/7] riscv: smp: fail booting up smp if inconsistent vlen is detected Date: Thu, 14 Mar 2024 22:25:37 +0800 Message-Id: <20240314142542.19957-3-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072617_383487_DCD7D5B3 X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , guoren@linux.alibaba.com, Heiko Stuebner , Marc Zyngier , bjorn@kernel.org, Nam Cao , Samuel Holland , Vincent Chen , conor.dooley@microchip.com, Albert Ou , Guo Ren , Evan Green , Andy Chiu , Paul Walmsley , Frederik Haxel , greentime.hu@sifive.com, Sami Tolvanen , Andrew Jones MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently we only support Vector for SMP platforms, that is, all SMP cores have the same vlenb. If we happen to detect a mismatching vlen, it is better to just fail bootting it up to prevent further race/scheduling issues. Also, move .Lsecondary_park forward and chage `tail smp_callin` into a regular call in the early assembly. So a core would be parked right after a return from smp_callin. Note that a successful smp_callin does not return. Fixes: 7017858eb2d7 ("riscv: Introduce riscv_v_vsize to record size of Vector context") Reported-by: Conor Dooley Closes: https://lore.kernel.org/linux-riscv/20240228-vicinity-cornstalk-4b8eb5fe5730@spud/ Signed-off-by: Andy Chiu --- Changelog v2: - update commit message to explain asm code change (Conor) --- arch/riscv/kernel/head.S | 14 +++++++------- arch/riscv/kernel/smpboot.c | 14 +++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 4236a69c35cb..a158fa9f2656 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -165,9 +165,15 @@ secondary_start_sbi: #endif call .Lsetup_trap_vector scs_load_current - tail smp_callin + call smp_callin #endif /* CONFIG_SMP */ +.align 2 +.Lsecondary_park: + /* We lack SMP support or have too many harts, so park this hart */ + wfi + j .Lsecondary_park + .align 2 .Lsetup_trap_vector: /* Set trap vector to exception handler */ @@ -181,12 +187,6 @@ secondary_start_sbi: csrw CSR_SCRATCH, zero ret -.align 2 -.Lsecondary_park: - /* We lack SMP support or have too many harts, so park this hart */ - wfi - j .Lsecondary_park - SYM_CODE_END(_start) SYM_CODE_START(_start_kernel) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index cfbe4b840d42..1f86ee10192f 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -218,6 +218,15 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); + if (has_vector()) { + /* + * Return as early as possible so the hart with a mismatching + * vlen won't boot. + */ + if (riscv_v_setup_vsize()) + return; + } + /* All kernel threads share the same mm context. */ mmgrab(mm); current->active_mm = mm; @@ -230,11 +239,6 @@ asmlinkage __visible void smp_callin(void) numa_add_cpu(curr_cpuid); set_cpu_online(curr_cpuid, 1); - if (has_vector()) { - if (riscv_v_setup_vsize()) - elf_hwcap &= ~COMPAT_HWCAP_ISA_V; - } - riscv_user_isa_enable(); /* From patchwork Thu Mar 14 14:25:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13592493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 343A5C54E68 for ; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:18 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@linux.alibaba.com, bjorn@kernel.org, Andy Chiu , Paul Walmsley , Albert Ou , Andrew Jones , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Charlie Jenkins , Yangyu Chen Subject: [v2, 3/7] riscv: cpufeature: call match_isa_ext() for single-letter extensions Date: Thu, 14 Mar 2024 22:25:38 +0800 Message-Id: <20240314142542.19957-4-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072621_151217_30ABCCAB X-CRM114-Status: UNSURE ( 9.61 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Single-letter extensions may also imply multiple subextensions. For example, Vector extension implies zve64d, and zve64d implies zve64f. Extension parsing for "riscv,isa-extensions" has the ability to resolve the dependency by calling match_isa_ext(). This patch makes deprecated parser call the same function for single letter extensions. Signed-off-by: Andy Chiu --- arch/riscv/kernel/cpufeature.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 36efc8e77ace..d836241a1f11 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -470,6 +470,10 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc if (unlikely(ext_err)) continue; + + for (int i = 0; i < riscv_isa_ext_count; i++) + match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); + if (!ext_long) { int nr = tolower(*ext) - 'a'; @@ -477,9 +481,6 @@ static void __init riscv_parse_isa_string(unsigned long *this_hwcap, struct risc *this_hwcap |= isa2hwcap[nr]; set_bit(nr, isainfo->isa); } - } else { - for (int i = 0; i < riscv_isa_ext_count; i++) - match_isa_ext(&riscv_isa_ext[i], ext, ext_end, isainfo); } } } From patchwork Thu Mar 14 14:25:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13592495 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D39D3C54E60 for ; Thu, 14 Mar 2024 14:26:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wMpmSKobOm2ran08LrL+Tv+yRdyFWZDDnCTGIJE0BRM=; b=plYxl0IuSFaAJa 3ERoWvH5lWCj+r+3jhlwwbraobh7zyt7q8atpzq55/uCy2zAC12R75rDow1kvy/yp3njiJTwbk09q ekmxY4vw12rU/qQbdZOZv2bUDkiutuHQCc04loXMZLWM3HEndC1yhKlp8JBqNDnc/Ac0290yxJwrT Kdp0d6+Udyi9br0AZAhFNBw5sdqjat3focVfBuj6UndWAYgeSeWL+GxGjhDex06i22lhv+XrnH+s0 Ixe+wBGIaJUpgD3Lg93XUUQDIXJkRGZPc7SePb87xQNqVoH6WuHfot/WJG9Itz1V6Fr1Flq3bE9Mf F095XRtCoUmkz+4Emq3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkm2O-0000000Ed2a-4BHI; Thu, 14 Mar 2024 14:26:29 +0000 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkm2L-0000000Eczu-2YF7 for linux-riscv@lists.infradead.org; Thu, 14 Mar 2024 14:26:27 +0000 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6e6ee9e3cffso284882b3a.1 for ; Thu, 14 Mar 2024 07:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1710426383; x=1711031183; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PNstRg6daczAXrALw7Zi6GYP2+HGLqW/5dmPLPDSUJY=; b=njTg6ZIZM30iuJNtCXreI0C47JhYACAv0vECvtKHDTeZ4MyYK0dLZWXJ8FS2dEyMiB b1Y1Qlc15aIn0N+6I0Mh9QYC+NEh6/OW9c3bgerBGauKZArmIE+53TQO6MqtaNCPTkLi NaZZoJktIPVPGHnAh5o53q0VM/TyrCzuZo8DwKmiuLjAEf4+TzM3bURNSCbxXw721g09 E5d2UMsqVpk1Q/KsxtLgFDcwbWNYDhAu2Wxx+eHRMgE5DQCZAqTZVn759ckBP96aArRv n3LaUWxW9MKEltTIIHw7HId0xiwOqMwqjX2YbpSI3Bv6TPfX+8jIlA3dsBecFtRRvtIH NSKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1710426383; x=1711031183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PNstRg6daczAXrALw7Zi6GYP2+HGLqW/5dmPLPDSUJY=; b=DF7GHfVs4FLQHcJk+GaLsk1wWCCnvcitwlIa/Z6CYUgneMoTrWV5GGhFvw1eIAY/S1 GCbpUrGHf1uvbUVMXAYryp7HhGs6VdEhGp7n8wagANGZIMnTWtccoeo+5vo4AaAjITAI j/B6a7fH//CrDwm3u8vvyKwn1jRWxZTT8aIcTFoEtCdgvuqAGQ10iiV/21a6NaPItNxH Fep22wWoIcVeBqlywBypeLPkLvDeVvO5QzxckpPSLr5cPL16A5ENy6GVXHU0yyXoldpI xNVCGZveYZ4eILwH94N10Bga5Lkx6QjRUUA2Irm7qTB20AzzUwF8kVF8Y4WkpVrrdDLx y/lA== X-Gm-Message-State: AOJu0YypFb+EHvqrk4UmQ9dfwZhZl1JSmje3pMLz3jtAoBJh8UvOk37/ fEEw3JDYJ/nf3ex+KLhCuhKblaeMFCkg4E4YCjNs6jeD612uYAsx47pjWLQJkKBWwk4b8nzWIfQ aeTP+MacRjlCNW5FafnI/QR55Z1VanWve09TWeqyH1NvqD3Teo6OLMbe2zangYd7AtGK/ZlRqOo N0bwd8jr1+RH24We5Y1WWVuNI1AT2KvgkBBxjtUNbWGYyDZiE57fqr X-Google-Smtp-Source: AGHT+IHCOBS+cXi7w9ic2iD6x5GoItCXB4+H5HlhuhP/fax9v+yBM5aNMDIglPLe+3Txu8Gb4LL+kA== X-Received: by 2002:a05:6a00:3cc5:b0:6e6:30ef:b7e9 with SMTP id ln5-20020a056a003cc500b006e630efb7e9mr2995239pfb.16.1710426382983; Thu, 14 Mar 2024 07:26:22 -0700 (PDT) Received: from hsinchu26.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:22 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@linux.alibaba.com, bjorn@kernel.org, Andy Chiu , Paul Walmsley , Albert Ou , Andrew Jones , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Evan Green , Anup Patel , Xiao Wang , Charlie Jenkins , Yangyu Chen Subject: [v2, 4/7] riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection Date: Thu, 14 Mar 2024 22:25:39 +0800 Message-Id: <20240314142542.19957-5-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072625_836138_0AB1717E X-CRM114-Status: GOOD ( 12.34 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Multiple Vector subextensions are added. Also, the patch takes care of the dependencies of Vector subextensions by macro expansions. So, if some "embedded" platform only reports "zve64f" on the ISA string, the parser is able to expand it to zve32x zve32f zve64x and zve64f. Signed-off-by: Andy Chiu --- Changelog v2: - remove the extension itself from its isa_exts[] list (Clément) - use riscv_zve64d_exts for v's extension list (Samuel) --- arch/riscv/include/asm/hwcap.h | 5 +++++ arch/riscv/kernel/cpufeature.c | 36 +++++++++++++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 5340f818746b..24efea44f1ab 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,6 +80,11 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 +#define RISCV_ISA_EXT_ZVE32X 74 +#define RISCV_ISA_EXT_ZVE32F 75 +#define RISCV_ISA_EXT_ZVE64X 76 +#define RISCV_ISA_EXT_ZVE64F 77 +#define RISCV_ISA_EXT_ZVE64D 78 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d836241a1f11..ddac25a5fe3e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -201,6 +201,35 @@ static const unsigned int riscv_zvbb_exts[] = { RISCV_ISA_EXT_ZVKB }; +#define RISCV_ISA_EXT_ZVE32F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE32X, + +#define RISCV_ISA_EXT_ZVE64F_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64X, \ + RISCV_ISA_EXT_ZVE32F, \ + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST + +#define RISCV_ISA_EXT_ZVE64D_IMPLY_LIST \ + RISCV_ISA_EXT_ZVE64F, \ + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST + +static const unsigned int riscv_zve32f_exts[] = { + RISCV_ISA_EXT_ZVE32F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64f_exts[] = { + RISCV_ISA_EXT_ZVE64F_IMPLY_LIST +}; + +static const unsigned int riscv_zve64d_exts[] = { + RISCV_ISA_EXT_ZVE64D_IMPLY_LIST +}; + +static const unsigned int riscv_zve64x_exts[] = { + RISCV_ISA_EXT_ZVE32X, + RISCV_ISA_EXT_ZVE64X +}; + /* * The canonical order of ISA extension names in the ISA string is defined in * chapter 27 of the unprivileged specification. @@ -248,7 +277,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_DATA(c, RISCV_ISA_EXT_c), - __RISCV_ISA_EXT_DATA(v, RISCV_ISA_EXT_v), + __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_zve64d_exts), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), @@ -283,6 +312,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), + __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), + __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), + __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), + __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), From patchwork Thu Mar 14 14:25:40 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:25 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@linux.alibaba.com, bjorn@kernel.org, Andy Chiu , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou Subject: [v2, 5/7] dt-bindings: riscv: add Zve32[xf] Zve64[xfd] ISA extension description Date: Thu, 14 Mar 2024 22:25:40 +0800 Message-Id: <20240314142542.19957-6-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072626_696182_AE8CD356 X-CRM114-Status: UNSURE ( 7.04 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add description for Zve32x Zve32f Zve64x Zve64f Zve64d ISA extensions. Signed-off-by: Andy Chiu --- Changelog v2: - new patch since v2 --- .../devicetree/bindings/riscv/extensions.yaml | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 63d81dc895e5..6ae50d1227d1 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -381,6 +381,36 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zve32f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve32x + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64x + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64f + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + + - const: zve64d + description: + The standard Zve32f extension for embedded processors, as ratified + in commit 6f702a2 ("Vector extensions are now ratified") of + riscv-v-spec. + - const: zvfh description: The standard Zvfh extension for vectored half-precision From patchwork Thu Mar 14 14:25:41 2024 Content-Type: text/plain; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:33 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Cc: greentime.hu@sifive.com, conor.dooley@microchip.com, guoren@linux.alibaba.com, bjorn@kernel.org, Andy Chiu , Jonathan Corbet , Paul Walmsley , Albert Ou , Evan Green , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Heiko Stuebner , Andrew Jones , Costa Shulyupin Subject: [v2, 6/7] riscv: hwprobe: add zve Vector subextensions into hwprobe interface Date: Thu, 14 Mar 2024 22:25:41 +0800 Message-Id: <20240314142542.19957-7-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072636_404487_2DDC2EF5 X-CRM114-Status: GOOD ( 10.66 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The following Vector subextensions for "embedded" platforms are added into RISCV_HWPROBE_KEY_IMA_EXT_0: - ZVE32X - ZVE32F - ZVE64X - ZVE64F - ZVE64D Extensions end with X mean the platform don't have a Vector FPU. Extensions end with F/D mean whether single (F) or double (D) precision Vector operation is supported. The number 32 or 64 follows from ZVE tells the maximum element length. Signed-off-by: Andy Chiu Reviewed-by: Clément Léger --- Changelog v2: - zve* extensions in hwprobe depends on whether kernel supports v, so include them after has_vector(). Fix a typo. (Clément) --- Documentation/arch/riscv/hwprobe.rst | 15 +++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 5 +++++ arch/riscv/kernel/sys_hwprobe.c | 5 +++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index b2bcc9eed9aa..d0b02e012e5d 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -188,6 +188,21 @@ The following keys are defined: manual starting from commit 95cf1f9 ("Add changes requested by Ved during signoff") + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is + supported, as defined by version 1.0 of the RISC-V Vector extension manual. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 9f2a8e3ff204..b9a0876e969f 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -59,6 +59,11 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) +#define RISCV_HWPROBE_EXT_ZVE32X (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZVE32F (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZVE64X (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZVE64F (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZVE64D (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index a7c56b41efd2..db7495001f27 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -113,6 +113,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZICOND); if (has_vector()) { + EXT_KEY(ZVE32X); + EXT_KEY(ZVE32F); + EXT_KEY(ZVE64X); + EXT_KEY(ZVE64F); + EXT_KEY(ZVE64D); EXT_KEY(ZVBB); EXT_KEY(ZVBC); EXT_KEY(ZVKB); From patchwork Thu Mar 14 14:25:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Chiu X-Patchwork-Id: 13592499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 96670C54E67 for ; Thu, 14 Mar 2024 14:27:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id y9-20020a62f249000000b006e6854d45afsm1556435pfl.97.2024.03.14.07.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Mar 2024 07:26:51 -0700 (PDT) From: Andy Chiu To: linux-riscv@lists.infradead.org, palmer@dabbelt.com Subject: [v2, 7/7] riscv: vector: adjust minimum Vector requirement to ZVE32X Date: Thu, 14 Mar 2024 22:25:42 +0800 Message-Id: <20240314142542.19957-8-andy.chiu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240314142542.19957-1-andy.chiu@sifive.com> References: <20240314142542.19957-1-andy.chiu@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_072653_238091_47B0B086 X-CRM114-Status: GOOD ( 24.67 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Joel Granados , guoren@linux.alibaba.com, Heiko Stuebner , Jisheng Zhang , Eric Biggers , =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= , Yangyu Chen , conor.dooley@microchip.com, Guo Ren , Mathis Salmen , Haorong Lu , Nick Knight , Anup Patel , greentime.hu@sifive.com, Andrew Jones , Albert Ou , Jerry Shih , Alexandre Ghiti , Charlie Jenkins , Lad Prabhakar , Xiao Wang , Al Viro , Paul Walmsley , =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Samuel Holland , Han-Kuan Chen , Vincent Chen , bjorn@kernel.org, Evan Green , Andy Chiu , Aurelien Jarno MIME-Version: 1.0 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Make has_vector take one argument. This argument represents the minimum Vector subextension that the following Vector actions assume. Also, change riscv_v_first_use_handler(), and boot code that calls riscv_v_setup_vsize() to accept the minimum Vector sub-extension, ZVE32X. Most kernel/user interfaces requires minimum of ZVE32X. Thus, programs compiled and run with ZVE32X should be supported by the kernel on most aspects. This includes context-switch, signal, ptrace, prctl, and hwprobe. One exception is that ELF_HWCAP returns 'V' only if full V is supported on the platform. This means that the system without a full V must not rely on ELF_HWCAP to tell whether it is allowable to execute Vector without first invoking a prctl() check. Signed-off-by: Andy Chiu Acked-by: Joel Granados --- Changelog v2: - update the comment in hwprobe. --- arch/riscv/include/asm/switch_to.h | 2 +- arch/riscv/include/asm/vector.h | 21 ++++++++++++++------- arch/riscv/include/asm/xor.h | 2 +- arch/riscv/kernel/cpufeature.c | 5 ++++- arch/riscv/kernel/kernel_mode_vector.c | 4 ++-- arch/riscv/kernel/process.c | 4 ++-- arch/riscv/kernel/signal.c | 6 +++--- arch/riscv/kernel/smpboot.c | 2 +- arch/riscv/kernel/sys_hwprobe.c | 8 ++++++-- arch/riscv/kernel/vector.c | 15 +++++++++------ arch/riscv/lib/uaccess.S | 2 +- 11 files changed, 44 insertions(+), 27 deletions(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..df1adf196c4f 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -78,7 +78,7 @@ do { \ struct task_struct *__next = (next); \ if (has_fpu()) \ __switch_to_fpu(__prev, __next); \ - if (has_vector()) \ + if (has_vector(ZVE32X)) \ __switch_to_vector(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 731dcd0ed4de..b96750493dfb 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -18,6 +18,7 @@ #include #include #include +#include extern unsigned long riscv_v_vsize; int riscv_v_setup_vsize(void); @@ -35,10 +36,16 @@ static inline u32 riscv_v_flags(void) return READ_ONCE(current->thread.riscv_v_flags); } -static __always_inline bool has_vector(void) -{ - return riscv_has_extension_unlikely(RISCV_ISA_EXT_v); -} +#define has_vector(VEXT) \ +({ \ + static_assert(RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32X || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE32F || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64X || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64F || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_ZVE64D || \ + RISCV_ISA_EXT_##VEXT == RISCV_ISA_EXT_v); \ + riscv_has_extension_unlikely(RISCV_ISA_EXT_##VEXT); \ +}) static inline void __riscv_v_vstate_clean(struct pt_regs *regs) { @@ -131,7 +138,7 @@ static inline void __riscv_v_vstate_restore(struct __riscv_v_ext_state *restore_ riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vle8.v v0, (%1)\n\t" "add %1, %1, %0\n\t" @@ -153,7 +160,7 @@ static inline void __riscv_v_vstate_discard(void) riscv_v_enable(); asm volatile ( ".option push\n\t" - ".option arch, +v\n\t" + ".option arch, +zve32x\n\t" "vsetvli %0, x0, e8, m8, ta, ma\n\t" "vmv.v.i v0, -1\n\t" "vmv.v.i v8, -1\n\t" @@ -267,7 +274,7 @@ bool riscv_v_vstate_ctrl_user_allowed(void); struct pt_regs; static inline int riscv_v_setup_vsize(void) { return -EOPNOTSUPP; } -static __always_inline bool has_vector(void) { return false; } +static __always_inline bool has_vector(unsigned long min_sub_ext) { return false; } static inline bool riscv_v_first_use_handler(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_query(struct pt_regs *regs) { return false; } static inline bool riscv_v_vstate_ctrl_user_allowed(void) { return false; } diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h index 96011861e46b..46042ef5a2f7 100644 --- a/arch/riscv/include/asm/xor.h +++ b/arch/riscv/include/asm/xor.h @@ -61,7 +61,7 @@ static struct xor_block_template xor_block_rvv = { do { \ xor_speed(&xor_block_8regs); \ xor_speed(&xor_block_32regs); \ - if (has_vector()) { \ + if (has_vector(ZVE32X)) { \ xor_speed(&xor_block_rvv);\ } \ } while (0) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index ddac25a5fe3e..475de9efb185 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -705,12 +705,15 @@ void __init riscv_fill_hwcap(void) elf_hwcap &= ~COMPAT_HWCAP_ISA_F; } - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_ZVE32X)) { /* * This callsite can't fail here. It cannot fail when called on * the boot hart. */ riscv_v_setup_vsize(); + } + + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { /* * ISA string in device tree might have 'v' flag, but * CONFIG_RISCV_ISA_V is disabled in kernel. diff --git a/arch/riscv/kernel/kernel_mode_vector.c b/arch/riscv/kernel/kernel_mode_vector.c index 6afe80c7f03a..0d4d1a03d1c7 100644 --- a/arch/riscv/kernel/kernel_mode_vector.c +++ b/arch/riscv/kernel/kernel_mode_vector.c @@ -208,7 +208,7 @@ void kernel_vector_begin(void) { bool nested = false; - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; BUG_ON(!may_use_simd()); @@ -236,7 +236,7 @@ EXPORT_SYMBOL_GPL(kernel_vector_begin); */ void kernel_vector_end(void) { - if (WARN_ON(!has_vector())) + if (WARN_ON(!has_vector(ZVE32X))) return; riscv_v_disable(); diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 92922dbd5b5c..919e72f9fff6 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -178,7 +178,7 @@ void flush_thread(void) void arch_release_task_struct(struct task_struct *tsk) { /* Free the vector context of datap. */ - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_free(tsk); } @@ -225,7 +225,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) p->thread.s[0] = 0; } p->thread.riscv_v_flags = 0; - if (has_vector()) + if (has_vector(ZVE32X)) riscv_v_thread_alloc(p); p->thread.ra = (unsigned long)ret_from_fork; p->thread.sp = (unsigned long)childregs; /* kernel sp */ diff --git a/arch/riscv/kernel/signal.c b/arch/riscv/kernel/signal.c index 501e66debf69..a96e6e969a3f 100644 --- a/arch/riscv/kernel/signal.c +++ b/arch/riscv/kernel/signal.c @@ -188,7 +188,7 @@ static long restore_sigcontext(struct pt_regs *regs, return 0; case RISCV_V_MAGIC: - if (!has_vector() || !riscv_v_vstate_query(regs) || + if (!has_vector(ZVE32X) || !riscv_v_vstate_query(regs) || size != riscv_v_sc_size) return -EINVAL; @@ -210,7 +210,7 @@ static size_t get_rt_frame_size(bool cal_all) frame_size = sizeof(*frame); - if (has_vector()) { + if (has_vector(ZVE32X)) { if (cal_all || riscv_v_vstate_query(task_pt_regs(current))) total_context_size += riscv_v_sc_size; } @@ -283,7 +283,7 @@ static long setup_sigcontext(struct rt_sigframe __user *frame, if (has_fpu()) err |= save_fp_state(regs, &sc->sc_fpregs); /* Save the vector state. */ - if (has_vector() && riscv_v_vstate_query(regs)) + if (has_vector(ZVE32X) && riscv_v_vstate_query(regs)) err |= save_v_state(regs, (void __user **)&sc_ext_ptr); /* Write zero to fp-reserved space and check it on restore_sigcontext */ err |= __put_user(0, &sc->sc_extdesc.reserved); diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 1f86ee10192f..4eb36d75f091 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -218,7 +218,7 @@ asmlinkage __visible void smp_callin(void) struct mm_struct *mm = &init_mm; unsigned int curr_cpuid = smp_processor_id(); - if (has_vector()) { + if (has_vector(ZVE32X)) { /* * Return as early as possible so the hart with a mismatching * vlen won't boot. diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index db7495001f27..839f912a2cfd 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -69,7 +69,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, if (riscv_isa_extension_available(NULL, c)) pair->value |= RISCV_HWPROBE_IMA_C; - if (has_vector()) + if (has_vector(v)) pair->value |= RISCV_HWPROBE_IMA_V; /* @@ -112,7 +112,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZACAS); EXT_KEY(ZICOND); - if (has_vector()) { + /* + * Vector crypto and ZVE* extensions are supported only if + * kernel has minimum V support of ZVE32X. + */ + if (has_vector(ZVE32X)) { EXT_KEY(ZVE32X); EXT_KEY(ZVE32F); EXT_KEY(ZVE64X); diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c index 6727d1d3b8f2..e8a47fa72351 100644 --- a/arch/riscv/kernel/vector.c +++ b/arch/riscv/kernel/vector.c @@ -53,7 +53,7 @@ int riscv_v_setup_vsize(void) void __init riscv_v_setup_ctx_cache(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return; riscv_v_user_cachep = kmem_cache_create_usercopy("riscv_vector_ctx", @@ -173,8 +173,11 @@ bool riscv_v_first_use_handler(struct pt_regs *regs) u32 __user *epc = (u32 __user *)regs->epc; u32 insn = (u32)regs->badaddr; + if (!has_vector(ZVE32X)) + return false; + /* Do not handle if V is not supported, or disabled */ - if (!(ELF_HWCAP & COMPAT_HWCAP_ISA_V)) + if (!riscv_v_vstate_ctrl_user_allowed()) return false; /* If V has been enabled then it is not the first-use trap */ @@ -213,7 +216,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) bool inherit; int cur, next; - if (!has_vector()) + if (!has_vector(ZVE32X)) return; next = riscv_v_ctrl_get_next(tsk); @@ -235,7 +238,7 @@ void riscv_v_vstate_ctrl_init(struct task_struct *tsk) long riscv_v_vstate_ctrl_get_current(void) { - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; return current->thread.vstate_ctrl & PR_RISCV_V_VSTATE_CTRL_MASK; @@ -246,7 +249,7 @@ long riscv_v_vstate_ctrl_set_current(unsigned long arg) bool inherit; int cur, next; - if (!has_vector()) + if (!has_vector(ZVE32X)) return -EINVAL; if (arg & ~PR_RISCV_V_VSTATE_CTRL_MASK) @@ -296,7 +299,7 @@ static struct ctl_table riscv_v_default_vstate_table[] = { static int __init riscv_v_sysctl_init(void) { - if (has_vector()) + if (has_vector(ZVE32X)) if (!register_sysctl("abi", riscv_v_default_vstate_table)) return -EINVAL; return 0; diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index bc22c078aba8..bbe143bb32a0 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -14,7 +14,7 @@ SYM_FUNC_START(__asm_copy_to_user) #ifdef CONFIG_RISCV_ISA_V - ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V) + ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_ZVE32X, CONFIG_RISCV_ISA_V) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy tail enter_vector_usercopy