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Thu, 21 Feb 2019 18:24:52 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 01/14] arm64: dts: imx8qxp: orginize dts in subsystems Thread-Topic: [PATCH 01/14] arm64: dts: imx8qxp: orginize dts in subsystems Thread-Index: AQHUyhK8LGNIJ2f64kmJFSFcpcpObA== Date: Thu, 21 Feb 2019 18:24:51 +0000 Message-ID: <1550773093-13349-2-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: bbdd087a-4bc6-4018-dd23-08d69829de8b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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So let's re-orginize them into subsystems in device tree as well for the possible reuse of the common part. Note, as there's still no devices of hsio subsys, so removed it first instead of creating a subsys headfile with no devices. They will be added back when new devices added. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 75 +++++ arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 95 +++++++ arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 124 ++++++++ arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 29 ++ arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 25 ++ arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 57 ++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 311 +-------------------- 7 files changed, 412 insertions(+), 304 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi new file mode 100644 index 0000000..f6f2b94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +adma_subsys: bus@59000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x59000000 0x0 0x59000000 0x2000000>; + + adma_lpcg: clock-controller@59000000 { + reg = <0x59000000 0x2000000>; + #clock-cells = <1>; + }; + + adma_lpuart0: serial@5a060000 { + reg = <0x5a060000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + adma_i2c0: i2c@5a800000 { + reg = <0x5a800000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + adma_i2c1: i2c@5a810000 { + reg = <0x5a810000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + adma_i2c2: i2c@5a820000 { + reg = <0x5a820000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + adma_i2c3: i2c@5a830000 { + reg = <0x5a830000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi new file mode 100644 index 0000000..ac5131d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +conn_subsys: bus@5b000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + + conn_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + usdhc1: mmc@5b010000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b010000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_0>; + status = "disabled"; + }; + + usdhc2: mmc@5b020000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b020000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: mmc@5b030000 { + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x5b030000 0x10000>; + clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, + <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_SDHC_2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + reg = <0x5b040000 0x10000>; + interrupts = , + , + , + ; + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_0>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + reg = <0x5b050000 0x10000>; + interrupts = , + , + , + ; + clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + power-domains = <&pd IMX_SC_R_ENET_1>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi new file mode 100644 index 0000000..1c6ba8d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +lsio_subsys: bus@5d000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + + lsio_lpcg: clock-controller@5d400000 { + reg = <0x5d400000 0x400000>; + #clock-cells = <1>; + }; + + lsio_mu0: mailbox@5d1b0000 { + reg = <0x5d1b0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu1: mailbox@5d1c0000 { + reg = <0x5d1c0000 0x10000>; + interrupts = ; + #mbox-cells = <2>; + }; + + lsio_mu3: mailbox@5d1e0000 { + reg = <0x5d1e0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_mu4: mailbox@5d1f0000 { + reg = <0x5d1f0000 0x10000>; + interrupts = ; + #mbox-cells = <0>; + status = "disabled"; + }; + + lsio_gpio0: gpio@5d080000 { + reg = <0x5d080000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_0>; + }; + + lsio_gpio1: gpio@5d090000 { + reg = <0x5d090000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_1>; + }; + + lsio_gpio2: gpio@5d0a0000 { + reg = <0x5d0a0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_2>; + }; + + lsio_gpio3: gpio@5d0b0000 { + reg = <0x5d0b0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_3>; + }; + + lsio_gpio4: gpio@5d0c0000 { + reg = <0x5d0c0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_4>; + }; + + lsio_gpio5: gpio@5d0d0000 { + reg = <0x5d0d0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_5>; + }; + + lsio_gpio6: gpio@5d0e0000 { + reg = <0x5d0e0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_6>; + }; + + lsio_gpio7: gpio@5d0f0000 { + reg = <0x5d0f0000 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&pd IMX_SC_R_GPIO_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi new file mode 100644 index 0000000..2486c72 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +&adma_lpcg { + compatible = "fsl,imx8qxp-lpcg-adma"; +}; + +&adma_lpuart0 { + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&adma_i2c0 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&adma_i2c1 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&adma_i2c2 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&adma_i2c3 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi new file mode 100644 index 0000000..27a3b46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +&conn_lpcg { + compatible = "fsl,imx8qxp-lpcg-conn"; +}; + +&usdhc1 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; +}; + +&fec1 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; +}; + +&fec2 { + compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi new file mode 100644 index 0000000..842849b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +&lsio_lpcg { + compatible = "fsl,imx8qxp-lpcg-lsio"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; +}; + +&lsio_gpio0 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 4c3dd95..c27043c 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -139,308 +139,11 @@ clock-frequency = <24000000>; clock-output-names = "xtal_24MHz"; }; - - adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - adma_lpcg: clock-controller@59000000 { - compatible = "fsl,imx8qxp-lpcg-adma"; - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - - adma_lpuart0: serial@5a060000 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x5a060000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a800000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a810000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a820000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x5a830000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; - clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; - }; - - conn_subsys: bus@5b000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - - conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - - usdhc1: mmc@5b010000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_0>; - status = "disabled"; - }; - - usdhc2: mmc@5b020000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc3: mmc@5b030000 { - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; - assigned-clock-rates = <200000000>; - power-domains = <&pd IMX_SC_R_SDHC_2>; - status = "disabled"; - }; - - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b040000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_0>; - status = "disabled"; - }; - - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; - reg = <0x5b050000 0x10000>; - interrupts = , - , - , - ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - power-domains = <&pd IMX_SC_R_ENET_1>; - status = "disabled"; - }; - }; - - lsio_subsys: bus@5d000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; - - lsio_lpcg: clock-controller@5d400000 { - compatible = "fsl,imx8qxp-lpcg-lsio"; - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - - lsio_mu0: mailbox@5d1b0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1b0000 0x10000>; - interrupts = ; - #mbox-cells = <0>; - status = "disabled"; - }; - - lsio_mu1: mailbox@5d1c0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1c0000 0x10000>; - interrupts = ; - #mbox-cells = <2>; - }; - - lsio_mu3: mailbox@5d1e0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1e0000 0x10000>; - interrupts = ; - #mbox-cells = <0>; - status = "disabled"; - }; - - lsio_mu4: mailbox@5d1f0000 { - compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; - reg = <0x5d1f0000 0x10000>; - interrupts = ; - #mbox-cells = <0>; - status = "disabled"; - }; - - lsio_gpio0: gpio@5d080000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d080000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_0>; - }; - - lsio_gpio1: gpio@5d090000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d090000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_1>; - }; - - lsio_gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0a0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_2>; - }; - - lsio_gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0b0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_3>; - }; - - lsio_gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0c0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_4>; - }; - - lsio_gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0d0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_5>; - }; - - lsio_gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0e0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_6>; - }; - - lsio_gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; - reg = <0x5d0f0000 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - power-domains = <&pd IMX_SC_R_GPIO_7>; - }; - }; + #include "imx8-ss-adma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" }; + +#include "imx8qxp-ss-adma.dtsi" +#include "imx8qxp-ss-conn.dtsi" +#include "imx8qxp-ss-lsio.dtsi" From patchwork Thu Feb 21 18:24:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824541 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 485B71390 for ; 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#address-cells = <1>; #size-cells = <1>; ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + /* SCU clocks */ + lsio_mem_clk: clock-lsio-mem { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "lsio_mem_clk"; + }; + + lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; + }; + + fspi0_clk: clock-fspi0{ + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "fspi0_clk"; + }; + + fspi1_clk: clock-fspi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "fspi1_clk"; + }; + + gpt0_clk: clock-gpt0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt0_clk"; + }; + + gpt1_clk: clock-gpt1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt1_clk"; + }; + + gpt2_clk: clock-gpt2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt2_clk"; + }; + + gpt3_clk: clock-gpt3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt3_clk"; + }; + + gpt4_clk: clock-gpt4 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpt4_clk"; + }; + + pwm0_clk: clock-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm0_clk"; + }; + + pwm1_clk: clock-pwm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm1_clk"; + }; + + pwm2_clk: clock-pwm2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm2_clk"; + }; + + pwm3_clk: clock-pwm3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm3_clk"; + }; + + pwm4_clk: clock-pwm4 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm4_clk"; + }; + + pwm5_clk: clock-pwm5 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm5_clk"; + }; + + pwm6_clk: clock-pwm6 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm6_clk"; + }; + + pwm7_clk: clock-pwm7 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "pwm7_clk"; + }; + lsio_lpcg: clock-controller@5d400000 { reg = <0x5d400000 0x400000>; #clock-cells = <1>; From patchwork Thu Feb 21 18:25:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824545 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 273F7922 for ; Thu, 21 Feb 2019 18:25:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1218F32053 for ; Thu, 21 Feb 2019 18:25:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0576032056; Thu, 21 Feb 2019 18:25:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6032432055 for ; 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Thu, 21 Feb 2019 18:25:00 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 03/14] arm64: dts: imx8: add conn scu clocks Thread-Topic: [PATCH 03/14] arm64: dts: imx8: add conn scu clocks Thread-Index: AQHUyhLB5z/Vto5y+UCugWB9Z0rq3w== Date: Thu, 21 Feb 2019 18:25:00 +0000 Message-ID: <1550773093-13349-4-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f5fe5824-6981-4879-c8ce-08d69829e3d9 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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#address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; + /* SCU clocks */ + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; + }; + + enet0_clk: clock-enet0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet0_clk"; + }; + + enet0_bypass_clk: clock-enet0-bypass { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet0_bypass_clk"; + }; + + enet0_rgmii_clk: clock-enet0-rgmii { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet0_rgmii_clk"; + }; + + enet1_clk: clock-enet1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet1_clk"; + }; + + enet1_bypass_clk: clock-enet1-bypass { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet1_bypass_clk"; + }; + + enet1_rgmii_clk: clock-enet1-rgmii { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "enet1_rgmii_clk"; + }; + + gpmi_bch_clk: clock-gpmi-bch { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpmi_bch_clk"; + }; + + gpmi_bch_io_clk: clock-gpmi-bch-io { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "gpmi_bch_io_clk"; + }; + + sdhc0_clk: clock-sdhc0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "sdhc0_clk"; + }; + + sdhc1_clk: clock-sdhc1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "sdhc1_clk"; + }; + + sdhc2_clk: clock-sdhc2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "sdhc2_clk"; + }; + + usb3_aclk: clock-usb3-aclk { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "usb3_aclk"; + }; + + usb3_bus_aclk: clock-usb3-bus { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "usb3_bus_aclk"; + }; + + usb3_lpm_aclk: clock-usb3-lpm { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "usb3_lpm_aclk"; + }; + conn_lpcg: clock-controller@5b200000 { reg = <0x5b200000 0xb0000>; #clock-cells = <1>; From patchwork Thu Feb 21 18:25:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824551 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 62C5D922 for ; Thu, 21 Feb 2019 18:26:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5192632053 for ; Thu, 21 Feb 2019 18:26:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 45B2A32056; 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#address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x2000000>; + /* SCU clocks */ + adma_ipg_clk: clock-adma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "adma_ipg_clk"; + }; + + adc0_clk: clock-adc0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "adc0_clk"; + }; + + can0_clk: clock-can0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can0_clk"; + }; + + ftm0_clk: clock-ftm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm0_clk"; + }; + + ftm1_clk: clock-ftm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm1_clk"; + }; + + i2c0_clk: clock-i2c0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: clock-i2c1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c1_clk"; + }; + + i2c2_clk: clock-i2c2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c2_clk"; + }; + + i2c3_clk: clock-i2c3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c3_clk"; + }; + + lcd0_clk: clock-lcd0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_clk"; + }; + + lcd0_pwm0_clk: clock-lcd0-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_pwm0_clk"; + }; + + spi0_clk: clock-spi0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi0_clk"; + }; + + spi1_clk: clock-spi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi1_clk"; + }; + + spi2_clk: clock-spi2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi2_clk"; + }; + + spi3_clk: clock-spi3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi3_clk"; + }; + + uart0_clk: clock-uart0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: clock-uart1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart1_clk"; + }; + + uart2_clk: clock-uart2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart2_clk"; + }; + + uart3_clk: clock-uart3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart3_clk"; + }; + adma_lpcg: clock-controller@59000000 { reg = <0x59000000 0x2000000>; #clock-cells = <1>; From patchwork Thu Feb 21 18:25:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824557 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E372B922 for ; Thu, 21 Feb 2019 18:26:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D1BBF32053 for ; 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}; - lsio_lpcg: clock-controller@5d400000 { + /* LPCG clocks */ + pwm0_lpcg: clock-controller@5d400000 { + reg = <0x5d400000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm0_clk>, <&pwm0_clk>, <&pwm0_clk>, + <&lsio_bus_clk>, <&pwm0_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm0_lpcg_ipg_clk", + "pwm0_lpcg_ipg_hf_clk", + "pwm0_lpcg_ipg_s_clk", + "pwm0_lpcg_ipg_slv_clk", + "pwm0_lpcg_ipg_mstr_clk"; + }; + + pwm1_lpcg: clock-controller@5d410000 { + reg = <0x5d410000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm1_clk>, <&pwm1_clk>, <&pwm1_clk>, + <&lsio_bus_clk>, <&pwm1_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm1_lpcg_ipg_clk", + "pwm1_lpcg_ipg_hf_clk", + "pwm1_lpcg_ipg_s_clk", + "pwm1_lpcg_ipg_slv_clk", + "pwm1_lpcg_ipg_mstr_clk"; + }; + + pwm2_lpcg: clock-controller@5d420000 { + reg = <0x5d420000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm2_clk>, <&pwm2_clk>, <&pwm2_clk>, + <&lsio_bus_clk>, <&pwm2_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm2_lpcg_ipg_clk", + "pwm2_lpcg_ipg_hf_clk", + "pwm2_lpcg_ipg_s_clk", + "pwm2_lpcg_ipg_slv_clk", + "pwm2_lpcg_ipg_mstr_clk"; + }; + + pwm3_lpcg: clock-controller@5d430000 { + reg = <0x5d430000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm3_clk>, <&pwm3_clk>, <&pwm3_clk>, + <&lsio_bus_clk>, <&pwm3_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm3_lpcg_ipg_clk", + "pwm3_lpcg_ipg_hf_clk", + "pwm3_lpcg_ipg_s_clk", + "pwm3_lpcg_ipg_slv_clk", + "pwm3_lpcg_ipg_mstr_clk"; + }; + + pwm4_lpcg: clock-controller@5d440000 { + reg = <0x5d440000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm4_clk>, <&pwm4_clk>, <&pwm4_clk>, + <&lsio_bus_clk>, <&pwm4_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm4_lpcg_ipg_clk", + "pwm4_lpcg_ipg_hf_clk", + "pwm4_lpcg_ipg_s_clk", + "pwm4_lpcg_ipg_slv_clk", + "pwm4_lpcg_ipg_mstr_clk"; + }; + + pwm5_lpcg: clock-controller@5d450000 { + reg = <0x5d450000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm5_clk>, <&pwm5_clk>, <&pwm5_clk>, + <&lsio_bus_clk>, <&pwm5_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm5_lpcg_ipg_clk", + "pwm5_lpcg_ipg_hf_clk", + "pwm5_lpcg_ipg_s_clk", + "pwm5_lpcg_ipg_slv_clk", + "pwm5_lpcg_ipg_mstr_clk"; + }; + + pwm6_lpcg: clock-controller@5d460000 { + reg = <0x5d460000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm6_clk>, <&pwm6_clk>, <&pwm6_clk>, + <&lsio_bus_clk>, <&pwm6_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm6_lpcg_ipg_clk", + "pwm6_lpcg_ipg_hf_clk", + "pwm6_lpcg_ipg_s_clk", + "pwm6_lpcg_ipg_slv_clk", + "pwm6_lpcg_ipg_mstr_clk"; + }; + + pwm7_lpcg: clock-controller@5d470000 { + reg = <0x5d470000 0x10000>; + #clock-cells = <1>; + clocks = <&pwm7_clk>, <&pwm7_clk>, <&pwm7_clk>, + <&lsio_bus_clk>, <&pwm7_clk>; + bit-offset = <0 4 16 20 24>; + clock-output-names = "pwm7_lpcg_ipg_clk", + "pwm7_lpcg_ipg_hf_clk", + "pwm7_lpcg_ipg_s_clk", + "pwm7_lpcg_ipg_slv_clk", + "pwm7_lpcg_ipg_mstr_clk"; + }; + + lsio_lpcg: clock-controller-legacy@5d400000 { reg = <0x5d400000 0x400000>; #clock-cells = <1>; }; From patchwork Thu Feb 21 18:25:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824561 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 493021390 for ; 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}; - conn_lpcg: clock-controller@5b200000 { + /* LPCG clocks */ + sdhc0_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&sdhc0_clk>, <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&sdhc1_clk>, <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&sdhc2_clk>, <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + }; + + enet0_lpcg: clock-controller@5b230000 { + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&enet0_clk>, <&enet0_clk>, <&conn_axi_clk>, + <&conn_ipg_clk>, <&conn_ipg_clk>; + bit-offset = <0 4 8 16 20>; + clock-output-names = "enet0_ipg_root_clk", + "enet0_tx_clk", + "enet0_ahb_clk", + "enet0_ipg_clk", + "enet0_ipg_s_clk"; + }; + + enet1_lpcg: clock-controller@5b240000 { + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&enet1_clk>, <&enet1_clk>, <&conn_axi_clk>, + <&conn_ipg_clk>, <&conn_ipg_clk>; + bit-offset = <0 4 8 16 20>; + clock-output-names = "enet1_ipg_root_clk", + "enet1_tx_clk", + "enet1_ahb_clk", + "enet1_ipg_clk", + "enet1_ipg_s_clk"; + }; + + conn_lpcg: clock-controller-legacy@5b200000 { reg = <0x5b200000 0xb0000>; #clock-cells = <1>; }; From patchwork Thu Feb 21 18:25:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824559 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B075E922 for ; Thu, 21 Feb 2019 18:26:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9E72132055 for ; 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}; + /* LPCG clocks */ + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&uart0_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&uart1_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&uart2_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&uart3_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c0_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c1_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c2_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c3_clk>, <&adma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + }; + adma_lpcg: clock-controller@59000000 { reg = <0x59000000 0x2000000>; #clock-cells = <1>; From patchwork Thu Feb 21 18:25:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 50D6D922 for ; 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SFS:(10009020)(136003)(396003)(366004)(39860400002)(346002)(376002)(189003)(199004)(256004)(53936002)(106356001)(71200400001)(71190400001)(81166006)(2351001)(2906002)(6916009)(446003)(105586002)(81156014)(44832011)(316002)(305945005)(97736004)(2616005)(8676002)(54906003)(14444005)(6512007)(7736002)(2501003)(68736007)(76176011)(386003)(6506007)(3846002)(486006)(14454004)(5640700003)(86362001)(6486002)(30864003)(52116002)(6436002)(4326008)(8936002)(102836004)(5660300002)(476003)(26005)(99286004)(478600001)(11346002)(6116002)(25786009)(50226002)(186003)(36756003)(66066001); DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR04MB5599; H:VI1PR04MB4222.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: DdR7bHogsjTJbHq+bfhJOt5S0l5ug7Sp499afNXmEWlsodmiZbbFBh3cHoE8x7gViITxmmYZcNNCfJDRfh0H65odx7pakBwDjMpP8HKiz4njD4XqcVHQ9hiX6Kb+8EfV2/ydpWW4G1i2Q9VXCgSNOX74OfZjPoQI3ua2VewprqkV33xu81m0aYxX4E5EVLyynMXPL6f2BOJ7/UBD7bI7FABgYCT9Om+gGTb3knMwIziebUwNO72TBaYSo0tr/fLhS8FVMnIc0R0y2uUiWu9sXTDEx/Cl5pQYFxMrZkkKIQW6lBNMHUMcGR2AUDUOFoPafH/+5nZesq5gmKRVstFo9nkvRmdn9efhd0t/dtvWYt+fRlc2aNGnhjDO2NoDFCZOM3MmkqoGxwYz/3c7nCLLxiPjFxyxwdZwuGzhQ2KoQwY= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6194847e-a528-407b-9a36-08d69829f09f X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Feb 2019 18:25:17.9920 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB5599 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190221_102531_337954_235E71FB X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aisheng Dong , Mark Rutland , "dongas86@gmail.com" , "devicetree@vger.kernel.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP switch to new clock binding Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 23 ++--- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 40 ++++---- arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 104 ++++++++++++++++++++- arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 68 +++++++++++++- arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 92 +++++++++++++++++- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 -- 6 files changed, 287 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index c7adeba..835ecf7 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -219,16 +219,11 @@ adma_subsys: bus@59000000 { "i2c3_lpcg_ipg_clk"; }; - adma_lpcg: clock-controller@59000000 { - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - adma_lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clocks = <&uart0_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; status = "disabled"; @@ -238,9 +233,9 @@ adma_subsys: bus@59000000 { reg = <0x5a800000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clocks = <&i2c0_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; + assigned-clocks = <&i2c0_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_0>; status = "disabled"; @@ -250,9 +245,9 @@ adma_subsys: bus@59000000 { reg = <0x5a810000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clocks = <&i2c1_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; + assigned-clocks = <&i2c1_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_1>; status = "disabled"; @@ -262,9 +257,9 @@ adma_subsys: bus@59000000 { reg = <0x5a820000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clocks = <&i2c2_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; + assigned-clocks = <&i2c2_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_2>; status = "disabled"; @@ -274,9 +269,9 @@ adma_subsys: bus@59000000 { reg = <0x5a830000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clocks = <&i2c3_lpcg 0>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; + assigned-clocks = <&i2c3_clk>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_3>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 33a3584..c6b2870 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -198,11 +198,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clocks = <&sdhc0_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_0>; status = "disabled"; @@ -212,11 +212,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clocks = <&sdhc1_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_1>; fsl,tuning-start-tap = <20>; @@ -228,11 +228,11 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>; + assigned-clocks = <&sdhc2_clk>; assigned-clock-rates = <200000000>; power-domains = <&pd IMX_SC_R_SDHC_2>; status = "disabled"; @@ -244,10 +244,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clocks = <&enet0_lpcg 3>, + <&enet0_lpcg 2>, + <&enet0_lpcg 1>, + <&enet0_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -261,10 +261,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clocks = <&enet1_lpcg 3>, + <&enet1_lpcg 2>, + <&enet1_lpcg 1>, + <&enet1_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 2486c72..2368e52 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -4,8 +4,108 @@ * Dong Aisheng */ -&adma_lpcg { - compatible = "fsl,imx8qxp-lpcg-adma"; +&adc0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&can0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&ftm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&ftm1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&i2c3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&lcd0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&lcd0_pwm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&spi3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&uart0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&uart3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&i2c3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &adma_lpuart0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index 27a3b46..5f6552d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -4,8 +4,72 @@ * Dong Aisheng */ -&conn_lpcg { - compatible = "fsl,imx8qxp-lpcg-conn"; +&enet0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet0_bypass_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet0_rgmii_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_bypass_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&enet1_rgmii_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_io_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_bus_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&usb3_lpm_aclk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&sdhc0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&sdhc1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&enet0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&enet1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &usdhc1 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index 842849b..742e57f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -4,8 +4,96 @@ * Dong Aisheng */ -&lsio_lpcg { - compatible = "fsl,imx8qxp-lpcg-lsio"; +&fspi0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&fspi1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&gpt4_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm0_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm1_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm2_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm3_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm4_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm5_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm6_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm7_clk { + compatible = "fsl,imx8qxp-clock", "fsl,scu-clk"; +}; + +&pwm0_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm1_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm2_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm3_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm4_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm5_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm6_lpcg { + compatible = "fsl,imx8qxp-lpcg"; +}; + +&pwm7_lpcg { + compatible = "fsl,imx8qxp-lpcg"; }; &lsio_mu0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index c27043c..589483a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -97,13 +97,6 @@ &lsio_mu1 1 2 &lsio_mu1 1 3>; - clk: clock-controller { - compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; - clocks = <&xtal32k &xtal24m>; - clock-names = "xtal_32KHz", "xtal_24Mhz"; - }; - iomuxc: pinctrl { compatible = "fsl,imx8qxp-iomuxc"; }; From patchwork Thu Feb 21 18:25:26 2019 Content-Type: text/plain; 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Thu, 21 Feb 2019 18:25:26 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 09/14] arm64: dts: imx8qm: add lsio ss support Thread-Topic: [PATCH 09/14] arm64: dts: imx8qm: add lsio ss support Thread-Index: AQHUyhLR2j01ec8330qg1uIxC4/xMQ== Date: Thu, 21 Feb 2019 18:25:26 +0000 Message-ID: <1550773093-13349-10-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: abf26679-5ae8-4bab-6977-08d69829f350 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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So we can fully reuse the exist LSIO SS dtsi. Add -ss-lsio.dtsi with compatible string updated according to imx8-ss-lsio.dtsi. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi | 145 ++++++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi new file mode 100644 index 0000000..9ea772b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&fspi0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&fspi1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpt0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpt1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpt2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpt3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpt4_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm4_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm5_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm6_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm7_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&pwm0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm4_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm5_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm6_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&pwm7_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&lsio_mu0 { + compatible = "fsl,imx8m-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu1 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu3 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_mu4 { + compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu"; +}; + +&lsio_gpio0 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio1 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio2 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio3 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio4 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio5 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio6 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; + +&lsio_gpio7 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; +}; From patchwork Thu Feb 21 18:25:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 37CAD922 for ; Thu, 21 Feb 2019 18:27:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24E13321A9 for ; Thu, 21 Feb 2019 18:27:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 19168321FD; Thu, 21 Feb 2019 18:27:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9AFDC321A9 for ; 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Thu, 21 Feb 2019 18:25:31 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 10/14] arm64: dts: imx8qm: add conn ss support Thread-Topic: [PATCH 10/14] arm64: dts: imx8qm: add conn ss support Thread-Index: AQHUyhLTjSkPl+mUc0CQCt8nCc+09A== Date: Thu, 21 Feb 2019 18:25:31 +0000 Message-ID: <1550773093-13349-11-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 263dd532-c8d7-4e62-57f4-08d69829f605 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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So we can fully reuse the exist CONN SS dtsi. Add -ss-conn.dtsi with compatible string updated according to imx8-ss-conn.dtsi. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi | 93 +++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi new file mode 100644 index 0000000..68eaf7f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng + */ + +&enet0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&enet0_bypass_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&enet0_rgmii_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&enet1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&enet1_bypass_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&enet1_rgmii_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&gpmi_bch_io_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&sdhc0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&sdhc1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&usb3_aclk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&usb3_bus_aclk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&usb3_lpm_aclk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&sdhc0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&sdhc1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&enet0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&enet1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&usdhc1 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc2 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; +}; + +&usdhc3 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx7d-usdhc"; +}; + +&fec1 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +}; + +&fec2 { + compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec"; +}; From patchwork Thu Feb 21 18:25:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824575 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4C24E1390 for ; Thu, 21 Feb 2019 18:28:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 35A18321FD for ; Thu, 21 Feb 2019 18:28:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 260D332224; Thu, 21 Feb 2019 18:28:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 08FB8321FD for ; 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Thu, 21 Feb 2019 18:25:34 +0000 From: Aisheng Dong To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH 11/14] arm64: dts: imx8: split adma ss into dma and audio ss Thread-Topic: [PATCH 11/14] arm64: dts: imx8: split adma ss into dma and audio ss Thread-Index: AQHUyhLVa4voSQ/PHE68eEoO39rJ3g== Date: Thu, 21 Feb 2019 18:25:34 +0000 Message-ID: <1550773093-13349-12-git-send-email-aisheng.dong@nxp.com> References: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1550773093-13349-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK2PR03CA0051.apcprd03.prod.outlook.com (2603:1096:202:17::21) To VI1PR04MB4222.eurprd04.prod.outlook.com (2603:10a6:803:3e::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 73520381-a397-4795-3dcd-08d69829f844 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Let's split them into two ss for better code reuse. Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 274 +------------------- arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 279 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +- arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 10 +- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 +- 5 files changed, 288 insertions(+), 281 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 835ecf7..991aaab 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -4,276 +4,4 @@ * Dong Aisheng */ -#include - -adma_subsys: bus@59000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x59000000 0x0 0x59000000 0x2000000>; - - /* SCU clocks */ - adma_ipg_clk: clock-adma-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "adma_ipg_clk"; - }; - - adc0_clk: clock-adc0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "adc0_clk"; - }; - - can0_clk: clock-can0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "can0_clk"; - }; - - ftm0_clk: clock-ftm0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "ftm0_clk"; - }; - - ftm1_clk: clock-ftm1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "ftm1_clk"; - }; - - i2c0_clk: clock-i2c0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c0_clk"; - }; - - i2c1_clk: clock-i2c1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c1_clk"; - }; - - i2c2_clk: clock-i2c2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c2_clk"; - }; - - i2c3_clk: clock-i2c3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "i2c3_clk"; - }; - - lcd0_clk: clock-lcd0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "lcd0_clk"; - }; - - lcd0_pwm0_clk: clock-lcd0-pwm0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "lcd0_pwm0_clk"; - }; - - spi0_clk: clock-spi0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi0_clk"; - }; - - spi1_clk: clock-spi1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi1_clk"; - }; - - spi2_clk: clock-spi2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi2_clk"; - }; - - spi3_clk: clock-spi3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "spi3_clk"; - }; - - uart0_clk: clock-uart0 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart0_clk"; - }; - - uart1_clk: clock-uart1 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart1_clk"; - }; - - uart2_clk: clock-uart2 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart2_clk"; - }; - - uart3_clk: clock-uart3 { - #clock-cells = <0>; - rsrc-id = ; - clk-type = ; - clock-output-names = "uart3_clk"; - }; - - /* LPCG clocks */ - uart0_lpcg: clock-controller@5a460000 { - reg = <0x5a460000 0x10000>; - #clock-cells = <1>; - clocks = <&uart0_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart0_lpcg_baud_clk", - "uart0_lpcg_ipg_clk"; - }; - - uart1_lpcg: clock-controller@5a470000 { - reg = <0x5a470000 0x10000>; - #clock-cells = <1>; - clocks = <&uart1_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart1_lpcg_baud_clk", - "uart1_lpcg_ipg_clk"; - }; - - uart2_lpcg: clock-controller@5a480000 { - reg = <0x5a480000 0x10000>; - #clock-cells = <1>; - clocks = <&uart2_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart2_lpcg_baud_clk", - "uart2_lpcg_ipg_clk"; - }; - - uart3_lpcg: clock-controller@5a490000 { - reg = <0x5a490000 0x10000>; - #clock-cells = <1>; - clocks = <&uart3_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "uart3_lpcg_baud_clk", - "uart3_lpcg_ipg_clk"; - }; - - i2c0_lpcg: clock-controller@5ac00000 { - reg = <0x5ac00000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c0_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c0_lpcg_clk", - "i2c0_lpcg_ipg_clk"; - }; - - i2c1_lpcg: clock-controller@5ac10000 { - reg = <0x5ac10000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c1_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c1_lpcg_clk", - "i2c1_lpcg_ipg_clk"; - }; - - i2c2_lpcg: clock-controller@5ac20000 { - reg = <0x5ac20000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c2_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c2_lpcg_clk", - "i2c2_lpcg_ipg_clk"; - }; - - i2c3_lpcg: clock-controller@5ac30000 { - reg = <0x5ac30000 0x10000>; - #clock-cells = <1>; - clocks = <&i2c3_clk>, <&adma_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "i2c3_lpcg_clk", - "i2c3_lpcg_ipg_clk"; - }; - - adma_lpuart0: serial@5a060000 { - reg = <0x5a060000 0x1000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&uart0_lpcg 0>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_UART_0>; - status = "disabled"; - }; - - adma_i2c0: i2c@5a800000 { - reg = <0x5a800000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c0_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c0_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_0>; - status = "disabled"; - }; - - adma_i2c1: i2c@5a810000 { - reg = <0x5a810000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c1_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c1_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_1>; - status = "disabled"; - }; - - adma_i2c2: i2c@5a820000 { - reg = <0x5a820000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c2_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c2_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_2>; - status = "disabled"; - }; - - adma_i2c3: i2c@5a830000 { - reg = <0x5a830000 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&i2c3_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&i2c3_clk>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_I2C_3>; - status = "disabled"; - }; -}; +#include "imx8-ss-dma.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi new file mode 100644 index 0000000..fda5fa7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include + +dma_subsys: bus@5a000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; + + /* SCU clocks */ + dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; + }; + + adc0_clk: clock-adc0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "adc0_clk"; + }; + + can0_clk: clock-can0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can0_clk"; + }; + + ftm0_clk: clock-ftm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm0_clk"; + }; + + ftm1_clk: clock-ftm1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "ftm1_clk"; + }; + + i2c0_clk: clock-i2c0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: clock-i2c1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c1_clk"; + }; + + i2c2_clk: clock-i2c2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c2_clk"; + }; + + i2c3_clk: clock-i2c3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "i2c3_clk"; + }; + + lcd0_clk: clock-lcd0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_clk"; + }; + + lcd0_pwm0_clk: clock-lcd0-pwm0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "lcd0_pwm0_clk"; + }; + + spi0_clk: clock-spi0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi0_clk"; + }; + + spi1_clk: clock-spi1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi1_clk"; + }; + + spi2_clk: clock-spi2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi2_clk"; + }; + + spi3_clk: clock-spi3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "spi3_clk"; + }; + + uart0_clk: clock-uart0 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: clock-uart1 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart1_clk"; + }; + + uart2_clk: clock-uart2 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart2_clk"; + }; + + uart3_clk: clock-uart3 { + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart3_clk"; + }; + + /* LPCG clocks */ + uart0_lpcg: clock-controller@5a460000 { + reg = <0x5a460000 0x10000>; + #clock-cells = <1>; + clocks = <&uart0_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart0_lpcg_baud_clk", + "uart0_lpcg_ipg_clk"; + }; + + uart1_lpcg: clock-controller@5a470000 { + reg = <0x5a470000 0x10000>; + #clock-cells = <1>; + clocks = <&uart1_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart1_lpcg_baud_clk", + "uart1_lpcg_ipg_clk"; + }; + + uart2_lpcg: clock-controller@5a480000 { + reg = <0x5a480000 0x10000>; + #clock-cells = <1>; + clocks = <&uart2_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart2_lpcg_baud_clk", + "uart2_lpcg_ipg_clk"; + }; + + uart3_lpcg: clock-controller@5a490000 { + reg = <0x5a490000 0x10000>; + #clock-cells = <1>; + clocks = <&uart3_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart3_lpcg_baud_clk", + "uart3_lpcg_ipg_clk"; + }; + + i2c0_lpcg: clock-controller@5ac00000 { + reg = <0x5ac00000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c0_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c0_lpcg_clk", + "i2c0_lpcg_ipg_clk"; + }; + + i2c1_lpcg: clock-controller@5ac10000 { + reg = <0x5ac10000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c1_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c1_lpcg_clk", + "i2c1_lpcg_ipg_clk"; + }; + + i2c2_lpcg: clock-controller@5ac20000 { + reg = <0x5ac20000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c2_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c2_lpcg_clk", + "i2c2_lpcg_ipg_clk"; + }; + + i2c3_lpcg: clock-controller@5ac30000 { + reg = <0x5ac30000 0x10000>; + #clock-cells = <1>; + clocks = <&i2c3_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "i2c3_lpcg_clk", + "i2c3_lpcg_ipg_clk"; + }; + + dma_lpuart0: serial@5a060000 { + reg = <0x5a060000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart0_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_UART_0>; + status = "disabled"; + }; + + dma_i2c0: i2c@5a800000 { + reg = <0x5a800000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c0_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_0>; + status = "disabled"; + }; + + dma_i2c1: i2c@5a810000 { + reg = <0x5a810000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c1_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c1_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_1>; + status = "disabled"; + }; + + dma_i2c2: i2c@5a820000 { + reg = <0x5a820000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c2_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c2_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_2>; + status = "disabled"; + }; + + dma_i2c3: i2c@5a830000 { + reg = <0x5a830000 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&i2c3_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&i2c3_clk>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_I2C_3>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 03aad66..1f9c2f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -12,7 +12,7 @@ compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; chosen { - stdout-path = &adma_lpuart0; + stdout-path = &dma_lpuart0; }; memory@80000000 { @@ -30,7 +30,7 @@ }; }; -&adma_lpuart0 { +&dma_lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 2368e52..67b8807 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -108,22 +108,22 @@ compatible = "fsl,imx8qxp-lpcg"; }; -&adma_lpuart0 { +&dma_lpuart0 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; }; -&adma_i2c0 { +&dma_i2c0 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c1 { +&dma_i2c1 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c2 { +&dma_i2c2 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; -&adma_i2c3 { +&dma_i2c3 { compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 589483a..161f6c0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -20,7 +20,7 @@ mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; - serial0 = &adma_lpuart0; + serial0 = &dma_lpuart0; }; cpus { From patchwork Thu Feb 21 18:25:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824565 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 33C9C1390 for ; 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And unlike MX8QXP that flexcan clocks are shared between multiple CAN instances, MX8QM has separate flexcan clock slice. So we reuse the most part of common imx8-ss-dma.dtsi and add new things based on it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 171 +++++++++++++++++++++++ 1 file changed, 171 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi new file mode 100644 index 0000000..7645612 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ +&dma_subsys { + adc1_clk: clock-adc1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "adc1_clk"; + }; + + can1_clk: clock-can1 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can1_clk"; + }; + + can2_clk: clock-can2 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "can2_clk"; + }; + + uart4_clk: clock-uart4 { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; + #clock-cells = <0>; + rsrc-id = ; + clk-type = ; + clock-output-names = "uart4_clk"; + }; + + uart4_lpcg: clock-controller@5a4a0000 { + reg = <0x5a4a0000 0x10000>; + #clock-cells = <1>; + clocks = <&uart4_clk>, <&dma_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "uart4_lpcg_baud_clk", + "uart4_lpcg_ipg_clk"; + }; +}; + +&adc0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&can0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&ftm1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&i2c3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&lcd0_pwm0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&spi3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart1_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart2_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart3_clk { + compatible = "fsl,imx8qm-clock", "fsl,scu-clk"; +}; + +&uart0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&uart3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c0_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c1_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c2_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&i2c3_lpcg { + compatible = "fsl,imx8qm-lpcg", "fsl,imx8qxp-lpcg"; +}; + +&dma_lpuart0 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx7ulp-lpuart"; +}; + +&dma_i2c0 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c2 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; + +&dma_i2c3 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; +}; From patchwork Thu Feb 21 18:25:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824569 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A7067922 for ; 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It uses the same architecture as MX8QXP, so many SS can be reused. This patch adds i.MX8QuadMax SoC dtsi file. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 173 ++++++++++++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi new file mode 100644 index 0000000..526cbbd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + serial0 = &dma_lpuart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&A53_0>; + }; + core1 { + cpu = <&A53_1>; + }; + core2 { + cpu = <&A53_2>; + }; + core3 { + cpu = <&A53_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&A72_0>; + }; + core1 { + cpu = <&A72_1>; + }; + }; + }; + + A53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&A53_L2>; + }; + + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + }; + + A53_L2: l2-cache0 { + compatible = "cache"; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + }; + + scu { + compatible = "fsl,imx-scu"; + mbox-names = "tx0", "tx1", "tx2", "tx3", + "rx0", "rx1", "rx2", "rx3"; + mboxes = <&lsio_mu1 0 0 + &lsio_mu1 0 1 + &lsio_mu1 0 2 + &lsio_mu1 0 3 + &lsio_mu1 1 0 + &lsio_mu1 1 1 + &lsio_mu1 1 2 + &lsio_mu1 1 3>; + + iomuxc: pinctrl { + compatible = "fsl,imx8qm-iomuxc"; + }; + + pd: imx8qx-pd { + compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd"; + #power-domain-cells = <1>; + }; + }; + + /* sorted in register address */ + #include "imx8-ss-dma.dtsi" + #include "imx8-ss-conn.dtsi" + #include "imx8-ss-lsio.dtsi" +}; + +#include "imx8qm-ss-dma.dtsi" +#include "imx8qm-ss-conn.dtsi" +#include "imx8qm-ss-lsio.dtsi" From patchwork Thu Feb 21 18:25:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 10824573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6EB101390 for ; Thu, 21 Feb 2019 18:27:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D0513205A for ; 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This patch adds i.MX8QuadMax MEK board support. Note that MX8QM needs a special workaround for TLB flush due to a SoC errata, otherwise there may be random crash if enable both clusters of A72 and A53. As the errata workaround is still not in mainline, so we disable A72 cluster first for MX8QM MEK. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 144 +++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-mek.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 13604e5..b8e5e3b 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -21,4 +21,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts new file mode 100644 index 0000000..80d8da1 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Dong Aisheng + */ + +/dts-v1/; + +#include "imx8qm.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + stdout-path = &dma_lpuart0; + }; + + cpus { + /delete-node/ cpu-map; + /delete-node/ cpu@100; + /delete-node/ cpu@101; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + }; + + reg_usdhc2_vmmc: usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&dma_lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 + IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; +};