From patchwork Mon Mar 18 13:37:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Coelho X-Patchwork-Id: 13595378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 801E6C54E71 for ; Mon, 18 Mar 2024 13:38:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E102910F73C; Mon, 18 Mar 2024 13:38:22 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="HewzNpNf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id E6E6710EF0D; Mon, 18 Mar 2024 13:38:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710769101; x=1742305101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qzHo0LqUfvw77QVxai1LSbWeFnr1GKPRs9LuIaf2R50=; b=HewzNpNfzJpDK1PTzTBJFKvek4+jP75TgwzayBQzO91arjZJeM8cUKCh KuOXeSSCpgsbRuDqDG6NAKf0q360dndS345WeNlneFEkj0jV3av1jQGmb FZi3shf1hmwQJIHS8mlxj1oGDhVuk2GOWOUi7H5DLbnbS6sTjiacoe6PG BrmmKlBmMHfa18TH5GSWi8fJaiDpFa+tX8UzfY7X83WpNUeXk0qvOYtpL U0npUS1nEnLKt3zMplmNjTAx0/sh4eDZse0+lVciw75sj56wpe6VexNee k4A4fKrG4Oh53CQ9F5BL7SwMjg51H3jROubQsM1oUj3XeZ9+vBrFcIkYZ Q==; X-IronPort-AV: E=McAfee;i="6600,9927,11016"; a="16218020" X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="16218020" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="13570048" Received: from dcroitox-mobl1.ger.corp.intel.com (HELO hazy.ger.corp.intel.com) ([10.251.210.126]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:18 -0700 From: Luca Coelho To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, uma.shankar@intel.com, ville.syrjala@linux.intel.com, jani.nikula@intel.com Subject: [PATCH v3 1/4] drm/i915/display: add support for DMC wakelocks Date: Mon, 18 Mar 2024 15:37:54 +0200 Message-Id: <20240318133757.1479189-2-luciano.coelho@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240318133757.1479189-1-luciano.coelho@intel.com> References: <20240318133757.1479189-1-luciano.coelho@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" In order to reduce the DC5->DC2 restore time, wakelocks have been introduced in DMC so the driver can tell it when registers and other memory areas are going to be accessed and keep their respective blocks awake. Implement this in the driver by adding the concept of DMC wakelocks. When the driver needs to access memory which lies inside pre-defined ranges, it will tell DMC to set the wakelock, access the memory, then wait for a while and clear the wakelock. The wakelock state is protected in the driver with spinlocks to prevent concurrency issues. BSpec: 71583 Signed-off-by: Luca Coelho --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_de.h | 97 +++++++- .../gpu/drm/i915/display/intel_display_core.h | 2 + .../drm/i915/display/intel_display_driver.c | 1 + drivers/gpu/drm/i915/display/intel_dmc_regs.h | 6 + drivers/gpu/drm/i915/display/intel_dmc_wl.c | 226 ++++++++++++++++++ drivers/gpu/drm/i915/display/intel_dmc_wl.h | 30 +++ drivers/gpu/drm/xe/Makefile | 1 + 8 files changed, 356 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl.c create mode 100644 drivers/gpu/drm/i915/display/intel_dmc_wl.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 3ef6ed41e62b..af83ea94c771 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -270,6 +270,7 @@ i915-y += \ display/intel_display_rps.o \ display/intel_display_wa.o \ display/intel_dmc.o \ + display/intel_dmc_wl.o \ display/intel_dpio_phy.o \ display/intel_dpll.o \ display/intel_dpll_mgr.o \ diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h index 42552d8c151e..6728a0077793 100644 --- a/drivers/gpu/drm/i915/display/intel_de.h +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -13,52 +13,125 @@ static inline u32 intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) { - return intel_uncore_read(&i915->uncore, reg); + u32 val; + + intel_dmc_wl_get(i915, reg); + + val = intel_uncore_read(&i915->uncore, reg); + + intel_dmc_wl_put(i915, reg); + + return val; } static inline u8 intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg) { - return intel_uncore_read8(&i915->uncore, reg); + u8 val; + + intel_dmc_wl_get(i915, reg); + + val = intel_uncore_read8(&i915->uncore, reg); + + intel_dmc_wl_put(i915, reg); + + return val; } static inline u64 intel_de_read64_2x32(struct drm_i915_private *i915, i915_reg_t lower_reg, i915_reg_t upper_reg) { - return intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg); + u64 val; + + intel_dmc_wl_get(i915, lower_reg); + intel_dmc_wl_get(i915, upper_reg); + + val = intel_uncore_read64_2x32(&i915->uncore, lower_reg, upper_reg); + + intel_dmc_wl_put(i915, upper_reg); + intel_dmc_wl_put(i915, lower_reg); + + return val; } static inline void intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) { + intel_dmc_wl_get(i915, reg); + intel_uncore_posting_read(&i915->uncore, reg); + + intel_dmc_wl_put(i915, reg); } static inline void intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) { + intel_dmc_wl_get(i915, reg); + intel_uncore_write(&i915->uncore, reg, val); + + intel_dmc_wl_put(i915, reg); } static inline u32 -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) +__intel_de_rmw_nowl(struct drm_i915_private *i915, i915_reg_t reg, + u32 clear, u32 set) { return intel_uncore_rmw(&i915->uncore, reg, clear, set); } +static inline u32 +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) +{ + u32 val; + + intel_dmc_wl_get(i915, reg); + + val = __intel_de_rmw_nowl(i915, reg, clear, set); + + intel_dmc_wl_put(i915, reg); + + return val; +} + +static inline int +__intel_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, u32 value, unsigned int timeout) +{ + return intel_wait_for_register(&i915->uncore, reg, mask, + value, timeout); +} + static inline int intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) { - return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); + int ret; + + intel_dmc_wl_get(i915, reg); + + ret = __intel_wait_for_register_nowl(i915, reg, mask, value, timeout); + + intel_dmc_wl_put(i915, reg); + + return ret; } static inline int intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 mask, u32 value, unsigned int timeout) { - return intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout); + int ret; + + intel_dmc_wl_get(i915, reg); + + ret = intel_wait_for_register_fw(&i915->uncore, reg, mask, value, timeout); + + intel_dmc_wl_put(i915, reg); + + return ret; } static inline int @@ -67,8 +140,16 @@ __intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, unsigned int fast_timeout_us, unsigned int slow_timeout_ms, u32 *out_value) { - return __intel_wait_for_register(&i915->uncore, reg, mask, value, - fast_timeout_us, slow_timeout_ms, out_value); + int ret; + + intel_dmc_wl_get(i915, reg); + + ret = __intel_wait_for_register(&i915->uncore, reg, mask, value, + fast_timeout_us, slow_timeout_ms, out_value); + + intel_dmc_wl_put(i915, reg); + + return ret; } static inline int diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h index 2167dbee5eea..c40719073510 100644 --- a/drivers/gpu/drm/i915/display/intel_display_core.h +++ b/drivers/gpu/drm/i915/display/intel_display_core.h @@ -26,6 +26,7 @@ #include "intel_global_state.h" #include "intel_gmbus.h" #include "intel_opregion.h" +#include "intel_dmc_wl.h" #include "intel_wm_types.h" struct task_struct; @@ -534,6 +535,7 @@ struct intel_display { struct intel_overlay *overlay; struct intel_display_params params; struct intel_vbt_data vbt; + struct intel_dmc_wl wl; struct intel_wm wm; }; diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 87dd07e0d138..e4015557af6a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -198,6 +198,7 @@ void intel_display_driver_early_probe(struct drm_i915_private *i915) intel_dpll_init_clock_hook(i915); intel_init_display_hooks(i915); intel_fdi_init_hook(i915); + intel_dmc_wl_init(i915); } /* part #1: call before irq install */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h index 90d0dbb41cfe..1bf446f96a10 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h @@ -97,4 +97,10 @@ #define TGL_DMC_DEBUG3 _MMIO(0x101090) #define DG1_DMC_DEBUG3 _MMIO(0x13415c) +#define DMC_WAKELOCK_CFG _MMIO(0x8F1B0) +#define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31) +#define DMC_WAKELOCK1_CTL _MMIO(0x8F140) +#define DMC_WAKELOCK_CTL_REQ REG_BIT(31) +#define DMC_WAKELOCK_CTL_ACK REG_BIT(15) + #endif /* __INTEL_DMC_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c new file mode 100644 index 000000000000..5c3d8204ae7e --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2023 Intel Corporation + */ + +#include + +#include "intel_de.h" +#include "intel_dmc_regs.h" +#include "intel_dmc_wl.h" + +/** + * DOC: DMC wakelock support + * + * Wake lock is the mechanism to cause display engine to exit DC + * states to allow programming to registers that are powered down in + * those states. Previous projects exited DC states automatically when + * detecting programming. Now software controls the exit by + * programming the wake lock. This improves system performance and + * system interactions and better fits the flip queue style of + * programming. Wake lock is only required when DC5, DC6, or DC6v have + * been enabled in DC_STATE_EN and the wake lock mode of operation has + * been enabled. + * + * The wakelock mechanism in DMC allows the display engine to exit DC + * states explicitly before programming registers that may be powered + * down. In earlier hardware, this was done automatically and + * implicitly when the display engine accessed a register. With the + * wakelock implementation, the driver asserts a wakelock in DMC, + * which forces it to exit the DC state until the wakelock is + * deasserted. + * + * This improves system performance and system interactions and better + * fits the flip queue style of programming. Wakelock is only + * required when DC5, DC6, or DC6v have been enabled in DC_STATE_EN + * and the wakelock feature enabled in the driver. + * + * The mechanism can be enabled and disabled by writing to the + * DMC_WAKELOCK_CFG register. There are also 13 control registers + * that can be used to hold and release different wakelocks. In the + * current implementation, we only need one wakelock, so only + * DMC_WAKELOCK1_CTL is used. The other definitions are here for + * potential future use. + */ + +#define DMC_WAKELOCK_CTL_TIMEOUT 5 +#define DMC_WAKELOCK_HOLD_TIME 50 + +struct intel_dmc_wl_range { + u32 start; + u32 end; +}; + +static struct intel_dmc_wl_range lnl_wl_range[] = { + { .start = 0x60000, .end = 0x7ffff }, +}; + +static void __intel_dmc_wl_release(struct drm_i915_private *i915) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + + WARN_ON(refcount_read(&wl->refcount)); + + queue_delayed_work(i915->unordered_wq, &wl->work, + msecs_to_jiffies(DMC_WAKELOCK_HOLD_TIME)); +} + +static void intel_dmc_wl_work(struct work_struct *work) +{ + struct intel_dmc_wl *wl = + container_of(work, struct intel_dmc_wl, work.work); + struct drm_i915_private *i915 = + container_of(wl, struct drm_i915_private, display.wl); + unsigned long flags; + + spin_lock_irqsave(&wl->lock, flags); + + /* Bail out if refcount reached zero while waiting for the spinlock */ + if (!refcount_read(&wl->refcount)) + goto out_unlock; + + __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0); + + WARN_RATELIMIT(__intel_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL, + DMC_WAKELOCK_CTL_ACK, 0, + DMC_WAKELOCK_CTL_TIMEOUT), + "DMC wakelock release timed out"); + +out_unlock: + spin_unlock_irqrestore(&wl->lock, flags); +} + +static bool intel_dmc_wl_check_range(u32 address) +{ + int i; + bool wl_needed = false; + + for (i = 0; i < ARRAY_SIZE(lnl_wl_range); i++) { + if (address >= lnl_wl_range[i].start && + address <= lnl_wl_range[i].end) { + wl_needed = true; + break; + } + } + + return wl_needed; +} + +void intel_dmc_wl_init(struct drm_i915_private *i915) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + + INIT_DELAYED_WORK(&wl->work, intel_dmc_wl_work); + spin_lock_init(&wl->lock); + refcount_set(&wl->refcount, 0); +} + +void intel_dmc_wl_enable(struct drm_i915_private *i915) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + unsigned long flags; + + spin_lock_irqsave(&wl->lock, flags); + + if (wl->enabled) + goto out_unlock; + + /* + * Enable wakelock in DMC. We shouldn't try to take the + * wakelock, because we're just enabling it, so call the + * non-locking version directly here. + */ + __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE); + + wl->enabled = true; + +out_unlock: + spin_unlock_irqrestore(&wl->lock, flags); +} + +void intel_dmc_wl_disable(struct drm_i915_private *i915) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + unsigned long flags; + + flush_delayed_work(&wl->work); + + spin_lock_irqsave(&wl->lock, flags); + + if (!wl->enabled) + goto out_unlock; + + drm_info(&i915->drm, "DMC_WAKELOCK_CFG refcount %d\n", + refcount_read(&wl->refcount)); + + /* Disable wakelock in DMC */ + __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0); + + drm_info(&i915->drm, "DMC_WAKELOCK_CFG read 0x%0x\n", + intel_de_read(i915, DMC_WAKELOCK_CFG)); + + refcount_set(&wl->refcount, 0); + wl->enabled = false; + +out_unlock: + spin_unlock_irqrestore(&wl->lock, flags); +} + +void intel_dmc_wl_get(struct drm_i915_private *i915, i915_reg_t reg) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + unsigned long flags; + + if (!intel_dmc_wl_check_range(reg.reg)) + return; + + spin_lock_irqsave(&wl->lock, flags); + + if (!wl->enabled) + goto out_unlock; + + cancel_delayed_work(&wl->work); + + if (refcount_inc_not_zero(&wl->refcount)) + goto out_unlock; + + refcount_set(&wl->refcount, 1); + + __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, 0, DMC_WAKELOCK_CTL_REQ); + + WARN_RATELIMIT(__intel_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL, + DMC_WAKELOCK_CTL_ACK, + DMC_WAKELOCK_CTL_ACK, + DMC_WAKELOCK_CTL_TIMEOUT), + "DMC wakelock ack timed out"); + +out_unlock: + spin_unlock_irqrestore(&wl->lock, flags); +} + +void intel_dmc_wl_put(struct drm_i915_private *i915, i915_reg_t reg) +{ + struct intel_dmc_wl *wl = &i915->display.wl; + unsigned long flags; + + if (!intel_dmc_wl_check_range(reg.reg)) + return; + + spin_lock_irqsave(&wl->lock, flags); + + if (!wl->enabled) + goto out_unlock; + + if (WARN_RATELIMIT(!refcount_read(&wl->refcount), + "Tried to put wakelock with refcount zero\n")) + goto out_unlock; + + if (refcount_dec_and_test(&wl->refcount)) { + __intel_dmc_wl_release(i915); + + goto out_unlock; + } + +out_unlock: + spin_unlock_irqrestore(&wl->lock, flags); +} diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.h b/drivers/gpu/drm/i915/display/intel_dmc_wl.h new file mode 100644 index 000000000000..b649a278be71 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2023 Intel Corporation + */ + +#ifndef __INTEL_WAKELOCK_H__ +#define __INTEL_WAKELOCK_H__ + +#include +#include +#include + +#include "i915_reg_defs.h" + +struct drm_i915_private; + +struct intel_dmc_wl { + spinlock_t lock; /* protects enabled and refcount */ + bool enabled; + refcount_t refcount; + struct delayed_work work; +}; + +void intel_dmc_wl_init(struct drm_i915_private *i915); +void intel_dmc_wl_enable(struct drm_i915_private *i915); +void intel_dmc_wl_disable(struct drm_i915_private *i915); +void intel_dmc_wl_get(struct drm_i915_private *i915, i915_reg_t reg); +void intel_dmc_wl_put(struct drm_i915_private *i915, i915_reg_t reg); + +#endif /* __INTEL_WAKELOCK_H__ */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 3c3e67885559..a080c9e6f372 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -279,6 +279,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_vdsc.o \ i915-display/intel_vga.o \ i915-display/intel_vrr.o \ + i915-display/intel_dmc_wl.o \ i915-display/intel_wm.o \ i915-display/skl_scaler.o \ i915-display/skl_universal_plane.o \ From patchwork Mon Mar 18 13:37:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Coelho X-Patchwork-Id: 13595379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BCA57C54E5D for ; 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X-IronPort-AV: E=McAfee;i="6600,9927,11016"; a="16218021" X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="16218021" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="13570059" Received: from dcroitox-mobl1.ger.corp.intel.com (HELO hazy.ger.corp.intel.com) ([10.251.210.126]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:21 -0700 From: Luca Coelho To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, uma.shankar@intel.com, ville.syrjala@linux.intel.com, jani.nikula@intel.com Subject: [PATCH v3 2/4] drm/i915/display: don't allow DMC wakelock on older hardware Date: Mon, 18 Mar 2024 15:37:55 +0200 Message-Id: <20240318133757.1479189-3-luciano.coelho@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240318133757.1479189-1-luciano.coelho@intel.com> References: <20240318133757.1479189-1-luciano.coelho@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Only allow running DMC wakelock code if the display version is 20 or greater. Signed-off-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_dmc_wl.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 5c3d8204ae7e..7c991e22c616 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -120,6 +120,9 @@ void intel_dmc_wl_enable(struct drm_i915_private *i915) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; + if (DISPLAY_VER(i915) < 20) + return; + spin_lock_irqsave(&wl->lock, flags); if (wl->enabled) @@ -143,6 +146,9 @@ void intel_dmc_wl_disable(struct drm_i915_private *i915) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; + if (DISPLAY_VER(i915) < 20) + return; + flush_delayed_work(&wl->work); spin_lock_irqsave(&wl->lock, flags); @@ -171,6 +177,9 @@ void intel_dmc_wl_get(struct drm_i915_private *i915, i915_reg_t reg) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; + if (DISPLAY_VER(i915) < 20) + return; + if (!intel_dmc_wl_check_range(reg.reg)) return; @@ -203,6 +212,9 @@ void intel_dmc_wl_put(struct drm_i915_private *i915, i915_reg_t reg) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; + if (DISPLAY_VER(i915) < 20) + return; + if (!intel_dmc_wl_check_range(reg.reg)) return; From patchwork Mon Mar 18 13:37:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Coelho X-Patchwork-Id: 13595380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E9D1C54E68 for ; Mon, 18 Mar 2024 13:38:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8D3910F74F; Mon, 18 Mar 2024 13:38:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="WvbJ5Ws4"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 604C510F74F; Mon, 18 Mar 2024 13:38:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710769105; x=1742305105; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mCdSMUfq6nstTWjKtY5hhEi2Q94CFeV1UhqEmEv3iik=; b=WvbJ5Ws411/PdQ1XVDpscXiOKs4YFnDVZmuRXqHC98e6oZHCSepGZdyp qtdSnnvXSP3pQ1ESOjnMHSMHYeeJgOvyceRhfwkPCpWOJcyAP8jYa4exx cet9c9GVm6xrp+0mBG2SQsQk80PaW0uBjdjzrX84+xm9JlDwykpGSNb30 3WkXby4TAMn9k+02lgH/s0uhnnifmIL7nMm9wOABNiAufpDMWQpmNQiMp 2/AQPLDfRYU35K6+OYrg5QXzdClwMZsrfpPGZBGs7dTF5Ei9oB8R2dmaF BdVvxfTefFC+wkWI9+M3pewoNlOnn63K6eelYr710oAZ9YeNQR8eb/Va/ A==; X-IronPort-AV: E=McAfee;i="6600,9927,11016"; a="16218024" X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="16218024" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="13570081" Received: from dcroitox-mobl1.ger.corp.intel.com (HELO hazy.ger.corp.intel.com) ([10.251.210.126]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:22 -0700 From: Luca Coelho To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, uma.shankar@intel.com, ville.syrjala@linux.intel.com, jani.nikula@intel.com Subject: [PATCH v3 3/4] drm/i915/display: add module parameter to enable DMC wakelock Date: Mon, 18 Mar 2024 15:37:56 +0200 Message-Id: <20240318133757.1479189-4-luciano.coelho@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240318133757.1479189-1-luciano.coelho@intel.com> References: <20240318133757.1479189-1-luciano.coelho@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This feature should be disabled by default until properly tested and mature. Add a module parameter to enable the feature for testing, while keeping it disabled by default for now. Signed-off-by: Luca Coelho Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display_params.h | 1 + drivers/gpu/drm/i915/display/intel_dmc_wl.c | 12 ++++++++---- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 11e03cfb774d..f40b223cc8a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -116,6 +116,11 @@ intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, "(0=disabled, 1=enabled) " "Default: 1"); +intel_display_param_named_unsafe(enable_dmc_wl, bool, 0400, + "Enable DMC wakelock " + "(0=disabled, 1=enabled) " + "Default: 0"); + __maybe_unused static void _param_print_bool(struct drm_printer *p, const char *driver_name, const char *name, bool val) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.h b/drivers/gpu/drm/i915/display/intel_display_params.h index 6206cc51df04..bf8dbbdb20a1 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.h +++ b/drivers/gpu/drm/i915/display/intel_display_params.h @@ -46,6 +46,7 @@ struct drm_i915_private; param(int, enable_psr, -1, 0600) \ param(bool, psr_safest_params, false, 0400) \ param(bool, enable_psr2_sel_fetch, true, 0400) \ + param(bool, enable_dmc_wl, false, 0400) \ #define MEMBER(T, member, ...) T member; struct intel_display_params { diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c index 7c991e22c616..84d054bcb2c1 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c @@ -120,7 +120,8 @@ void intel_dmc_wl_enable(struct drm_i915_private *i915) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; - if (DISPLAY_VER(i915) < 20) + if (!i915->display.params.enable_dmc_wl || + DISPLAY_VER(i915) < 20) return; spin_lock_irqsave(&wl->lock, flags); @@ -146,7 +147,8 @@ void intel_dmc_wl_disable(struct drm_i915_private *i915) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; - if (DISPLAY_VER(i915) < 20) + if (!i915->display.params.enable_dmc_wl || + DISPLAY_VER(i915) < 20) return; flush_delayed_work(&wl->work); @@ -177,7 +179,8 @@ void intel_dmc_wl_get(struct drm_i915_private *i915, i915_reg_t reg) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; - if (DISPLAY_VER(i915) < 20) + if (!i915->display.params.enable_dmc_wl || + DISPLAY_VER(i915) < 20) return; if (!intel_dmc_wl_check_range(reg.reg)) @@ -212,7 +215,8 @@ void intel_dmc_wl_put(struct drm_i915_private *i915, i915_reg_t reg) struct intel_dmc_wl *wl = &i915->display.wl; unsigned long flags; - if (DISPLAY_VER(i915) < 20) + if (!i915->display.params.enable_dmc_wl || + DISPLAY_VER(i915) < 20) return; if (!intel_dmc_wl_check_range(reg.reg)) From patchwork Mon Mar 18 13:37:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Coelho X-Patchwork-Id: 13595381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A0F8C54E68 for ; Mon, 18 Mar 2024 13:38:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B59E810EF0D; Mon, 18 Mar 2024 13:38:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GDATvsAJ"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8483E10F74D; Mon, 18 Mar 2024 13:38:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710769107; x=1742305107; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lhF65XRkLePdsVNSatfYL0Ods1iGsHeaiNcqlrUSDGM=; b=GDATvsAJI+KkEVO4v1yuOb4ZnkGuuqomgYJ/JauTBSXZSpHuUUIG9bTm Eiww/ccRZ9MfEdH3WVzoICOHAFkLhpR1VWx2QkMpjJvXh1YBc2PpoekXb 0y72RJ6VBKzg273qoDcRNm0jtkFakeFkNh1JsO1Q1KBmxNEUuCu8RPeye JntJ06ISeyj2w+wiCmAi+kOiUUjFvllNnZNhF1osl9Mp/8yfGSycG8M/G 0SXCWpSUBapTu/q9VMBboYBMBvscVTTmGGmecHisMd8y7d3G9H5zojFoS JriP/TDfo+sZnsQwyyCoRrQsaB/MvVd+oX3Mufua2CwNTWaB0CWEHOPG9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,11016"; a="16218025" X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="16218025" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,134,1708416000"; d="scan'208";a="13570086" Received: from dcroitox-mobl1.ger.corp.intel.com (HELO hazy.ger.corp.intel.com) ([10.251.210.126]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Mar 2024 06:38:25 -0700 From: Luca Coelho To: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, uma.shankar@intel.com, ville.syrjala@linux.intel.com, jani.nikula@intel.com Subject: [PATCH v3 4/4] drm/i915/display: tie DMC wakelock to DC5/6 state transitions Date: Mon, 18 Mar 2024 15:37:57 +0200 Message-Id: <20240318133757.1479189-5-luciano.coelho@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240318133757.1479189-1-luciano.coelho@intel.com> References: <20240318133757.1479189-1-luciano.coelho@intel.com> MIME-Version: 1.0 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We only need DMC wakelocks when we allow DC5 and DC6 states. Add the calls to enable and disable DMC wakelock accordingly. Signed-off-by: Luca Coelho --- drivers/gpu/drm/i915/display/intel_display_power_well.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 217f82f1da84..367464f5c5cd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -17,6 +17,7 @@ #include "intel_dkl_phy.h" #include "intel_dkl_phy_regs.h" #include "intel_dmc.h" +#include "intel_dmc_wl.h" #include "intel_dp_aux_regs.h" #include "intel_dpio_phy.h" #include "intel_dpll.h" @@ -821,6 +822,8 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); + intel_dmc_wl_enable(dev_priv); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } @@ -850,6 +853,8 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, SKL_SELECT_ALTERNATE_DC_EXIT); + intel_dmc_wl_enable(dev_priv); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); } @@ -970,6 +975,8 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; + intel_dmc_wl_disable(dev_priv); + intel_cdclk_get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ drm_WARN_ON(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 3fa851b5c7a6..b20cc018b9a8 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -550,6 +550,8 @@ void intel_dmc_disable_program(struct drm_i915_private *i915) pipedmc_clock_gating_wa(i915, true); disable_all_event_handlers(i915); pipedmc_clock_gating_wa(i915, false); + + intel_dmc_wl_disable(i915); } void assert_dmc_loaded(struct drm_i915_private *i915) @@ -1079,6 +1081,8 @@ void intel_dmc_suspend(struct drm_i915_private *i915) if (dmc) flush_work(&dmc->work); + intel_dmc_wl_disable(i915); + /* Drop the reference held in case DMC isn't loaded. */ if (!intel_dmc_has_payload(i915)) intel_dmc_runtime_pm_put(i915);