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Add the "renesas,r9a09g057-ostm" compatible string for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley --- Documentation/devicetree/bindings/timer/renesas,ostm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml index 8b06a681764e..e8c642166462 100644 --- a/Documentation/devicetree/bindings/timer/renesas,ostm.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,ostm.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five - renesas,r9a07g044-ostm # RZ/G2{L,LC} - renesas,r9a07g054-ostm # RZ/V2L + - renesas,r9a09g057-ostm # RZ/V2H(P) - const: renesas,ostm # Generic reg: @@ -58,6 +59,7 @@ if: - renesas,r9a07g043-ostm - renesas,r9a07g044-ostm - renesas,r9a07g054-ostm + - renesas,r9a09g057-ostm then: required: - resets From patchwork Mon Mar 18 16:07:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 13595516 X-Patchwork-Delegate: geert@linux-m68k.org Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 262B453385; 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Mon, 18 Mar 2024 09:08:39 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2500:a01:c23f:76ae:8149:291]) by smtp.gmail.com with ESMTPSA id by19-20020a056000099300b0034174875850sm2686930wrb.70.2024.03.18.09.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Mar 2024 09:08:38 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chris Brandt , Magnus Damm Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH 2/2] clocksource/drivers/renesas-ostm: Add OSTM support for RZ/V2H(P) SoC Date: Mon, 18 Mar 2024 16:07:31 +0000 Message-Id: <20240318160731.33960-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240318160731.33960-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240318160731.33960-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lad Prabhakar RZ/V2H(P) (R9A09G057) SoC has Generic Timer Module(a.k.a OSTM) which needs to deassert the reset line before accessing any registers just like the RZ/G2L SoC. Enable the entry point for RZ/V2H(P) SoC so that we can deassert the reset line in probe callback. While at it use IS_ENABLED() macro instead of open coding. Signed-off-by: Lad Prabhakar --- drivers/clocksource/renesas-ostm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clocksource/renesas-ostm.c b/drivers/clocksource/renesas-ostm.c index 8da972dc1713..b8b3c82b2528 100644 --- a/drivers/clocksource/renesas-ostm.c +++ b/drivers/clocksource/renesas-ostm.c @@ -224,7 +224,7 @@ static int __init ostm_init(struct device_node *np) TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init); -#ifdef CONFIG_ARCH_RZG2L +#if IS_ENABLED(CONFIG_ARCH_RZG2L) || IS_ENABLED(CONFIG_ARCH_R9A09G057) static int __init ostm_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev;