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Wed, 20 Mar 2024 15:22:04 +0000 Received: from TY3P286MB2754.JPNP286.PROD.OUTLOOK.COM ([fe80::d127:7317:59e9:143e]) by TY3P286MB2754.JPNP286.PROD.OUTLOOK.COM ([fe80::d127:7317:59e9:143e%4]) with mapi id 15.20.7386.030; Wed, 20 Mar 2024 15:22:04 +0000 From: Songyang Li To: tsbogend@alpha.franken.de Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Songyang Li Subject: [PATCH] MIPS: Octeon: Add PCIe link status check Date: Wed, 20 Mar 2024 23:22:00 +0800 Message-ID: X-Mailer: git-send-email 2.25.1 X-TMN: [xSexVDk8IWs74z85TBYDJvZ4tq2DCD/T] X-ClientProxiedBy: TYCP286CA0048.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b5::11) To TY3P286MB2754.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:256::8) X-Microsoft-Original-Message-ID: <20240320152200.8271-1-leesongyang@outlook.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY3P286MB2754:EE_|TY3P286MB2562:EE_ X-MS-Office365-Filtering-Correlation-Id: 4815c572-31e0-400c-f7ee-08dc48f17f2e X-MS-Exchange-SLBlob-MailProps: Vs63Iqe4sQk8N0yY9albUc+E2gbT5Qb45bcPRRKiE0NCRmCl89oJwaR7LhkAkC9rNTLh/6WerkVWBIXK3xyRivGAbYA35+xQkGmQQzoTjVaZTqjVgVTfxJMftZjDSa8g89IvGu7osMPfAA8G7zjRe1ECIVIo5Yc4n6MDdZkRrxLDjG1PBnFc6J0vsJqir2Tgf4Y3olSIJd0sfbykQbPqtRiiS+uD80ddAKcMUnudh/jEDyQ9Da5bfwGLx2u+JCbmHtGG2KmcRq5Rny9GV3/bLFnCohhl8fYiSiZG1mXixEe+P8xZ5r9k2KDPnPxc47aPVFjQPDXqxxfLvx2hILqQfUlXorBF6BNmdYw38YVk3uQzTjQYWw1dshs4wplrSDvNj1zeXIkVDDA8aW/UlNoTDdW1VROiqD0dxResfLp+6/UDqoaP9CBEICRtP/c4pcKe7gOyd8caGEvVRGBjbbCFMJdn4XccW0zsrgjWotWfjNu/TkZgESfH42yWcVGXruS535zw3pNvDQIb131Plhf+muNwt7bCVZ5JKZ8LZyamvN4IlFLro4hLWKBHbSaBrpg3aJ/Iz6bp/KpfCFPDdHCREEw3u62OUBRBvDygdm7B8DkHMCWydz1KT8rVqiEJXgpXmxlUrpkZROAy7Z/o6rjv97IF4c6Oee7/yVF/GJU0IB5ACxL199HdZsEp0XHlchIBhk6vJD931sm7zHnU/SSbzw+1G+ma/GJkwIk69BBxbh0= X-Microsoft-Antispam: BCL:0; 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So it is necessary to add PCIe link status check for system protection. When the PCIe link is down or in training, assigning a value of 0 to the configuration address can prevent read-write behavior to the configuration space of peripheral PCIe devices, thereby preventing kernel panic. Signed-off-by: Songyang Li --- arch/mips/pci/pcie-octeon.c | 6 ++++++ 1 file changed, 6 insertions(+) mode change 100644 => 100755 arch/mips/pci/pcie-octeon.c diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c old mode 100644 new mode 100755 index 2583e318e8c6..b080c7c6cc46 --- a/arch/mips/pci/pcie-octeon.c +++ b/arch/mips/pci/pcie-octeon.c @@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus, { union cvmx_pcie_address pcie_addr; union cvmx_pciercx_cfg006 pciercx_cfg006; + union cvmx_pciercx_cfg032 pciercx_cfg032; pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port)); if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) return 0; + pciercx_cfg032.u32 = + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); + if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)) + return 0; + pcie_addr.u64 = 0; pcie_addr.config.upper = 2; pcie_addr.config.io = 1;