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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:08 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:54 +0100 Subject: [PATCH v2 1/6] clk: qcom: apss-ipq-pll: reuse Stromer reg offsets from 'clk_alpha_pll_regs' Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-1-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The register offset array defined locally for the CLK_ALPHA_PLL_TYPE_STROMER_PLUS is the same as the entry defined for CLK_ALPHA_PLL_TYPE_STROMER in the 'clk_alpha_pll_regs' array. To avoid code duplication, remove the local definition and use the global one instead. No functional changes. Reviewed-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio --- Changes in v2: - add Reviewed-by tag from Dmitry - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-1-52f795429d5d@gmail.com Depends on the following patches: - "clk: qcom: apss-ipq-pll: use stromer ops for IPQ5018 to fix boot failure" Link: https://lore.kernel.org/r/20240315-apss-ipq-pll-ipq5018-hang-v2-1-6fe30ada2009@gmail.com - "clk: qcom: clk-alpha-pll: Stromer register cleanup" Link: https://lore.kernel.org/r/20240311-alpha-pll-stromer-cleanup-v1-0-f7c0c5607cca@gmail.com --- drivers/clk/qcom/apss-ipq-pll.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index dfffec2f06ae7..ed3e6405f99cb 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -24,17 +24,6 @@ static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL] = 0x30, [PLL_OFF_TEST_CTL_U] = 0x34, }, - [CLK_ALPHA_PLL_TYPE_STROMER_PLUS] = { - [PLL_OFF_L_VAL] = 0x08, - [PLL_OFF_ALPHA_VAL] = 0x10, - [PLL_OFF_ALPHA_VAL_U] = 0x14, - [PLL_OFF_USER_CTL] = 0x18, - [PLL_OFF_USER_CTL_U] = 0x1c, - [PLL_OFF_CONFIG_CTL] = 0x20, - [PLL_OFF_STATUS] = 0x28, - [PLL_OFF_TEST_CTL] = 0x30, - [PLL_OFF_TEST_CTL_U] = 0x34, - }, }; static struct clk_alpha_pll ipq_pll_huayra = { @@ -57,12 +46,7 @@ static struct clk_alpha_pll ipq_pll_huayra = { static struct clk_alpha_pll ipq_pll_stromer = { .offset = 0x0, - /* - * Reuse CLK_ALPHA_PLL_TYPE_STROMER_PLUS register offsets. - * Although this is a bit confusing, but the offset values - * are correct nevertheless. - */ - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER], .flags = SUPPORTS_DYNAMIC_UPDATE, .clkr = { .enable_reg = 0x0, @@ -80,7 +64,11 @@ static struct clk_alpha_pll ipq_pll_stromer = { static struct clk_alpha_pll ipq_pll_stromer_plus = { .offset = 0x0, - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + /* + * The register offsets of the Stromer Plus PLL used in IPQ5332 + * are the same as the Stromer PLL's offsets. + */ + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER], .flags = SUPPORTS_DYNAMIC_UPDATE, .clkr = { .enable_reg = 0x0, From patchwork Thu Mar 21 07:49:55 2024 Content-Type: text/plain; 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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:09 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:55 +0100 Subject: [PATCH v2 2/6] clk: qcom: apss-ipq-pll: move Huayra register map to 'clk_alpha_pll_regs' Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-2-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 Move the locally defined Huayra register map to 'clk_alpha_pll_regs' in order to allow using that by other drivers, like the clk-cbf-8996. No functional changes. Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- Changes in v2: - rework the patch as requested by Dmitry Baryshkov by moving the register map into clk-alpha-pll.c instead of keeping that locally - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-2-52f795429d5d@gmail.com --- drivers/clk/qcom/apss-ipq-pll.c | 20 +------------------- drivers/clk/qcom/clk-alpha-pll.c | 10 ++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index ed3e6405f99cb..8cf17374a2e2a 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -8,27 +8,9 @@ #include "clk-alpha-pll.h" -/* - * Even though APSS PLL type is of existing one (like Huayra), its offsets - * are different from the one mentioned in the clk-alpha-pll.c, since the - * PLL is specific to APSS, so lets the define the same. - */ -static const u8 ipq_pll_offsets[][PLL_OFF_MAX_REGS] = { - [CLK_ALPHA_PLL_TYPE_HUAYRA] = { - [PLL_OFF_L_VAL] = 0x08, - [PLL_OFF_ALPHA_VAL] = 0x10, - [PLL_OFF_USER_CTL] = 0x18, - [PLL_OFF_CONFIG_CTL] = 0x20, - [PLL_OFF_CONFIG_CTL_U] = 0x24, - [PLL_OFF_STATUS] = 0x28, - [PLL_OFF_TEST_CTL] = 0x30, - [PLL_OFF_TEST_CTL_U] = 0x34, - }, -}; - static struct clk_alpha_pll ipq_pll_huayra = { .offset = 0x0, - .regs = ipq_pll_offsets[CLK_ALPHA_PLL_TYPE_HUAYRA], + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS], .flags = SUPPORTS_DYNAMIC_UPDATE, .clkr = { .enable_reg = 0x0, diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 55a77e36dc44c..ba039b2b24a09 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -82,6 +82,16 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x20, [PLL_OFF_STATUS] = 0x24, }, + [CLK_ALPHA_PLL_TYPE_HUAYRA_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_STATUS] = 0x28, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + }, [CLK_ALPHA_PLL_TYPE_BRAMMO] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index a1a75bb12fe88..d057955138952 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -15,6 +15,7 @@ enum { CLK_ALPHA_PLL_TYPE_DEFAULT, CLK_ALPHA_PLL_TYPE_HUAYRA, + CLK_ALPHA_PLL_TYPE_HUAYRA_APSS, CLK_ALPHA_PLL_TYPE_BRAMMO, CLK_ALPHA_PLL_TYPE_FABIA, CLK_ALPHA_PLL_TYPE_TRION, From patchwork Thu Mar 21 07:49:56 2024 Content-Type: text/plain; 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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:11 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:56 +0100 Subject: [PATCH v2 3/6] clk: qcom: apss-ipq-pll: remove 'pll_type' field from struct 'apss_pll_data' Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-3-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The value of the 'pll_type' field of 'struct apps_pll_data' is used only by the probe function to decide which config function should be called for the actual PLL. However this can be derived also from the 'pll' field which makes the 'pll_type' field redundant. Additionally, the CLK_ALPHA_PLL_TYPE_* enumeration values are meant to be used as indices to the 'clk_alpha_pll_regs' array so using those to define the pll type in this driver is misleading anyway. Change the probe function to use the 'pll' field to determine the configuration function to be used, and remove the 'pll_type' field to simplify the code. No functional changes. Signed-off-by: Gabor Juhos --- Changes in v2: - no changes - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-3-52f795429d5d@gmail.com --- drivers/clk/qcom/apss-ipq-pll.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index 8cf17374a2e2a..816b0d1f8d8c8 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -131,37 +131,31 @@ static const struct alpha_pll_config ipq9574_pll_config = { }; struct apss_pll_data { - int pll_type; struct clk_alpha_pll *pll; const struct alpha_pll_config *pll_config; }; static const struct apss_pll_data ipq5018_pll_data = { - .pll_type = CLK_ALPHA_PLL_TYPE_STROMER, .pll = &ipq_pll_stromer, .pll_config = &ipq5018_pll_config, }; static struct apss_pll_data ipq5332_pll_data = { - .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS, .pll = &ipq_pll_stromer_plus, .pll_config = &ipq5332_pll_config, }; static struct apss_pll_data ipq8074_pll_data = { - .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA, .pll = &ipq_pll_huayra, .pll_config = &ipq8074_pll_config, }; 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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:12 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:57 +0100 Subject: [PATCH v2 4/6] clk: qcom: apss-ipq-pll: constify match data structures Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-4-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The match data structures are used only by the apss_ipq_pll_probe() function and are never modified so mark those as constant. No functional changes. Reviewed-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos Reviewed-by: Konrad Dybcio --- Changes in v2: - add Reviewed-by tag from Dmitry - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-4-52f795429d5d@gmail.com --- drivers/clk/qcom/apss-ipq-pll.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index 816b0d1f8d8c8..49da67435d4fe 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -140,22 +140,22 @@ static const struct apss_pll_data ipq5018_pll_data = { .pll_config = &ipq5018_pll_config, }; -static struct apss_pll_data ipq5332_pll_data = { +static const struct apss_pll_data ipq5332_pll_data = { .pll = &ipq_pll_stromer_plus, .pll_config = &ipq5332_pll_config, }; -static struct apss_pll_data ipq8074_pll_data = { +static const struct apss_pll_data ipq8074_pll_data = { .pll = &ipq_pll_huayra, .pll_config = &ipq8074_pll_config, }; -static struct apss_pll_data ipq6018_pll_data = { +static const struct apss_pll_data ipq6018_pll_data = { .pll = &ipq_pll_huayra, .pll_config = &ipq6018_pll_config, }; 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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:14 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:58 +0100 Subject: [PATCH v2 5/6] clk: qcom: apss-ipq-pll: constify clk_init_data structures Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-5-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The clk_init_data structures are never modified, so add const qualifier to the ones where it is missing. No functional changes. Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- Changes in v2: - no changes - Link to v1: https://lore.kernel.org/r/20240318-apss-ipq-pll-cleanup-v1-5-52f795429d5d@gmail.com --- drivers/clk/qcom/apss-ipq-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c index 49da67435d4fe..5bbf329c9bdd1 100644 --- a/drivers/clk/qcom/apss-ipq-pll.c +++ b/drivers/clk/qcom/apss-ipq-pll.c @@ -15,7 +15,7 @@ static struct clk_alpha_pll ipq_pll_huayra = { .clkr = { .enable_reg = 0x0, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "a53pll", .parent_data = &(const struct clk_parent_data) { .fw_name = "xo", @@ -55,7 +55,7 @@ static struct clk_alpha_pll ipq_pll_stromer_plus = { .clkr = { .enable_reg = 0x0, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "a53pll", .parent_data = &(const struct clk_parent_data) { .fw_name = "xo", From patchwork Thu Mar 21 07:49:59 2024 Content-Type: text/plain; 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[87.101.120.23]) by smtp.googlemail.com with ESMTPSA id p1-20020a05600c1d8100b004146bda6c32sm4637096wms.9.2024.03.21.00.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 00:50:15 -0700 (PDT) From: Gabor Juhos Date: Thu, 21 Mar 2024 08:49:59 +0100 Subject: [PATCH v2 6/6] clk: qcom: clk-cbf-8996: use HUAYRA_APPS register map for cbf_pll Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-apss-ipq-pll-cleanup-v2-6-201f3cf79fd4@gmail.com> References: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> In-Reply-To: <20240321-apss-ipq-pll-cleanup-v2-0-201f3cf79fd4@gmail.com> To: Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Gabor Juhos X-Mailer: b4 0.12.3 The register map used for 'cbf_pll' is the same as the one defined for the CLK_ALPHA_PLL_TYPE_HUAYRA_APSS indice in the 'clk_alpha_pll_regs' array. Drop the local register map and use the global one instead to reduce code duplication. No functional changes intended. Compile tested only. Suggested-by: Dmitry Baryshkov Signed-off-by: Gabor Juhos Reviewed-by: Dmitry Baryshkov --- Changes since v1: - new patch Note: Although this patch is not strictly related to the subject of the series but as the change has been suggested by Dmitry during the review process it has been added here for completeness. --- drivers/clk/qcom/clk-cbf-8996.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clk-cbf-8996.c b/drivers/clk/qcom/clk-cbf-8996.c index fe24b4abeab48..76bf523431b85 100644 --- a/drivers/clk/qcom/clk-cbf-8996.c +++ b/drivers/clk/qcom/clk-cbf-8996.c @@ -41,17 +41,6 @@ enum { #define CBF_PLL_OFFSET 0xf000 -static const u8 cbf_pll_regs[PLL_OFF_MAX_REGS] = { - [PLL_OFF_L_VAL] = 0x08, - [PLL_OFF_ALPHA_VAL] = 0x10, - [PLL_OFF_USER_CTL] = 0x18, - [PLL_OFF_CONFIG_CTL] = 0x20, - [PLL_OFF_CONFIG_CTL_U] = 0x24, - [PLL_OFF_TEST_CTL] = 0x30, - [PLL_OFF_TEST_CTL_U] = 0x34, - [PLL_OFF_STATUS] = 0x28, -}; - static struct alpha_pll_config cbfpll_config = { .l = 72, .config_ctl_val = 0x200d4828, @@ -67,7 +56,7 @@ static struct alpha_pll_config cbfpll_config = { static struct clk_alpha_pll cbf_pll = { .offset = CBF_PLL_OFFSET, - .regs = cbf_pll_regs, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA_APSS], .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE, .clkr.hw.init = &(struct clk_init_data){ .name = "cbf_pll",