From patchwork Thu Mar 21 15:48:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 18C9EC54E68 for ; Thu, 21 Mar 2024 15:49:30 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKf3-0004Jn-AN; Thu, 21 Mar 2024 11:48:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKf1-0004JT-Iq for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:48:55 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKez-0001BU-Lb for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:48:55 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-41466e01965so7931095e9.3 for ; Thu, 21 Mar 2024 08:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036131; x=1711640931; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; b=d2jICh1dd4XIjkMWk8imYmpKT9o4rOLdhDCls43AAKP3nsU9riB59s0ZTYeXFMY9dj FS0F7q8MMIxsR1dvd7n4pvSj0PORqRshsN9wiYCNwyNHME3hGoGIiPVX9FPF16X3kPFI 2ZE1ORKaloEMfv6+/wfpA5EurTUEeMDAzfRseHysj8mG+ujmy/HO8rMIH+TAOBZNx+05 Mb6RHetRCj2peiAKX/IgH5Y0YGZBHmKyD0OgqwgJ8v1Xc+n65CuYLzPX8SPJPvypByrE 8ag0DPjWoSYpDGROeS2Mza34EuAYjYeLurz4Y0a4kcLHqeAQP/7gNoSbCf/lyKS/g/Fi rkZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036131; x=1711640931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bTgCkgY7q586A21zu0JSDs5UTTpVyxNoAlIlHHAmSdk=; b=xNNcF7V1MkV/6pw6mzeZzTncyizEb5mwLZh+xWh3Mj2ympw0c4TIj/OszloDtK70Uo HB4va3NVTswdObdhPii8EXrPG6qdDcpQC1dZxEH/fOWXUEqFHiTK4qvKpxDNI7TDh6BI TWDFlYlyeNufNqApNoy97g23ZtnYztz+iXfbaGsysaCSXdy7iZX8fd69dBbNuxDdavMg MH6dif4zXBo5pFtrKEvOiI4wpu8dvpMqVP0THSZ9eA5i8pmOv0nyzV6Sf/wZs4SiqNP6 14S6s4MxStkPIafBNtx5sOusZ3ifsYxwX9957dGVxHFMWljeptz25xKM+BhOUfMeFQjh tRTg== X-Gm-Message-State: AOJu0YxXup4WrKglA2WXN3pzkJEdO+Ma02hwniCCktgtIuMcuHukaZAw CCx5ivDF5GIrYLpPji7HOk3gDjcWEmqdhaiHWi+ajZhE7CPe7s2W/pXLLFKpaRjfeGiJevSAGUa wCKs= X-Google-Smtp-Source: AGHT+IE92dHNbX39E5CpL6fzghojPWn69hg0rMxVmayS2tpnQqnqbNz6dlTYqB9LpiS/OQbj/28ECQ== X-Received: by 2002:a05:600c:3514:b0:414:63c4:c40d with SMTP id h20-20020a05600c351400b0041463c4c40dmr6529657wmq.40.1711036130799; Thu, 21 Mar 2024 08:48:50 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id t6-20020a05600c198600b004131310a29fsm141401wmq.15.2024.03.21.08.48.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:48:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.0? 01/21] host/atomic128: Include missing 'qemu/atomic.h' header Date: Thu, 21 Mar 2024 16:48:17 +0100 Message-ID: <20240321154838.95771-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org qatomic_cmpxchg__nocheck(), qatomic_read__nocheck(), qatomic_set__nocheck() are defined in "qemu/atomic.h". Include it in order to avoid: In file included from include/exec/helper-proto.h:10: In file included from include/exec/helper-proto-common.h:10: In file included from include/qemu/atomic128.h:61: In file included from host/include/aarch64/host/atomic128-cas.h:16: host/include/generic/host/atomic128-cas.h:23:11: error: call to undeclared function 'qatomic_cmpxchg__nocheck'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] r.i = qatomic_cmpxchg__nocheck(ptr_align, c.i, n.i); ^ Signed-off-by: Philippe Mathieu-Daudé --- host/include/generic/host/atomic128-cas.h | 2 ++ host/include/generic/host/atomic128-ldst.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/host/include/generic/host/atomic128-cas.h b/host/include/generic/host/atomic128-cas.h index 6b40cc2271..4824f14659 100644 --- a/host/include/generic/host/atomic128-cas.h +++ b/host/include/generic/host/atomic128-cas.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_CAS_H #define HOST_ATOMIC128_CAS_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) static inline Int128 ATTRIBUTE_ATOMIC128_OPT atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) diff --git a/host/include/generic/host/atomic128-ldst.h b/host/include/generic/host/atomic128-ldst.h index 691e6a8531..12e4aca2da 100644 --- a/host/include/generic/host/atomic128-ldst.h +++ b/host/include/generic/host/atomic128-ldst.h @@ -11,6 +11,8 @@ #ifndef HOST_ATOMIC128_LDST_H #define HOST_ATOMIC128_LDST_H +#include "qemu/atomic.h" + #if defined(CONFIG_ATOMIC128) # define HAVE_ATOMIC128_RO 1 # define HAVE_ATOMIC128_RW 1 From patchwork Thu Mar 21 15:48:18 2024 Content-Type: text/plain; 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Thu, 21 Mar 2024 08:48:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 02/21] hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h Date: Thu, 21 Mar 2024 16:48:18 +0100 Message-ID: <20240321154838.95771-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Commit fd3f7d24d4 ("include/hw/core: Remove i386 conditional on fake_user_interrupt") remove the need to check on NEED_CPU_H. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index bf8ff8e3ee..88857eb921 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -49,7 +49,6 @@ struct TCGCPUOps { /** @debug_excp_handler: Callback for handling debug exceptions */ void (*debug_excp_handler)(CPUState *cpu); -#ifdef NEED_CPU_H #ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. @@ -174,7 +173,6 @@ struct TCGCPUOps { */ bool (*need_replay_interrupt)(int interrupt_request); #endif /* !CONFIG_USER_ONLY */ -#endif /* NEED_CPU_H */ }; From patchwork Thu Mar 21 15:48:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599010 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E013FCD11C2 for ; Thu, 21 Mar 2024 15:50:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKfU-0004sm-JY; Thu, 21 Mar 2024 11:49:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKfQ-0004ds-64 for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:49:20 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKfH-0001Fv-GA for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:49:16 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4146feb33e1so8759355e9.2 for ; Thu, 21 Mar 2024 08:49:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036146; x=1711640946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Uml8evcLi9xkWgCFD8gP1/OkUGdeyARM6PHY5ELWBs=; b=dTeYg3U/cwhEnshK10ojj7HgizCwdzRaO+SjS/8d4AHMV3Gtg7H+hwp+TiM90wlYkN N87nFIjtmoj9i9u67lWZjOjcKW992T9kuu2q01UebM1RMpc/1ECcFip9tLk+NodTiTi7 QpH/nfdl+2Bv6j6d8YgKPbS6xre3d2K2j/QYlqQwe4mhuyxbWEZSSbT/C22ZLRxXdS51 zIXx5x6BgqDN7zNuig46DeWiWHVhh0mRn9cvKMdQDYIRKad3x3OtxuutvsJ69lmIJxVm BODuy1ALwcsIX6RUGHO3QXpDUHnDaTPvJ9lc8ALGk+QO33/TsuDtAS0w2DSTF4i5WU4J x0QA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036146; x=1711640946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Uml8evcLi9xkWgCFD8gP1/OkUGdeyARM6PHY5ELWBs=; b=hPOL1bx49Ij/+y4Rk5VdRsrp4qwwZQ2s2MIIlGfpuNCqHvQwBSUzhgJnKafZW0iZ3T lySVn+VFg/IqOYFb3lkgBlIoLqOb/0T9M7YMFiS7JMK/w1zczSf7imC9/JgTUd3Ft854 OIN9jzr0QkCeBaR5R/LqGMBNmk3d6LQnbniROu+OvE9MFip0hctFNng8Bs3JaYJpyac7 ymjNmAEEf2BLsiCoGgObI5S0ffK98C+brjBEHO5i18jedglTN0E86Mt0UywHZaq6ZO1I gpE0CMm3/onHmhwIcIvq4sckTM/VBzT+9LtDr3in7WDDsyxC3nLFEhOjyfpMOqOQ4Juu vXNQ== X-Gm-Message-State: AOJu0YyTHM9i2ha5IqtiKr41MONfRzC7d5f0TXwdhG6+5fZLIb3Tyxv+ aITxQuetXHxPLIxQZo25Fre/Td40vYBNAfsIcRhtY4niGHKzU17rPaT7N5ucssKZsPIBOyDqgc+ w2D0= X-Google-Smtp-Source: AGHT+IFAw5OqL09R7bmcyeZ9YyOFejxWkGzyRzgg8/RdS1yUB7jjDdFHJRAFWdetwbNp/D/m0mJFLQ== X-Received: by 2002:a05:600c:4ecf:b0:413:ee4c:57e4 with SMTP id g15-20020a05600c4ecf00b00413ee4c57e4mr7568498wmq.8.1711036145816; Thu, 21 Mar 2024 08:49:05 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id fc12-20020a05600c524c00b0041477d83499sm136619wmb.16.2024.03.21.08.49.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 03/21] target/i386: Move APIC related code to cpu-apic.c Date: Thu, 21 Mar 2024 16:48:19 +0100 Message-ID: <20240321154838.95771-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move APIC related code split in cpu-sysemu.c and monitor.c to cpu-apic.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu --- target/i386/cpu-apic.c | 112 +++++++++++++++++++++++++++++++++++++++ target/i386/cpu-sysemu.c | 77 --------------------------- target/i386/monitor.c | 25 --------- target/i386/meson.build | 1 + 4 files changed, 113 insertions(+), 102 deletions(-) create mode 100644 target/i386/cpu-apic.c diff --git a/target/i386/cpu-apic.c b/target/i386/cpu-apic.c new file mode 100644 index 0000000000..d397ec94dc --- /dev/null +++ b/target/i386/cpu-apic.c @@ -0,0 +1,112 @@ +/* + * QEMU x86 CPU <-> APIC + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" +#include "qapi/qmp/qdict.h" +#include "qapi/error.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" +#include "sysemu/hw_accel.h" +#include "sysemu/kvm.h" +#include "sysemu/xen.h" +#include "exec/address-spaces.h" +#include "hw/qdev-properties.h" +#include "hw/i386/apic_internal.h" +#include "cpu-internal.h" + +APICCommonClass *apic_get_class(Error **errp) +{ + const char *apic_type = "apic"; + + /* TODO: in-kernel irqchip for hvf */ + if (kvm_enabled()) { + if (!kvm_irqchip_in_kernel()) { + error_setg(errp, "KVM does not support userspace APIC"); + return NULL; + } + apic_type = "kvm-apic"; + } else if (xen_enabled()) { + apic_type = "xen-apic"; + } else if (whpx_apic_in_platform()) { + apic_type = "whpx-apic"; + } + + return APIC_COMMON_CLASS(object_class_by_name(apic_type)); +} + +void x86_cpu_apic_create(X86CPU *cpu, Error **errp) +{ + APICCommonState *apic; + APICCommonClass *apic_class = apic_get_class(errp); + + if (!apic_class) { + return; + } + + cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); + object_property_add_child(OBJECT(cpu), "lapic", + OBJECT(cpu->apic_state)); + object_unref(OBJECT(cpu->apic_state)); + + /* TODO: convert to link<> */ + apic = APIC_COMMON(cpu->apic_state); + apic->cpu = cpu; + apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; + + /* + * apic_common_set_id needs to check if the CPU has x2APIC + * feature in case APIC ID >= 255, so we need to set apic->cpu + * before setting APIC ID + */ + qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); +} + +void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) +{ + APICCommonState *apic; + static bool apic_mmio_map_once; + + if (cpu->apic_state == NULL) { + return; + } + qdev_realize(DEVICE(cpu->apic_state), NULL, errp); + + /* Map APIC MMIO area */ + apic = APIC_COMMON(cpu->apic_state); + if (!apic_mmio_map_once) { + memory_region_add_subregion_overlap(get_system_memory(), + apic->apicbase & + MSR_IA32_APICBASE_BASE, + &apic->io_memory, + 0x1000); + apic_mmio_map_once = true; + } +} + +void hmp_info_local_apic(Monitor *mon, const QDict *qdict) +{ + CPUState *cs; + + if (qdict_haskey(qdict, "apic-id")) { + int id = qdict_get_try_int(qdict, "apic-id", 0); + + cs = cpu_by_arch_id(id); + if (cs) { + cpu_synchronize_state(cs); + } + } else { + cs = mon_get_cpu(mon); + } + + + if (!cs) { + monitor_printf(mon, "No CPU available\n"); + return; + } + x86_cpu_dump_local_apic_state(cs, CPU_DUMP_FPU); +} diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 3f9093d285..227ac021f6 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -19,19 +19,12 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "sysemu/kvm.h" -#include "sysemu/xen.h" -#include "sysemu/whpx.h" #include "qapi/error.h" #include "qapi/qapi-visit-run-state.h" #include "qapi/qmp/qdict.h" #include "qapi/qobject-input-visitor.h" #include "qom/qom-qobject.h" #include "qapi/qapi-commands-machine-target.h" -#include "hw/qdev-properties.h" - -#include "exec/address-spaces.h" -#include "hw/i386/apic_internal.h" #include "cpu-internal.h" @@ -273,75 +266,6 @@ void x86_cpu_machine_reset_cb(void *opaque) cpu_reset(CPU(cpu)); } -APICCommonClass *apic_get_class(Error **errp) -{ - const char *apic_type = "apic"; - - /* TODO: in-kernel irqchip for hvf */ - if (kvm_enabled()) { - if (!kvm_irqchip_in_kernel()) { - error_setg(errp, "KVM does not support userspace APIC"); - return NULL; - } - apic_type = "kvm-apic"; - } else if (xen_enabled()) { - apic_type = "xen-apic"; - } else if (whpx_apic_in_platform()) { - apic_type = "whpx-apic"; - } - - return APIC_COMMON_CLASS(object_class_by_name(apic_type)); -} - -void x86_cpu_apic_create(X86CPU *cpu, Error **errp) -{ - APICCommonState *apic; - APICCommonClass *apic_class = apic_get_class(errp); - - if (!apic_class) { - return; - } - - cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); - object_property_add_child(OBJECT(cpu), "lapic", - OBJECT(cpu->apic_state)); - object_unref(OBJECT(cpu->apic_state)); - - /* TODO: convert to link<> */ - apic = APIC_COMMON(cpu->apic_state); - apic->cpu = cpu; - apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; - - /* - * apic_common_set_id needs to check if the CPU has x2APIC - * feature in case APIC ID >= 255, so we need to set apic->cpu - * before setting APIC ID - */ - qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); -} - -void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) -{ - APICCommonState *apic; - static bool apic_mmio_map_once; - - if (cpu->apic_state == NULL) { - return; - } - qdev_realize(DEVICE(cpu->apic_state), NULL, errp); - - /* Map APIC MMIO area */ - apic = APIC_COMMON(cpu->apic_state); - if (!apic_mmio_map_once) { - memory_region_add_subregion_overlap(get_system_memory(), - apic->apicbase & - MSR_IA32_APICBASE_BASE, - &apic->io_memory, - 0x1000); - apic_mmio_map_once = true; - } -} - GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); @@ -385,4 +309,3 @@ void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v, errp); qapi_free_GuestPanicInformation(panic_info); } - diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 3a281dab02..2d766b2637 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -28,8 +28,6 @@ #include "monitor/hmp-target.h" #include "monitor/hmp.h" #include "qapi/qmp/qdict.h" -#include "sysemu/hw_accel.h" -#include "sysemu/kvm.h" #include "qapi/error.h" #include "qapi/qapi-commands-misc-target.h" #include "qapi/qapi-commands-misc.h" @@ -647,26 +645,3 @@ const MonitorDef *target_monitor_defs(void) { return monitor_defs; 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Thu, 21 Mar 2024 08:49:13 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id q14-20020a05600c46ce00b004140a757256sm5997663wmo.31.2024.03.21.08.49.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:13 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 04/21] target/i386: Extract x86_dump_mmu() from hmp_info_tlb() Date: Thu, 21 Mar 2024 16:48:20 +0100 Message-ID: <20240321154838.95771-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org hmp_info_tlb() is specific to tcg/system, move it to target/i386/tcg/sysemu/hmp-cmds.c, along with the functions it depend on (except addr_canonical() which is exposed in "cpu.h"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.h | 7 ++ target/i386/mmu.c | 231 ++++++++++++++++++++++++++++++++++++++++ target/i386/monitor.c | 215 ------------------------------------- target/i386/meson.build | 1 + 4 files changed, 239 insertions(+), 215 deletions(-) create mode 100644 target/i386/mmu.c diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 952174bb6f..055c5b99de 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2342,6 +2342,13 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) return mmu_index_base + mmu_index_32; } +#if !defined(CONFIG_USER_ONLY) +void x86_dump_mmu(Monitor *mon, CPUX86State *env); + +/* Perform linear address sign extension */ +hwaddr addr_canonical(CPUArchState *env, hwaddr addr); +#endif + #define CC_DST (env->cc_dst) #define CC_SRC (env->cc_src) #define CC_SRC2 (env->cc_src2) diff --git a/target/i386/mmu.c b/target/i386/mmu.c new file mode 100644 index 0000000000..da9b2263b4 --- /dev/null +++ b/target/i386/mmu.c @@ -0,0 +1,231 @@ +/* + * QEMU x86 MMU monitor commands + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" +#include "cpu.h" + +hwaddr addr_canonical(CPUArchState *env, hwaddr addr) +{ +#ifdef TARGET_X86_64 + if (env->cr[4] & CR4_LA57_MASK) { + if (addr & (1ULL << 56)) { + addr |= (hwaddr)-(1LL << 57); + } + } else { + if (addr & (1ULL << 47)) { + addr |= (hwaddr)-(1LL << 48); + } + } +#endif + return addr; +} + +static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, + hwaddr pte, hwaddr mask) +{ + addr = addr_canonical(env, addr); + + monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx + " %c%c%c%c%c%c%c%c%c\n", + addr, + pte & mask, + pte & PG_NX_MASK ? 'X' : '-', + pte & PG_GLOBAL_MASK ? 'G' : '-', + pte & PG_PSE_MASK ? 'P' : '-', + pte & PG_DIRTY_MASK ? 'D' : '-', + pte & PG_ACCESSED_MASK ? 'A' : '-', + pte & PG_PCD_MASK ? 'C' : '-', + pte & PG_PWT_MASK ? 'T' : '-', + pte & PG_USER_MASK ? 'U' : '-', + pte & PG_RW_MASK ? 'W' : '-'); +} + +static void tlb_info_32(Monitor *mon, CPUArchState *env) +{ + unsigned int l1, l2; + uint32_t pgd, pde, pte; + + pgd = env->cr[3] & ~0xfff; + for(l1 = 0; l1 < 1024; l1++) { + cpu_physical_memory_read(pgd + l1 * 4, &pde, 4); + pde = le32_to_cpu(pde); + if (pde & PG_PRESENT_MASK) { + if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { + /* 4M pages */ + print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); + } else { + for(l2 = 0; l2 < 1024; l2++) { + cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); + pte = le32_to_cpu(pte); + if (pte & PG_PRESENT_MASK) { + print_pte(mon, env, (l1 << 22) + (l2 << 12), + pte & ~PG_PSE_MASK, + ~0xfff); + } + } + } + } + } +} + +static void tlb_info_pae32(Monitor *mon, CPUArchState *env) +{ + unsigned int l1, l2, l3; + uint64_t pdpe, pde, pte; + uint64_t pdp_addr, pd_addr, pt_addr; + + pdp_addr = env->cr[3] & ~0x1f; + for (l1 = 0; l1 < 4; l1++) { + cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); + pdpe = le64_to_cpu(pdpe); + if (pdpe & PG_PRESENT_MASK) { + pd_addr = pdpe & 0x3fffffffff000ULL; + for (l2 = 0; l2 < 512; l2++) { + cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8); + pde = le64_to_cpu(pde); + if (pde & PG_PRESENT_MASK) { + if (pde & PG_PSE_MASK) { + /* 2M pages with PAE, CR4.PSE is ignored */ + print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, + ~((hwaddr)(1 << 20) - 1)); + } else { + pt_addr = pde & 0x3fffffffff000ULL; + for (l3 = 0; l3 < 512; l3++) { + cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8); + pte = le64_to_cpu(pte); + if (pte & PG_PRESENT_MASK) { + print_pte(mon, env, (l1 << 30) + (l2 << 21) + + (l3 << 12), + pte & ~PG_PSE_MASK, + ~(hwaddr)0xfff); + } + } + } + } + } + } + } +} + +#ifdef TARGET_X86_64 +static void tlb_info_la48(Monitor *mon, CPUArchState *env, + uint64_t l0, uint64_t pml4_addr) +{ + uint64_t l1, l2, l3, l4; + uint64_t pml4e, pdpe, pde, pte; + uint64_t pdp_addr, pd_addr, pt_addr; + + for (l1 = 0; l1 < 512; l1++) { + cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8); + pml4e = le64_to_cpu(pml4e); + if (!(pml4e & PG_PRESENT_MASK)) { + continue; + } + + pdp_addr = pml4e & 0x3fffffffff000ULL; + for (l2 = 0; l2 < 512; l2++) { + cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8); + pdpe = le64_to_cpu(pdpe); + if (!(pdpe & PG_PRESENT_MASK)) { + continue; + } + + if (pdpe & PG_PSE_MASK) { + /* 1G pages, CR4.PSE is ignored */ + print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), + pdpe, 0x3ffffc0000000ULL); + continue; + } + + pd_addr = pdpe & 0x3fffffffff000ULL; + for (l3 = 0; l3 < 512; l3++) { + cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8); + pde = le64_to_cpu(pde); + if (!(pde & PG_PRESENT_MASK)) { + continue; + } + + if (pde & PG_PSE_MASK) { + /* 2M pages, CR4.PSE is ignored */ + print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + + (l3 << 21), pde, 0x3ffffffe00000ULL); + continue; + } + + pt_addr = pde & 0x3fffffffff000ULL; + for (l4 = 0; l4 < 512; l4++) { + cpu_physical_memory_read(pt_addr + + l4 * 8, + &pte, 8); + pte = le64_to_cpu(pte); + if (pte & PG_PRESENT_MASK) { + print_pte(mon, env, (l0 << 48) + (l1 << 39) + + (l2 << 30) + (l3 << 21) + (l4 << 12), + pte & ~PG_PSE_MASK, 0x3fffffffff000ULL); + } + } + } + } + } +} + +static void tlb_info_la57(Monitor *mon, CPUArchState *env) +{ + uint64_t l0; + uint64_t pml5e; + uint64_t pml5_addr; + + pml5_addr = env->cr[3] & 0x3fffffffff000ULL; + for (l0 = 0; l0 < 512; l0++) { + cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8); + pml5e = le64_to_cpu(pml5e); + if (pml5e & PG_PRESENT_MASK) { + tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); + } + } +} +#endif /* TARGET_X86_64 */ + +void x86_dump_mmu(Monitor *mon, CPUX86State *env) +{ + if (!(env->cr[0] & CR0_PG_MASK)) { + monitor_printf(mon, "PG disabled\n"); + return; + } + if (env->cr[4] & CR4_PAE_MASK) { +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + if (env->cr[4] & CR4_LA57_MASK) { + tlb_info_la57(mon, env); + } else { + tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL); + } + } else +#endif + { + tlb_info_pae32(mon, env); + } + } else { + tlb_info_32(mon, env); + } +} + +void hmp_info_tlb(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env; + + env = mon_get_cpu_env(mon); + if (!env) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + x86_dump_mmu(mon, env); +} diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 2d766b2637..fa155ac3c9 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -32,221 +32,6 @@ #include "qapi/qapi-commands-misc-target.h" #include "qapi/qapi-commands-misc.h" -/* Perform linear address sign extension */ -static hwaddr addr_canonical(CPUArchState *env, hwaddr addr) -{ -#ifdef TARGET_X86_64 - if (env->cr[4] & CR4_LA57_MASK) { - if (addr & (1ULL << 56)) { - addr |= (hwaddr)-(1LL << 57); - } - } else { - if (addr & (1ULL << 47)) { - addr |= (hwaddr)-(1LL << 48); - } - } -#endif - return addr; -} - -static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, - hwaddr pte, hwaddr mask) -{ - addr = addr_canonical(env, addr); - - monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx - " %c%c%c%c%c%c%c%c%c\n", - addr, - pte & mask, - pte & PG_NX_MASK ? 'X' : '-', - pte & PG_GLOBAL_MASK ? 'G' : '-', - pte & PG_PSE_MASK ? 'P' : '-', - pte & PG_DIRTY_MASK ? 'D' : '-', - pte & PG_ACCESSED_MASK ? 'A' : '-', - pte & PG_PCD_MASK ? 'C' : '-', - pte & PG_PWT_MASK ? 'T' : '-', - pte & PG_USER_MASK ? 'U' : '-', - pte & PG_RW_MASK ? 'W' : '-'); -} - -static void tlb_info_32(Monitor *mon, CPUArchState *env) -{ - unsigned int l1, l2; - uint32_t pgd, pde, pte; - - pgd = env->cr[3] & ~0xfff; - for(l1 = 0; l1 < 1024; l1++) { - cpu_physical_memory_read(pgd + l1 * 4, &pde, 4); - pde = le32_to_cpu(pde); - if (pde & PG_PRESENT_MASK) { - if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) { - /* 4M pages */ - print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1)); - } else { - for(l2 = 0; l2 < 1024; l2++) { - cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4); - pte = le32_to_cpu(pte); - if (pte & PG_PRESENT_MASK) { - print_pte(mon, env, (l1 << 22) + (l2 << 12), - pte & ~PG_PSE_MASK, - ~0xfff); - } - } - } - } - } -} - -static void tlb_info_pae32(Monitor *mon, CPUArchState *env) -{ - unsigned int l1, l2, l3; - uint64_t pdpe, pde, pte; - uint64_t pdp_addr, pd_addr, pt_addr; - - pdp_addr = env->cr[3] & ~0x1f; - for (l1 = 0; l1 < 4; l1++) { - cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); - if (pdpe & PG_PRESENT_MASK) { - pd_addr = pdpe & 0x3fffffffff000ULL; - for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8); - pde = le64_to_cpu(pde); - if (pde & PG_PRESENT_MASK) { - if (pde & PG_PSE_MASK) { - /* 2M pages with PAE, CR4.PSE is ignored */ - print_pte(mon, env, (l1 << 30) + (l2 << 21), pde, - ~((hwaddr)(1 << 20) - 1)); - } else { - pt_addr = pde & 0x3fffffffff000ULL; - for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8); - pte = le64_to_cpu(pte); - if (pte & PG_PRESENT_MASK) { - print_pte(mon, env, (l1 << 30) + (l2 << 21) - + (l3 << 12), - pte & ~PG_PSE_MASK, - ~(hwaddr)0xfff); - } - } - } - } - } - } - } -} - -#ifdef TARGET_X86_64 -static void tlb_info_la48(Monitor *mon, CPUArchState *env, - uint64_t l0, uint64_t pml4_addr) -{ - uint64_t l1, l2, l3, l4; - uint64_t pml4e, pdpe, pde, pte; - uint64_t pdp_addr, pd_addr, pt_addr; - - for (l1 = 0; l1 < 512; l1++) { - cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8); - pml4e = le64_to_cpu(pml4e); - if (!(pml4e & PG_PRESENT_MASK)) { - continue; - } - - pdp_addr = pml4e & 0x3fffffffff000ULL; - for (l2 = 0; l2 < 512; l2++) { - cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8); - pdpe = le64_to_cpu(pdpe); - if (!(pdpe & PG_PRESENT_MASK)) { - continue; - } - - if (pdpe & PG_PSE_MASK) { - /* 1G pages, CR4.PSE is ignored */ - print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30), - pdpe, 0x3ffffc0000000ULL); - continue; - } - - pd_addr = pdpe & 0x3fffffffff000ULL; - for (l3 = 0; l3 < 512; l3++) { - cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8); - pde = le64_to_cpu(pde); - if (!(pde & PG_PRESENT_MASK)) { - continue; - } - - if (pde & PG_PSE_MASK) { - /* 2M pages, CR4.PSE is ignored */ - print_pte(mon, env, (l0 << 48) + (l1 << 39) + (l2 << 30) + - (l3 << 21), pde, 0x3ffffffe00000ULL); - continue; - } - - pt_addr = pde & 0x3fffffffff000ULL; - for (l4 = 0; l4 < 512; l4++) { - cpu_physical_memory_read(pt_addr - + l4 * 8, - &pte, 8); - pte = le64_to_cpu(pte); - if (pte & PG_PRESENT_MASK) { - print_pte(mon, env, (l0 << 48) + (l1 << 39) + - (l2 << 30) + (l3 << 21) + (l4 << 12), - pte & ~PG_PSE_MASK, 0x3fffffffff000ULL); - } - } - } - } - } -} - -static void tlb_info_la57(Monitor *mon, CPUArchState *env) -{ - uint64_t l0; - uint64_t pml5e; - uint64_t pml5_addr; - - pml5_addr = env->cr[3] & 0x3fffffffff000ULL; - for (l0 = 0; l0 < 512; l0++) { - cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8); - pml5e = le64_to_cpu(pml5e); - if (pml5e & PG_PRESENT_MASK) { - tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL); - } - } -} -#endif /* TARGET_X86_64 */ - -void hmp_info_tlb(Monitor *mon, const QDict *qdict) -{ - CPUArchState *env; - - env = mon_get_cpu_env(mon); - if (!env) { - monitor_printf(mon, "No CPU available\n"); - return; - } - - if (!(env->cr[0] & CR0_PG_MASK)) { - monitor_printf(mon, "PG disabled\n"); - return; - } - if (env->cr[4] & CR4_PAE_MASK) { -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - if (env->cr[4] & CR4_LA57_MASK) { - tlb_info_la57(mon, env); - } else { - tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL); - } - } else -#endif - { - tlb_info_pae32(mon, env); - } - } else { - tlb_info_32(mon, env); - } -} - static void mem_print(Monitor *mon, CPUArchState *env, hwaddr *pstart, int *plast_prot, hwaddr end, int prot) diff --git a/target/i386/meson.build b/target/i386/meson.build index ba8dc68a34..6c6f383e2e 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,6 +18,7 @@ i386_system_ss.add(files( 'arch_memory_mapping.c', 'machine.c', 'monitor.c', + 'mmu.c', 'cpu-apic.c', 'cpu-sysemu.c', )) From patchwork Thu Mar 21 15:48:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA44AC54E58 for ; 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Thu, 21 Mar 2024 08:49:21 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id iv20-20020a05600c549400b004146bce65f4sm5887932wmb.13.2024.03.21.08.49.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 05/21] target/m68k: Replace qemu_printf() by monitor_printf() in monitor Date: Thu, 21 Mar 2024 16:48:21 +0100 Message-ID: <20240321154838.95771-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Markus Armbruster --- target/m68k/cpu.h | 2 +- target/m68k/helper.c | 126 +++++++++++++++++++++--------------------- target/m68k/monitor.c | 4 +- 3 files changed, 67 insertions(+), 65 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 346427e144..4e4307956d 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -620,6 +620,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, } } -void dump_mmu(CPUM68KState *env); +void dump_mmu(Monitor *mon, CPUM68KState *env); #endif diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 1a475f082a..310e26dfa1 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -25,7 +25,7 @@ #include "exec/helper-proto.h" #include "gdbstub/helpers.h" #include "fpu/softfloat.h" -#include "qemu/qemu-print.h" +#include "monitor/monitor.h" #define SIGNBIT (1u << 31) @@ -455,28 +455,30 @@ void m68k_switch_sp(CPUM68KState *env) #if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ -static void print_address_zone(uint32_t logical, uint32_t physical, +static void print_address_zone(Monitor *mon, + uint32_t logical, uint32_t physical, uint32_t size, int attr) { - qemu_printf("%08x - %08x -> %08x - %08x %c ", - logical, logical + size - 1, - physical, physical + size - 1, - attr & 4 ? 'W' : '-'); + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ", + logical, logical + size - 1, + physical, physical + size - 1, + attr & 4 ? 'W' : '-'); size >>= 10; if (size < 1024) { - qemu_printf("(%d KiB)\n", size); + monitor_printf(mon, "(%d KiB)\n", size); } else { size >>= 10; if (size < 1024) { - qemu_printf("(%d MiB)\n", size); + monitor_printf(mon, "(%d MiB)\n", size); } else { size >>= 10; - qemu_printf("(%d GiB)\n", size); + monitor_printf(mon, "(%d GiB)\n", size); } } } -static void dump_address_map(CPUM68KState *env, uint32_t root_pointer) +static void dump_address_map(Monitor *mon, CPUM68KState *env, + uint32_t root_pointer) { int i, j, k; int tic_size, tic_shift; @@ -545,7 +547,7 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer) if (first_logical != 0xffffffff) { size = last_logical + (1 << tic_shift) - first_logical; - print_address_zone(first_logical, + print_address_zone(mon, first_logical, first_physical, size, last_attr); } first_logical = logical; @@ -556,125 +558,125 @@ static void dump_address_map(CPUM68KState *env, uint32_t root_pointer) } if (first_logical != logical || (attr & 4) != (last_attr & 4)) { size = logical + (1 << tic_shift) - first_logical; - print_address_zone(first_logical, first_physical, size, last_attr); + print_address_zone(mon, first_logical, first_physical, size, last_attr); } } #define DUMP_CACHEFLAGS(a) \ switch (a & M68K_DESC_CACHEMODE) { \ case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \ - qemu_printf("T"); \ + monitor_puts(mon, "T"); \ break; \ case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \ - qemu_printf("C"); \ + monitor_puts(mon, "C"); \ break; \ case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ - qemu_printf("S"); \ + monitor_puts(mon, "S"); \ break; \ case M68K_DESC_CM_NCACHE: /* noncachable */ \ - qemu_printf("N"); \ + monitor_puts(mon, "N"); \ break; \ } -static void dump_ttr(uint32_t ttr) +static void dump_ttr(Monitor *mon, uint32_t ttr) { if ((ttr & M68K_TTR_ENABLED) == 0) { - qemu_printf("disabled\n"); + monitor_puts(mon, "disabled\n"); return; } - qemu_printf("Base: 0x%08x Mask: 0x%08x Control: ", - ttr & M68K_TTR_ADDR_BASE, - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ", + ttr & M68K_TTR_ADDR_BASE, + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); switch (ttr & M68K_TTR_SFIELD) { case M68K_TTR_SFIELD_USER: - qemu_printf("U"); + monitor_puts(mon, "U"); break; case M68K_TTR_SFIELD_SUPER: - qemu_printf("S"); + monitor_puts(mon, "S"); break; default: - qemu_printf("*"); + monitor_puts(mon, "*"); break; } DUMP_CACHEFLAGS(ttr); if (ttr & M68K_DESC_WRITEPROT) { - qemu_printf("R"); + monitor_puts(mon, "R"); } else { - qemu_printf("W"); + monitor_puts(mon, "W"); } - qemu_printf(" U: %d\n", (ttr & M68K_DESC_USERATTR) >> + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >> M68K_DESC_USERATTR_SHIFT); } -void dump_mmu(CPUM68KState *env) +void dump_mmu(Monitor *mon, CPUM68KState *env) { if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { - qemu_printf("Translation disabled\n"); + monitor_puts(mon, "Translation disabled\n"); return; } - qemu_printf("Page Size: "); + monitor_puts(mon, "Page Size: "); if (env->mmu.tcr & M68K_TCR_PAGE_8K) { - qemu_printf("8kB\n"); + monitor_puts(mon, "8kB\n"); } else { - qemu_printf("4kB\n"); + monitor_puts(mon, "4kB\n"); } - qemu_printf("MMUSR: "); + monitor_puts(mon, "MMUSR: "); if (env->mmu.mmusr & M68K_MMU_B_040) { - qemu_printf("BUS ERROR\n"); + monitor_puts(mon, "BUS ERROR\n"); } else { - qemu_printf("Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); /* flags found on the page descriptor */ if (env->mmu.mmusr & M68K_MMU_G_040) { - qemu_printf("G"); /* Global */ + monitor_puts(mon, "G"); /* Global */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } if (env->mmu.mmusr & M68K_MMU_S_040) { - qemu_printf("S"); /* Supervisor */ + monitor_puts(mon, "S"); /* Supervisor */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } if (env->mmu.mmusr & M68K_MMU_M_040) { - qemu_printf("M"); /* Modified */ + monitor_puts(mon, "M"); /* Modified */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } if (env->mmu.mmusr & M68K_MMU_WP_040) { - qemu_printf("W"); /* Write protect */ + monitor_puts(mon, "W"); /* Write protect */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } if (env->mmu.mmusr & M68K_MMU_T_040) { - qemu_printf("T"); /* Transparent */ + monitor_puts(mon, "T"); /* Transparent */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } if (env->mmu.mmusr & M68K_MMU_R_040) { - qemu_printf("R"); /* Resident */ + monitor_puts(mon, "R"); /* Resident */ } else { - qemu_printf("."); + monitor_puts(mon, "."); } - qemu_printf(" Cache: "); + monitor_puts(mon, " Cache: "); DUMP_CACHEFLAGS(env->mmu.mmusr); - qemu_printf(" U: %d\n", (env->mmu.mmusr >> 8) & 3); - qemu_printf("\n"); + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3); + monitor_puts(mon, "\n"); } - qemu_printf("ITTR0: "); - dump_ttr(env->mmu.ttr[M68K_ITTR0]); - qemu_printf("ITTR1: "); - dump_ttr(env->mmu.ttr[M68K_ITTR1]); - qemu_printf("DTTR0: "); - dump_ttr(env->mmu.ttr[M68K_DTTR0]); - qemu_printf("DTTR1: "); - dump_ttr(env->mmu.ttr[M68K_DTTR1]); + monitor_puts(mon, "ITTR0: "); + dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]); + monitor_puts(mon, "ITTR1: "); + dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]); + monitor_puts(mon, "DTTR0: "); + dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]); + monitor_puts(mon, "DTTR1: "); + dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]); - qemu_printf("SRP: 0x%08x\n", env->mmu.srp); - dump_address_map(env, env->mmu.srp); + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp); + dump_address_map(mon, env, env->mmu.srp); - qemu_printf("URP: 0x%08x\n", env->mmu.urp); - dump_address_map(env, env->mmu.urp); + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp); + dump_address_map(mon, env, env->mmu.urp); } static int check_TTR(uint32_t ttr, int *prot, target_ulong addr, diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 2bdf6acae0..623c6ab635 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -15,11 +15,11 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) CPUArchState *env1 = mon_get_cpu_env(mon); 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Thu, 21 Mar 2024 08:49:28 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id r14-20020a05600c35ce00b004146aac1d2asm5952403wmq.27.2024.03.21.08.49.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 06/21] target/m68k: Have dump_ttr() take a @description argument Date: Thu, 21 Mar 2024 16:48:22 +0100 Message-ID: <20240321154838.95771-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Slightly simplify dump_mmu() by passing the description as argument to dump_ttr(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/m68k/helper.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 310e26dfa1..cf9d83e47e 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -578,8 +578,9 @@ static void dump_address_map(Monitor *mon, CPUM68KState *env, break; \ } -static void dump_ttr(Monitor *mon, uint32_t ttr) +static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr) { + monitor_printf(mon, "%s: ", desc); if ((ttr & M68K_TTR_ENABLED) == 0) { monitor_puts(mon, "disabled\n"); return; @@ -663,14 +664,10 @@ void dump_mmu(Monitor *mon, CPUM68KState *env) monitor_puts(mon, "\n"); } - monitor_puts(mon, "ITTR0: "); - dump_ttr(mon, env->mmu.ttr[M68K_ITTR0]); - monitor_puts(mon, "ITTR1: "); - dump_ttr(mon, env->mmu.ttr[M68K_ITTR1]); - monitor_puts(mon, "DTTR0: "); - dump_ttr(mon, env->mmu.ttr[M68K_DTTR0]); - monitor_puts(mon, "DTTR1: "); - dump_ttr(mon, env->mmu.ttr[M68K_DTTR1]); + dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]); + dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]); + dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]); + dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]); monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp); dump_address_map(mon, env, env->mmu.srp); From patchwork Thu Mar 21 15:48:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7CBE8C54E58 for ; Thu, 21 Mar 2024 15:50:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKfp-0005jT-44; Thu, 21 Mar 2024 11:49:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKfn-0005WT-5f for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:49:43 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKfi-0001QX-QF for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:49:42 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-41466e01965so7937905e9.3 for ; Thu, 21 Mar 2024 08:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036176; x=1711640976; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sC//v5zJC26L5oJBPuaKUrq0r2OoFOjOzcD/UQcspDw=; b=rLh1W1Od7zUegQVnLB1jrDqxPHf1d6D5npeVhFkEp4oLnUq7aY65Y9e34KL6Vba1NU ULgytPFa7qlfesSywN4X3umHx9JBRaYygYG9mB4zGnwA0pAfiFDcTqz26gl2o4Hphngi Kcu8+nTlKw7lvK3oKfS58nyNUzRExYdmr9UX2q0LmAC2xnmGtK15YqQZ2owCXHqu9tiL nbehf3VitkANQBlMH9dJHVkWYHHI0aH0iBIizLWJllL7XzMXDC7jaCgM4Lf65aQrN4Rm dNPFJIU/4A/+wRIrkvEkGmYJmD6WKperO/3qnJs4TU/vu64ZZNVqQaztmfzuVKvFQpe/ bqkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036176; x=1711640976; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sC//v5zJC26L5oJBPuaKUrq0r2OoFOjOzcD/UQcspDw=; b=Jrx9GS0qbfbN32Vb564s4HnpAHwtnSNLXFxQ/bxo61mUgGlskZ2bb8bF3JVCxHxKGO 5bqDkNy5p96jQp2NKbUpRWcTpT2X1ov3/xOgFa42+WV1KcybWfNDvhL1a0rJ1pG07nJh RAMQqOYxwVZfQSu3hseGWw5l0KL/6QH7ctbmbmYHUekzReV9xialY94GbFpV2JvdH7FB AYe/p/8RgZubbpKAzLmvrwRLCRg6zQsVNJoB9lHSf47v0HZAf6YEhAdRJE2ky76KXNX2 PsTSBXEKCmSnjm2fBxLgwP8ppae+c8Nr3cYMq1B/TrNL2R4wAg8cmclmlcPdC8z17qzT nvhQ== X-Gm-Message-State: AOJu0YyoJWU7CbA32iwvvA+YhRVnsTXtiyeMdsL+pkIpbSkzLJIEMtFq aw2C/Q1ie41roGM7hjK6PzY7dKN6ivbh/txPUNUQPs8ujBE0o6O9jwY1MmPcY4gE4GqMELqsVXU V+Eo= X-Google-Smtp-Source: AGHT+IFw0k53MJIEDoEtj/96Ez8pi/LpbXoIDbS/169t1A8FKaf2xVKWSjv2p94mK18bkZO+A1abiA== X-Received: by 2002:a05:600c:3b19:b0:414:f50:3587 with SMTP id m25-20020a05600c3b1900b004140f503587mr9936764wms.8.1711036176449; Thu, 21 Mar 2024 08:49:36 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id e13-20020a05600c4e4d00b004146750314csm6021722wmq.3.2024.03.21.08.49.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 07/21] target/m68k: Move MMU monitor commands from helper.c to monitor.c Date: Thu, 21 Mar 2024 16:48:23 +0100 Message-ID: <20240321154838.95771-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Keep all HMP commands in monitor.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/m68k/cpu.h | 3 +- target/m68k/helper.c | 222 ----------------------------------------- target/m68k/monitor.c | 223 +++++++++++++++++++++++++++++++++++++++++- 3 files changed, 223 insertions(+), 225 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 4e4307956d..0c2a9fa717 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -589,6 +589,7 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void m68k_dump_mmu(Monitor *mon, CPUM68KState *env); #endif #include "exec/cpu-all.h" @@ -620,6 +621,4 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, } } -void dump_mmu(Monitor *mon, CPUM68KState *env); - #endif diff --git a/target/m68k/helper.c b/target/m68k/helper.c index cf9d83e47e..bd833aed5d 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "gdbstub/helpers.h" #include "fpu/softfloat.h" -#include "monitor/monitor.h" #define SIGNBIT (1u << 31) @@ -455,227 +454,6 @@ void m68k_switch_sp(CPUM68KState *env) #if !defined(CONFIG_USER_ONLY) /* MMU: 68040 only */ -static void print_address_zone(Monitor *mon, - uint32_t logical, uint32_t physical, - uint32_t size, int attr) -{ - monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ", - logical, logical + size - 1, - physical, physical + size - 1, - attr & 4 ? 'W' : '-'); - size >>= 10; - if (size < 1024) { - monitor_printf(mon, "(%d KiB)\n", size); - } else { - size >>= 10; - if (size < 1024) { - monitor_printf(mon, "(%d MiB)\n", size); - } else { - size >>= 10; - monitor_printf(mon, "(%d GiB)\n", size); - } - } -} - -static void dump_address_map(Monitor *mon, CPUM68KState *env, - uint32_t root_pointer) -{ - int i, j, k; - int tic_size, tic_shift; - uint32_t tib_mask; - uint32_t tia, tib, tic; - uint32_t logical = 0xffffffff, physical = 0xffffffff; - uint32_t first_logical = 0xffffffff, first_physical = 0xffffffff; - uint32_t last_logical, last_physical; - int32_t size; - int last_attr = -1, attr = -1; - CPUState *cs = env_cpu(env); - MemTxResult txres; - - if (env->mmu.tcr & M68K_TCR_PAGE_8K) { - /* 8k page */ - tic_size = 32; - tic_shift = 13; - tib_mask = M68K_8K_PAGE_MASK; - } else { - /* 4k page */ - tic_size = 64; - tic_shift = 12; - tib_mask = M68K_4K_PAGE_MASK; - } - for (i = 0; i < M68K_ROOT_POINTER_ENTRIES; i++) { - tia = address_space_ldl(cs->as, M68K_POINTER_BASE(root_pointer) + i * 4, - MEMTXATTRS_UNSPECIFIED, &txres); - if (txres != MEMTX_OK || !M68K_UDT_VALID(tia)) { - continue; - } - for (j = 0; j < M68K_ROOT_POINTER_ENTRIES; j++) { - tib = address_space_ldl(cs->as, M68K_POINTER_BASE(tia) + j * 4, - MEMTXATTRS_UNSPECIFIED, &txres); - if (txres != MEMTX_OK || !M68K_UDT_VALID(tib)) { - continue; - } - for (k = 0; k < tic_size; k++) { - tic = address_space_ldl(cs->as, (tib & tib_mask) + k * 4, - MEMTXATTRS_UNSPECIFIED, &txres); - if (txres != MEMTX_OK || !M68K_PDT_VALID(tic)) { - continue; - } - if (M68K_PDT_INDIRECT(tic)) { - tic = address_space_ldl(cs->as, M68K_INDIRECT_POINTER(tic), - MEMTXATTRS_UNSPECIFIED, &txres); - if (txres != MEMTX_OK) { - continue; - } - } - - last_logical = logical; - logical = (i << M68K_TTS_ROOT_SHIFT) | - (j << M68K_TTS_POINTER_SHIFT) | - (k << tic_shift); - - last_physical = physical; - physical = tic & ~((1 << tic_shift) - 1); - - last_attr = attr; - attr = tic & ((1 << tic_shift) - 1); - - if ((logical != (last_logical + (1 << tic_shift))) || - (physical != (last_physical + (1 << tic_shift))) || - (attr & 4) != (last_attr & 4)) { - - if (first_logical != 0xffffffff) { - size = last_logical + (1 << tic_shift) - - first_logical; - print_address_zone(mon, first_logical, - first_physical, size, last_attr); - } - first_logical = logical; - first_physical = physical; - } - } - } - } - if (first_logical != logical || (attr & 4) != (last_attr & 4)) { - size = logical + (1 << tic_shift) - first_logical; - print_address_zone(mon, first_logical, first_physical, size, last_attr); - } -} - -#define DUMP_CACHEFLAGS(a) \ - switch (a & M68K_DESC_CACHEMODE) { \ - case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \ - monitor_puts(mon, "T"); \ - break; \ - case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \ - monitor_puts(mon, "C"); \ - break; \ - case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ - monitor_puts(mon, "S"); \ - break; \ - case M68K_DESC_CM_NCACHE: /* noncachable */ \ - monitor_puts(mon, "N"); \ - break; \ - } - -static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr) -{ - monitor_printf(mon, "%s: ", desc); - if ((ttr & M68K_TTR_ENABLED) == 0) { - monitor_puts(mon, "disabled\n"); - return; - } - monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ", - ttr & M68K_TTR_ADDR_BASE, - (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); - switch (ttr & M68K_TTR_SFIELD) { - case M68K_TTR_SFIELD_USER: - monitor_puts(mon, "U"); - break; - case M68K_TTR_SFIELD_SUPER: - monitor_puts(mon, "S"); - break; - default: - monitor_puts(mon, "*"); - break; - } - DUMP_CACHEFLAGS(ttr); - if (ttr & M68K_DESC_WRITEPROT) { - monitor_puts(mon, "R"); - } else { - monitor_puts(mon, "W"); - } - monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >> - M68K_DESC_USERATTR_SHIFT); -} - -void dump_mmu(Monitor *mon, CPUM68KState *env) -{ - if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { - monitor_puts(mon, "Translation disabled\n"); - return; - } - monitor_puts(mon, "Page Size: "); - if (env->mmu.tcr & M68K_TCR_PAGE_8K) { - monitor_puts(mon, "8kB\n"); - } else { - monitor_puts(mon, "4kB\n"); - } - - monitor_puts(mon, "MMUSR: "); - if (env->mmu.mmusr & M68K_MMU_B_040) { - monitor_puts(mon, "BUS ERROR\n"); - } else { - monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); - /* flags found on the page descriptor */ - if (env->mmu.mmusr & M68K_MMU_G_040) { - monitor_puts(mon, "G"); /* Global */ - } else { - monitor_puts(mon, "."); - } - if (env->mmu.mmusr & M68K_MMU_S_040) { - monitor_puts(mon, "S"); /* Supervisor */ - } else { - monitor_puts(mon, "."); - } - if (env->mmu.mmusr & M68K_MMU_M_040) { - monitor_puts(mon, "M"); /* Modified */ - } else { - monitor_puts(mon, "."); - } - if (env->mmu.mmusr & M68K_MMU_WP_040) { - monitor_puts(mon, "W"); /* Write protect */ - } else { - monitor_puts(mon, "."); - } - if (env->mmu.mmusr & M68K_MMU_T_040) { - monitor_puts(mon, "T"); /* Transparent */ - } else { - monitor_puts(mon, "."); - } - if (env->mmu.mmusr & M68K_MMU_R_040) { - monitor_puts(mon, "R"); /* Resident */ - } else { - monitor_puts(mon, "."); - } - monitor_puts(mon, " Cache: "); - DUMP_CACHEFLAGS(env->mmu.mmusr); - monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3); - monitor_puts(mon, "\n"); - } - - dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]); - dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]); - dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]); - dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]); - - monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp); - dump_address_map(mon, env, env->mmu.srp); - - monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp); - dump_address_map(mon, env, env->mmu.urp); -} - static int check_TTR(uint32_t ttr, int *prot, target_ulong addr, int access_type) { diff --git a/target/m68k/monitor.c b/target/m68k/monitor.c index 623c6ab635..c225846540 100644 --- a/target/m68k/monitor.c +++ b/target/m68k/monitor.c @@ -10,6 +10,227 @@ #include "monitor/hmp-target.h" #include "monitor/monitor.h" +static void print_address_zone(Monitor *mon, + uint32_t logical, uint32_t physical, + uint32_t size, int attr) +{ + monitor_printf(mon, "%08x - %08x -> %08x - %08x %c ", + logical, logical + size - 1, + physical, physical + size - 1, + attr & 4 ? 'W' : '-'); + size >>= 10; + if (size < 1024) { + monitor_printf(mon, "(%d KiB)\n", size); + } else { + size >>= 10; + if (size < 1024) { + monitor_printf(mon, "(%d MiB)\n", size); + } else { + size >>= 10; + monitor_printf(mon, "(%d GiB)\n", size); + } + } +} + +static void dump_address_map(Monitor *mon, CPUM68KState *env, + uint32_t root_pointer) +{ + int i, j, k; + int tic_size, tic_shift; + uint32_t tib_mask; + uint32_t tia, tib, tic; + uint32_t logical = 0xffffffff, physical = 0xffffffff; + uint32_t first_logical = 0xffffffff, first_physical = 0xffffffff; + uint32_t last_logical, last_physical; + int32_t size; + int last_attr = -1, attr = -1; + CPUState *cs = env_cpu(env); + MemTxResult txres; + + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + /* 8k page */ + tic_size = 32; + tic_shift = 13; + tib_mask = M68K_8K_PAGE_MASK; + } else { + /* 4k page */ + tic_size = 64; + tic_shift = 12; + tib_mask = M68K_4K_PAGE_MASK; + } + for (i = 0; i < M68K_ROOT_POINTER_ENTRIES; i++) { + tia = address_space_ldl(cs->as, M68K_POINTER_BASE(root_pointer) + i * 4, + MEMTXATTRS_UNSPECIFIED, &txres); + if (txres != MEMTX_OK || !M68K_UDT_VALID(tia)) { + continue; + } + for (j = 0; j < M68K_ROOT_POINTER_ENTRIES; j++) { + tib = address_space_ldl(cs->as, M68K_POINTER_BASE(tia) + j * 4, + MEMTXATTRS_UNSPECIFIED, &txres); + if (txres != MEMTX_OK || !M68K_UDT_VALID(tib)) { + continue; + } + for (k = 0; k < tic_size; k++) { + tic = address_space_ldl(cs->as, (tib & tib_mask) + k * 4, + MEMTXATTRS_UNSPECIFIED, &txres); + if (txres != MEMTX_OK || !M68K_PDT_VALID(tic)) { + continue; + } + if (M68K_PDT_INDIRECT(tic)) { + tic = address_space_ldl(cs->as, M68K_INDIRECT_POINTER(tic), + MEMTXATTRS_UNSPECIFIED, &txres); + if (txres != MEMTX_OK) { + continue; + } + } + + last_logical = logical; + logical = (i << M68K_TTS_ROOT_SHIFT) | + (j << M68K_TTS_POINTER_SHIFT) | + (k << tic_shift); + + last_physical = physical; + physical = tic & ~((1 << tic_shift) - 1); + + last_attr = attr; + attr = tic & ((1 << tic_shift) - 1); + + if ((logical != (last_logical + (1 << tic_shift))) || + (physical != (last_physical + (1 << tic_shift))) || + (attr & 4) != (last_attr & 4)) { + + if (first_logical != 0xffffffff) { + size = last_logical + (1 << tic_shift) - + first_logical; + print_address_zone(mon, first_logical, + first_physical, size, last_attr); + } + first_logical = logical; + first_physical = physical; + } + } + } + } + if (first_logical != logical || (attr & 4) != (last_attr & 4)) { + size = logical + (1 << tic_shift) - first_logical; + print_address_zone(mon, first_logical, first_physical, size, last_attr); + } +} + +#define DUMP_CACHEFLAGS(a) \ + switch (a & M68K_DESC_CACHEMODE) { \ + case M68K_DESC_CM_WRTHRU: /* cacheable, write-through */ \ + monitor_puts(mon, "T"); \ + break; \ + case M68K_DESC_CM_COPYBK: /* cacheable, copyback */ \ + monitor_puts(mon, "C"); \ + break; \ + case M68K_DESC_CM_SERIAL: /* noncachable, serialized */ \ + monitor_puts(mon, "S"); \ + break; \ + case M68K_DESC_CM_NCACHE: /* noncachable */ \ + monitor_puts(mon, "N"); \ + break; \ + } + +static void dump_ttr(Monitor *mon, const char *desc, uint32_t ttr) +{ + monitor_printf(mon, "%s: ", desc); + if ((ttr & M68K_TTR_ENABLED) == 0) { + monitor_puts(mon, "disabled\n"); + return; + } + monitor_printf(mon, "Base: 0x%08x Mask: 0x%08x Control: ", + ttr & M68K_TTR_ADDR_BASE, + (ttr & M68K_TTR_ADDR_MASK) << M68K_TTR_ADDR_MASK_SHIFT); + switch (ttr & M68K_TTR_SFIELD) { + case M68K_TTR_SFIELD_USER: + monitor_puts(mon, "U"); + break; + case M68K_TTR_SFIELD_SUPER: + monitor_puts(mon, "S"); + break; + default: + monitor_puts(mon, "*"); + break; + } + DUMP_CACHEFLAGS(ttr); + if (ttr & M68K_DESC_WRITEPROT) { + monitor_puts(mon, "R"); + } else { + monitor_puts(mon, "W"); + } + monitor_printf(mon, " U: %d\n", (ttr & M68K_DESC_USERATTR) >> + M68K_DESC_USERATTR_SHIFT); +} + +void m68k_dump_mmu(Monitor *mon, CPUM68KState *env) +{ + if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) { + monitor_puts(mon, "Translation disabled\n"); + return; + } + monitor_puts(mon, "Page Size: "); + if (env->mmu.tcr & M68K_TCR_PAGE_8K) { + monitor_puts(mon, "8kB\n"); + } else { + monitor_puts(mon, "4kB\n"); + } + + monitor_puts(mon, "MMUSR: "); + if (env->mmu.mmusr & M68K_MMU_B_040) { + monitor_puts(mon, "BUS ERROR\n"); + } else { + monitor_printf(mon, "Phy=%08x Flags: ", env->mmu.mmusr & 0xfffff000); + /* flags found on the page descriptor */ + if (env->mmu.mmusr & M68K_MMU_G_040) { + monitor_puts(mon, "G"); /* Global */ + } else { + monitor_puts(mon, "."); + } + if (env->mmu.mmusr & M68K_MMU_S_040) { + monitor_puts(mon, "S"); /* Supervisor */ + } else { + monitor_puts(mon, "."); + } + if (env->mmu.mmusr & M68K_MMU_M_040) { + monitor_puts(mon, "M"); /* Modified */ + } else { + monitor_puts(mon, "."); + } + if (env->mmu.mmusr & M68K_MMU_WP_040) { + monitor_puts(mon, "W"); /* Write protect */ + } else { + monitor_puts(mon, "."); + } + if (env->mmu.mmusr & M68K_MMU_T_040) { + monitor_puts(mon, "T"); /* Transparent */ + } else { + monitor_puts(mon, "."); + } + if (env->mmu.mmusr & M68K_MMU_R_040) { + monitor_puts(mon, "R"); /* Resident */ + } else { + monitor_puts(mon, "."); + } + monitor_puts(mon, " Cache: "); + DUMP_CACHEFLAGS(env->mmu.mmusr); + monitor_printf(mon, " U: %d\n", (env->mmu.mmusr >> 8) & 3); + monitor_puts(mon, "\n"); + } + + dump_ttr(mon, "ITTR0", env->mmu.ttr[M68K_ITTR0]); + dump_ttr(mon, "ITTR1", env->mmu.ttr[M68K_ITTR1]); + dump_ttr(mon, "DTTR0", env->mmu.ttr[M68K_DTTR0]); + dump_ttr(mon, "DTTR1", env->mmu.ttr[M68K_DTTR1]); + + monitor_printf(mon, "SRP: 0x%08x\n", env->mmu.srp); + dump_address_map(mon, env, env->mmu.srp); + + monitor_printf(mon, "URP: 0x%08x\n", env->mmu.urp); + dump_address_map(mon, env, env->mmu.urp); +} + void hmp_info_tlb(Monitor *mon, const QDict *qdict) { CPUArchState *env1 = mon_get_cpu_env(mon); @@ -19,7 +240,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) return; } - dump_mmu(mon, env1); + m68k_dump_mmu(mon, env1); } static const MonitorDef monitor_defs[] = { From patchwork Thu Mar 21 15:48:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599009 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A135BC54E58 for ; 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Thu, 21 Mar 2024 08:49:44 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id o9-20020adfe809000000b0033ec6ebf878sm17419893wrm.93.2024.03.21.08.49.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 08/21] target/microblaze: Prefix MMU API with 'mb_' Date: Thu, 21 Mar 2024 16:48:24 +0100 Message-ID: <20240321154838.95771-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org MicroBlaze MMU API is exposed in "mmu.h". In order to avoid name clashing with other targets, prefix the API with 'mb_'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias --- target/microblaze/mmu.h | 10 +++++----- target/microblaze/cpu.c | 2 +- target/microblaze/helper.c | 4 ++-- target/microblaze/mmu.c | 14 +++++++------- target/microblaze/op_helper.c | 4 ++-- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 1068bd2d52..5b51e0a9c6 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -85,10 +85,10 @@ typedef struct { } err; } MicroBlazeMMULookup; -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, MMUAccessType rw, int mmu_idx); -uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); -void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); -void mmu_init(MicroBlazeMMU *mmu); +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, + target_ulong vaddr, MMUAccessType rw, int mmu_idx); +uint32_t mb_mmu_read(CPUMBState *env, bool ea, uint32_t rn); +void mb_mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v); +void mb_mmu_init(MicroBlazeMMU *mmu); #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 96c2b71f7f..59bfb5c45d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -205,7 +205,7 @@ static void mb_cpu_reset_hold(Object *obj) mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); #else mb_cpu_write_msr(env, 0); - mmu_init(&env->mmu); + mb_mmu_init(&env->mmu); #endif } diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index d25c9eb4d3..961687bae7 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -57,7 +57,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, return true; } - hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); + hit = mb_mmu_translate(cpu, &lu, address, access_type, mmu_idx); if (likely(hit)) { uint32_t vaddr = address & TARGET_PAGE_MASK; uint32_t paddr = lu.paddr + vaddr - lu.vaddr; @@ -238,7 +238,7 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); if (mmu_idx != MMU_NOMMU_IDX) { - hit = mmu_translate(cpu, &lu, addr, 0, 0); + hit = mb_mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { vaddr = addr & TARGET_PAGE_MASK; paddr = lu.paddr + vaddr - lu.vaddr; diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 234006634e..5fb8ee8418 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -74,8 +74,8 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid) } /* rw - 0 = read, 1 = write, 2 = fetch. */ -unsigned int mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, - target_ulong vaddr, MMUAccessType rw, int mmu_idx) +unsigned int mb_mmu_translate(MicroBlazeCPU *cpu, MicroBlazeMMULookup *lu, + target_ulong vaddr, MMUAccessType rw, int mmu_idx) { MicroBlazeMMU *mmu = &cpu->env.mmu; unsigned int i, hit = 0; @@ -175,7 +175,7 @@ done: } /* Writes/reads to the MMU's special regs end up here. */ -uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) +uint32_t mb_mmu_read(CPUMBState *env, bool ext, uint32_t rn) { MicroBlazeCPU *cpu = env_archcpu(env); unsigned int i; @@ -228,7 +228,7 @@ uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn) return r; } -void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) +void mb_mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) { MicroBlazeCPU *cpu = env_archcpu(env); uint64_t tmp64; @@ -304,8 +304,8 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) return; } - hit = mmu_translate(cpu, &lu, v & TLB_EPN_MASK, - 0, cpu_mmu_index(env_cpu(env), false)); + hit = mb_mmu_translate(cpu, &lu, v & TLB_EPN_MASK, + 0, cpu_mmu_index(env_cpu(env), false)); if (hit) { env->mmu.regs[MMU_R_TLBX] = lu.idx; } else { @@ -319,7 +319,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v) } } -void mmu_init(MicroBlazeMMU *mmu) +void mb_mmu_init(MicroBlazeMMU *mmu) { int i; for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f6378030b7..58475a3af5 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -386,12 +386,12 @@ void helper_stackprot(CPUMBState *env, target_ulong addr) /* Writes/reads to the MMU's special regs end up here. */ uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn) { - return mmu_read(env, ext, rn); + return mb_mmu_read(env, ext, rn); } void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v) { - mmu_write(env, ext, rn, v); + mb_mmu_write(env, ext, rn, v); } void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, From patchwork Thu Mar 21 15:48:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599011 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FA0FC54E68 for ; Thu, 21 Mar 2024 15:50:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKg3-0006V3-Bq; Thu, 21 Mar 2024 11:49:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKg1-0006Oq-DS for qemu-devel@nongnu.org; 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Thu, 21 Mar 2024 08:49:51 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id g8-20020a05600c4ec800b0041408451874sm5958377wmq.17.2024.03.21.08.49.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo Subject: [PATCH-for-9.1 09/21] target/mips: Prefix MMU API with 'mips_' Date: Thu, 21 Mar 2024 16:48:25 +0100 Message-ID: <20240321154838.95771-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org MIPS MMU API declared in tcg-internal.h has public linkage. In order to avoid name clashing with other targets, prefix the API with 'mips_'. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/tcg-internal.h | 2 +- target/mips/cpu.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index aef032c48d..2dc9d9100f 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -43,7 +43,7 @@ void do_raise_exception(CPUMIPSState *env, void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mmu_init(CPUMIPSState *env, const mips_def_t *def); +void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def); void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 8d8f690a53..8acf691b0b 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -485,7 +485,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) env->exception_base = (int32_t)0xBFC00000; #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - mmu_init(env, env->cpu_model); + mips_mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); mvp_init(env); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 119eae771e..0167b1162f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -464,7 +464,7 @@ static void r4k_mmu_init(CPUMIPSState *env, const mips_def_t *def) env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; } -void mmu_init(CPUMIPSState *env, const mips_def_t *def) +void mips_mmu_init(CPUMIPSState *env, const mips_def_t *def) { env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); From patchwork Thu Mar 21 15:48:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1521FC54E58 for ; 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Thu, 21 Mar 2024 08:49:59 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id q18-20020adff792000000b0033ec9b26b7asm17495211wrp.25.2024.03.21.08.49.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:49:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 10/21] target/nios2: Prefix MMU API with 'nios2_' Date: Thu, 21 Mar 2024 16:48:26 +0100 Message-ID: <20240321154838.95771-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Nios2 MMU API is exposed in "mmu.h". In order to avoid name clashing with other targets, prefix the API with 'nios2_'. Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/mmu.h | 11 +++++------ target/nios2/cpu.c | 2 +- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 7 +++---- 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index 5b085900fb..5b16a5facf 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -42,11 +42,10 @@ typedef struct Nios2MMULookup { int prot; } Nios2MMULookup; -void mmu_flip_um(CPUNios2State *env, unsigned int um); -unsigned int mmu_translate(CPUNios2State *env, - Nios2MMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx); -void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v); -void mmu_init(CPUNios2State *env); +void nios2_mmu_flip_um(CPUNios2State *env, unsigned int um); +unsigned int nios2_mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, + target_ulong vaddr, int rw, int mmu_idx); +void nios2_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v); +void nios2_mmu_init(CPUNios2State *env); #endif /* NIOS2_MMU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 679aff5730..d2a9a0d4f1 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -113,7 +113,7 @@ static void nios2_cpu_initfn(Object *obj) #if !defined(CONFIG_USER_ONLY) Nios2CPU *cpu = NIOS2_CPU(obj); - mmu_init(&cpu->env); + nios2_mmu_init(&cpu->env); #endif } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index ac57121afc..2b6bdfbc55 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -268,7 +268,7 @@ hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) unsigned int hit; if (cpu->mmu_present && (addr < 0xC0000000)) { - hit = mmu_translate(env, &lu, addr, 0, 0); + hit = nios2_mmu_translate(env, &lu, addr, 0, 0); if (hit) { vaddr = addr & TARGET_PAGE_MASK; paddr = lu.paddr + vaddr - lu.vaddr; @@ -335,7 +335,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } /* Virtual page. */ - hit = mmu_translate(env, &lu, address, access_type, mmu_idx); + hit = nios2_mmu_translate(env, &lu, address, access_type, mmu_idx); if (hit) { vaddr = address & TARGET_PAGE_MASK; paddr = lu.paddr + vaddr - lu.vaddr; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index d9b690b78e..272bd9fc6a 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -28,9 +28,8 @@ /* rw - 0 = read, 1 = write, 2 = fetch. */ -unsigned int mmu_translate(CPUNios2State *env, - Nios2MMULookup *lu, - target_ulong vaddr, int rw, int mmu_idx) +unsigned int nios2_mmu_translate(CPUNios2State *env, Nios2MMULookup *lu, + target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu = env_archcpu(env); int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); @@ -180,7 +179,7 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) env->mmu.pteaddr_wr = v; } -void mmu_init(CPUNios2State *env) +void nios2_mmu_init(CPUNios2State *env) { Nios2CPU *cpu = env_archcpu(env); Nios2MMU *mmu = &env->mmu; From patchwork Thu Mar 21 15:48:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EA3F7C54E58 for ; Thu, 21 Mar 2024 15:52:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKgZ-0007Qd-9V; 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Thu, 21 Mar 2024 08:50:07 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id n18-20020a05600c501200b004146bdce3fesm5885327wmr.4.2024.03.21.08.50.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 11/21] target/nios2: Move monitor commands to monitor.c Date: Thu, 21 Mar 2024 16:48:27 +0100 Message-ID: <20240321154838.95771-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Move 'info tlb' monitor commands to monitor.c, rename dump_mmu() as nios2_info_mmu(). Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu.h | 2 +- target/nios2/mmu.c | 27 --------------------------- target/nios2/monitor.c | 28 +++++++++++++++++++++++++++- 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 4164a3432e..27e835cf40 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -250,7 +250,7 @@ static inline void nios2_update_crs(CPUNios2State *env) void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); -void dump_mmu(CPUNios2State *env); +void nios2_info_mmu(Monitor *mon, CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); G_NORETURN void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 272bd9fc6a..278eba1b0a 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -19,7 +19,6 @@ */ #include "qemu/osdep.h" -#include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" #include "mmu.h" @@ -187,29 +186,3 @@ void nios2_mmu_init(CPUNios2State *env) mmu->tlb_entry_mask = (cpu->tlb_num_entries / cpu->tlb_num_ways) - 1; mmu->tlb = g_new0(Nios2TLBEntry, cpu->tlb_num_entries); } - -void dump_mmu(CPUNios2State *env) -{ - Nios2CPU *cpu = env_archcpu(env); - int i; - - qemu_printf("MMU: ways %d, entries %d, pid bits %d\n", - cpu->tlb_num_ways, cpu->tlb_num_entries, - cpu->pid_num_bits); - - for (i = 0; i < cpu->tlb_num_entries; i++) { - Nios2TLBEntry *entry = &env->mmu.tlb[i]; - qemu_printf("TLB[%d] = %08X %08X %c VPN %05X " - "PID %02X %c PFN %05X %c%c%c%c\n", - i, entry->tag, entry->data, - (entry->tag & (1 << 10)) ? 'V' : '-', - entry->tag >> 12, - entry->tag & ((1 << cpu->pid_num_bits) - 1), - (entry->tag & (1 << 11)) ? 'G' : '-', - FIELD_EX32(entry->data, CR_TLBACC, PFN), - (entry->data & CR_TLBACC_C) ? 'C' : '-', - (entry->data & CR_TLBACC_R) ? 'R' : '-', - (entry->data & CR_TLBACC_W) ? 'W' : '-', - (entry->data & CR_TLBACC_X) ? 'X' : '-'); - } -} diff --git a/target/nios2/monitor.c b/target/nios2/monitor.c index 0152dec3fa..c6043769e4 100644 --- a/target/nios2/monitor.c +++ b/target/nios2/monitor.c @@ -22,14 +22,40 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" +#include "qemu/qemu-print.h" #include "cpu.h" #include "monitor/monitor.h" #include "monitor/hmp-target.h" #include "monitor/hmp.h" +void nios2_info_mmu(Monitor *mon, CPUNios2State *env) +{ + Nios2CPU *cpu = env_archcpu(env); + + qemu_printf("MMU: ways %d, entries %d, pid bits %d\n", + cpu->tlb_num_ways, cpu->tlb_num_entries, + cpu->pid_num_bits); + + for (int i = 0; i < cpu->tlb_num_entries; i++) { + Nios2TLBEntry *entry = &env->mmu.tlb[i]; + qemu_printf("TLB[%d] = %08X %08X %c VPN %05X " + "PID %02X %c PFN %05X %c%c%c%c\n", + i, entry->tag, entry->data, + (entry->tag & (1 << 10)) ? 'V' : '-', + entry->tag >> 12, + entry->tag & ((1 << cpu->pid_num_bits) - 1), + (entry->tag & (1 << 11)) ? 'G' : '-', + FIELD_EX32(entry->data, CR_TLBACC, PFN), + (entry->data & CR_TLBACC_C) ? 'C' : '-', + (entry->data & CR_TLBACC_R) ? 'R' : '-', + (entry->data & CR_TLBACC_W) ? 'W' : '-', + (entry->data & CR_TLBACC_X) ? 'X' : '-'); + } +} + void hmp_info_tlb(Monitor *mon, const QDict *qdict) { CPUArchState *env1 = mon_get_cpu_env(mon); - dump_mmu(env1); + nios2_info_mmu(mon, env1); } From patchwork Thu Mar 21 15:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5B37CC54E58 for ; Thu, 21 Mar 2024 15:53:21 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKgZ-0007Vl-WB; Thu, 21 Mar 2024 11:50:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKgT-0007D7-Pr for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:27 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKgM-0001nA-79 for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:20 -0400 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-414633f7a52so11074275e9.0 for ; Thu, 21 Mar 2024 08:50:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036215; x=1711641015; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4LWS7xvFoegnF0mSZFeKjpH3HSq3m0fIT12twQQtV6g=; b=GIJEQf922Ov9ko0AHycgKkxdholgPW4TsZEYJIp/JtC+udhgtiBLppSC6DU9/YiIV8 Moj4MlkPnPNxe9jAlF3mFtTcnwmjQNYFcPx+iHLDJ60Zl3YD1o52r8KyVGCcBW3sxfDh iiEkt3eNlNl9gSanFoiAPZB/S7+3J6oQxI2Zv7XqdPg09yDUlcCDyXZYf5dZ40lSbmuI BuaCPDmfnmbhvL0uWvQPU820GE3d0i/lXJ8tQ12q7VJD1v14R8mxLbyxjm66gTf2oXr3 03Lk2CVMV5RyOjX6aCKLR/ur2E7Naet5SfMCaBkCcdoTRjimWet7TUqjMkZ11jlrdyxd FnJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036215; x=1711641015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4LWS7xvFoegnF0mSZFeKjpH3HSq3m0fIT12twQQtV6g=; b=w5qgDKXdBE2VNFwDtTI/jIS0T5R/MqIn6xd5UMxt6zFPUbMle7UsDjVoT+h4PxYp6T tAxXnKHmQoam3T82IJsBwDTt+hfqij1ffHhoTNY9agP3Jha3qOCdm5PdhY9V/cHM+NIS lM/lAzQCqL6y9phjMxiAFBm/vcUwjHUVQuwjimSSJIqmWGJ9KDr8dE+l2cTaHMdN6rr0 IvYgYTsrOWQxbE1xmZZJRvtSHiDqtEjkLd3qcouOmgYAGAc8+lm0C6l66L9/70ka0FPD Q1ibQ8D9GAJUKuQIAPDms6eFNQy8miNl2WxrIQPXlgMTf0kDbuzyKru3ss4rklPa5Cfj VG4A== X-Gm-Message-State: AOJu0Yz/0RrWgw75hp2556XG4QchdwrLuBr/uWXLTFQkilfccwVmT3rf juS6LenuKZpw58A5G0J7LENAWGZEBt62xQoXBYoKqJA50p0oFjAvZOpnFQfT18IUIvaizueo/g8 hS18= X-Google-Smtp-Source: AGHT+IEeQPhUy7k5Ot/s/fwB1HmG9WBBgDKW6+YXl8dX+9y6uFk/adnRBaAFqSwIZ5/3x8GqHetqlA== X-Received: by 2002:a05:600c:4e8f:b0:414:1fc:2ef3 with SMTP id f15-20020a05600c4e8f00b0041401fc2ef3mr2378590wmq.29.1711036215092; Thu, 21 Mar 2024 08:50:15 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id iv13-20020a05600c548d00b0041463334822sm134735wmb.26.2024.03.21.08.50.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 12/21] target/nios2: Replace qemu_printf() by monitor_printf() in monitor Date: Thu, 21 Mar 2024 16:48:28 +0100 Message-ID: <20240321154838.95771-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- target/nios2/monitor.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/target/nios2/monitor.c b/target/nios2/monitor.c index c6043769e4..983c16d7f8 100644 --- a/target/nios2/monitor.c +++ b/target/nios2/monitor.c @@ -22,7 +22,6 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "qemu/qemu-print.h" #include "cpu.h" #include "monitor/monitor.h" #include "monitor/hmp-target.h" @@ -32,24 +31,24 @@ void nios2_info_mmu(Monitor *mon, CPUNios2State *env) { Nios2CPU *cpu = env_archcpu(env); - qemu_printf("MMU: ways %d, entries %d, pid bits %d\n", - cpu->tlb_num_ways, cpu->tlb_num_entries, - cpu->pid_num_bits); + monitor_printf(mon, "MMU: ways %d, entries %d, pid bits %d\n", + cpu->tlb_num_ways, cpu->tlb_num_entries, + cpu->pid_num_bits); for (int i = 0; i < cpu->tlb_num_entries; i++) { Nios2TLBEntry *entry = &env->mmu.tlb[i]; - qemu_printf("TLB[%d] = %08X %08X %c VPN %05X " - "PID %02X %c PFN %05X %c%c%c%c\n", - i, entry->tag, entry->data, - (entry->tag & (1 << 10)) ? 'V' : '-', - entry->tag >> 12, - entry->tag & ((1 << cpu->pid_num_bits) - 1), - (entry->tag & (1 << 11)) ? 'G' : '-', - FIELD_EX32(entry->data, CR_TLBACC, PFN), - (entry->data & CR_TLBACC_C) ? 'C' : '-', - (entry->data & CR_TLBACC_R) ? 'R' : '-', - (entry->data & CR_TLBACC_W) ? 'W' : '-', - (entry->data & CR_TLBACC_X) ? 'X' : '-'); + monitor_printf(mon, "TLB[%d] = %08X %08X %c VPN %05X " + "PID %02X %c PFN %05X %c%c%c%c\n", + i, entry->tag, entry->data, + (entry->tag & (1 << 10)) ? 'V' : '-', + entry->tag >> 12, + entry->tag & ((1 << cpu->pid_num_bits) - 1), + (entry->tag & (1 << 11)) ? 'G' : '-', + FIELD_EX32(entry->data, CR_TLBACC, PFN), + (entry->data & CR_TLBACC_C) ? 'C' : '-', + (entry->data & CR_TLBACC_R) ? 'R' : '-', + (entry->data & CR_TLBACC_W) ? 'W' : '-', + (entry->data & CR_TLBACC_X) ? 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Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 13/21] target/ppc: Replace qemu_printf() by monitor_printf() in monitor Date: Thu, 21 Mar 2024 16:48:29 +0100 Message-ID: <20240321154838.95771-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- target/ppc/cpu.h | 2 +- target/ppc/mmu_common.c | 147 +++++++++++++++++++------------------- target/ppc/ppc-qmp-cmds.c | 2 +- 3 files changed, 77 insertions(+), 74 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 67e6b2effd..52ac667470 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2982,7 +2982,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) } #endif -void dump_mmu(CPUPPCState *env); +void ppc_dump_mmu(Monitor *mon, CPUPPCState *env); void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 751403f1c8..ba8e91b949 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -32,6 +32,7 @@ #include "internal.h" #include "mmu-book3s-v3.h" #include "mmu-radix64.h" +#include "monitor/monitor.h" /* #define DUMP_PAGE_TABLES */ @@ -924,21 +925,21 @@ static const char *book3e_tsize_to_str[32] = { "1T", "2T" }; -static void mmubooke_dump_mmu(CPUPPCState *env) +static void mmubooke_dump_mmu(Monitor *mon, CPUPPCState *env) { ppcemb_tlb_t *entry; int i; #ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { - qemu_printf("Cannot access KVM TLB\n"); + monitor_puts(mon, "Cannot access KVM TLB\n"); return; } #endif - qemu_printf("\nTLB:\n"); - qemu_printf("Effective Physical Size PID Prot " - "Attr\n"); + monitor_puts(mon, "\nTLB:\n"); + monitor_puts(mon, "Effective Physical Size PID Prot " + "Attr\n"); entry = &env->tlb.tlbe[0]; for (i = 0; i < env->nb_tlb; i++, entry++) { @@ -962,22 +963,22 @@ static void mmubooke_dump_mmu(CPUPPCState *env) } else { snprintf(size_buf, sizeof(size_buf), "%3" PRId64 "k", size / KiB); } - qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n", - (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID, - entry->prot, entry->attr); + monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %s %-5u %08x %08x\n", + (uint64_t)ea, (uint64_t)pa, size_buf, (uint32_t)entry->PID, + entry->prot, entry->attr); } } -static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset, - int tlbsize) +static void mmubooke206_dump_one_tlb(Monitor *mon, CPUPPCState *env, + int tlbn, int offset, int tlbsize) { ppcmas_tlb_t *entry; int i; - qemu_printf("\nTLB%d:\n", tlbn); - qemu_printf("Effective Physical Size TID TS SRWX" - " URWX WIMGE U0123\n"); + monitor_printf(mon, "\nTLB%d:\n", tlbn); + monitor_puts(mon, "Effective Physical Size TID TS SRWX" + " URWX WIMGE U0123\n"); entry = &env->tlb.tlbm[offset]; for (i = 0; i < tlbsize; i++, entry++) { @@ -993,38 +994,38 @@ static void mmubooke206_dump_one_tlb(CPUPPCState *env, int tlbn, int offset, ea = entry->mas2 & ~(size - 1); pa = entry->mas7_3 & ~(size - 1); - qemu_printf("0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c" - " U%c%c%c %c%c%c%c%c U%c%c%c%c\n", - (uint64_t)ea, (uint64_t)pa, - book3e_tsize_to_str[tsize], - (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT, - (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT, - entry->mas7_3 & MAS3_SR ? 'R' : '-', - entry->mas7_3 & MAS3_SW ? 'W' : '-', - entry->mas7_3 & MAS3_SX ? 'X' : '-', - entry->mas7_3 & MAS3_UR ? 'R' : '-', - entry->mas7_3 & MAS3_UW ? 'W' : '-', - entry->mas7_3 & MAS3_UX ? 'X' : '-', - entry->mas2 & MAS2_W ? 'W' : '-', - entry->mas2 & MAS2_I ? 'I' : '-', - entry->mas2 & MAS2_M ? 'M' : '-', - entry->mas2 & MAS2_G ? 'G' : '-', - entry->mas2 & MAS2_E ? 'E' : '-', - entry->mas7_3 & MAS3_U0 ? '0' : '-', - entry->mas7_3 & MAS3_U1 ? '1' : '-', - entry->mas7_3 & MAS3_U2 ? '2' : '-', - entry->mas7_3 & MAS3_U3 ? '3' : '-'); + monitor_printf(mon, "0x%016" PRIx64 " 0x%016" PRIx64 " %4s %-5u %1u S%c%c%c" + " U%c%c%c %c%c%c%c%c U%c%c%c%c\n", + (uint64_t)ea, (uint64_t)pa, + book3e_tsize_to_str[tsize], + (entry->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT, + (entry->mas1 & MAS1_TS) >> MAS1_TS_SHIFT, + entry->mas7_3 & MAS3_SR ? 'R' : '-', + entry->mas7_3 & MAS3_SW ? 'W' : '-', + entry->mas7_3 & MAS3_SX ? 'X' : '-', + entry->mas7_3 & MAS3_UR ? 'R' : '-', + entry->mas7_3 & MAS3_UW ? 'W' : '-', + entry->mas7_3 & MAS3_UX ? 'X' : '-', + entry->mas2 & MAS2_W ? 'W' : '-', + entry->mas2 & MAS2_I ? 'I' : '-', + entry->mas2 & MAS2_M ? 'M' : '-', + entry->mas2 & MAS2_G ? 'G' : '-', + entry->mas2 & MAS2_E ? 'E' : '-', + entry->mas7_3 & MAS3_U0 ? '0' : '-', + entry->mas7_3 & MAS3_U1 ? '1' : '-', + entry->mas7_3 & MAS3_U2 ? '2' : '-', + entry->mas7_3 & MAS3_U3 ? '3' : '-'); } } -static void mmubooke206_dump_mmu(CPUPPCState *env) +static void mmubooke206_dump_mmu(Monitor *mon, CPUPPCState *env) { int offset = 0; int i; #ifdef CONFIG_KVM if (kvm_enabled() && !env->kvm_sw_tlb) { - qemu_printf("Cannot access KVM TLB\n"); + monitor_puts(mon, "Cannot access KVM TLB\n"); return; } #endif @@ -1036,12 +1037,12 @@ static void mmubooke206_dump_mmu(CPUPPCState *env) continue; } - mmubooke206_dump_one_tlb(env, i, offset, size); + mmubooke206_dump_one_tlb(mon, env, i, offset, size); offset += size; } } -static void mmu6xx_dump_BATs(CPUPPCState *env, int type) +static void mmu6xx_dump_BATs(Monitor *mon, CPUPPCState *env, int type) { target_ulong *BATlt, *BATut, *BATu, *BATl; target_ulong BEPIl, BEPIu, bl; @@ -1064,51 +1065,53 @@ static void mmu6xx_dump_BATs(CPUPPCState *env, int type) BEPIu = *BATu & 0xF0000000; BEPIl = *BATu & 0x0FFE0000; bl = (*BATu & 0x00001FFC) << 15; - qemu_printf("%s BAT%d BATu " TARGET_FMT_lx - " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " - TARGET_FMT_lx " " TARGET_FMT_lx "\n", - type == ACCESS_CODE ? "code" : "data", i, - *BATu, *BATl, BEPIu, BEPIl, bl); + monitor_printf(mon, "%s BAT%d BATu " TARGET_FMT_lx + " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " + TARGET_FMT_lx " " TARGET_FMT_lx "\n", + type == ACCESS_CODE ? "code" : "data", i, + *BATu, *BATl, BEPIu, BEPIl, bl); } } -static void mmu6xx_dump_mmu(CPUPPCState *env) +static void mmu6xx_dump_mmu(Monitor *mon, CPUPPCState *env) { PowerPCCPU *cpu = env_archcpu(env); ppc6xx_tlb_t *tlb; target_ulong sr; int type, way, entry, i; - qemu_printf("HTAB base = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_base(cpu)); - qemu_printf("HTAB mask = 0x%"HWADDR_PRIx"\n", ppc_hash32_hpt_mask(cpu)); + monitor_printf(mon, "HTAB base = 0x%"HWADDR_PRIx"\n", + ppc_hash32_hpt_base(cpu)); + monitor_printf(mon, "HTAB mask = 0x%"HWADDR_PRIx"\n", + ppc_hash32_hpt_mask(cpu)); - qemu_printf("\nSegment registers:\n"); + monitor_puts(mon, "\nSegment registers:\n"); for (i = 0; i < 32; i++) { sr = env->sr[i]; if (sr & 0x80000000) { - qemu_printf("%02d T=%d Ks=%d Kp=%d BUID=0x%03x " - "CNTLR_SPEC=0x%05x\n", i, - sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, - sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF), - (uint32_t)(sr & 0xFFFFF)); + monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d BUID=0x%03x " + "CNTLR_SPEC=0x%05x\n", i, + sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, + sr & 0x20000000 ? 1 : 0, (uint32_t)((sr >> 20) & 0x1FF), + (uint32_t)(sr & 0xFFFFF)); } else { - qemu_printf("%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i, - sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, - sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0, - (uint32_t)(sr & 0x00FFFFFF)); + monitor_printf(mon, "%02d T=%d Ks=%d Kp=%d N=%d VSID=0x%06x\n", i, + sr & 0x80000000 ? 1 : 0, sr & 0x40000000 ? 1 : 0, + sr & 0x20000000 ? 1 : 0, sr & 0x10000000 ? 1 : 0, + (uint32_t)(sr & 0x00FFFFFF)); } } - qemu_printf("\nBATs:\n"); - mmu6xx_dump_BATs(env, ACCESS_INT); - mmu6xx_dump_BATs(env, ACCESS_CODE); + monitor_puts(mon, "\nBATs:\n"); + mmu6xx_dump_BATs(mon, env, ACCESS_INT); + mmu6xx_dump_BATs(mon, env, ACCESS_CODE); if (env->id_tlbs != 1) { - qemu_printf("ERROR: 6xx MMU should have separated TLB" - " for code and data\n"); + monitor_puts(mon, "ERROR: 6xx MMU should have separated TLB" + " for code and data\n"); } - qemu_printf("\nTLBs [EPN EPN + SIZE]\n"); + monitor_puts(mon, "\nTLBs [EPN EPN + SIZE]\n"); for (type = 0; type < 2; type++) { for (way = 0; way < env->nb_ways; way++) { @@ -1117,28 +1120,28 @@ static void mmu6xx_dump_mmu(CPUPPCState *env) entry++) { tlb = &env->tlb.tlb6[entry]; - qemu_printf("%s TLB %02d/%02d way:%d %s [" - TARGET_FMT_lx " " TARGET_FMT_lx "]\n", - type ? "code" : "data", entry % env->nb_tlb, - env->nb_tlb, way, - pte_is_valid(tlb->pte0) ? "valid" : "inval", - tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE); + monitor_printf(mon, "%s TLB %02d/%02d way:%d %s [" + TARGET_FMT_lx " " TARGET_FMT_lx "]\n", + type ? "code" : "data", entry % env->nb_tlb, + env->nb_tlb, way, + pte_is_valid(tlb->pte0) ? "valid" : "inval", + tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE); } } } } -void dump_mmu(CPUPPCState *env) +void ppc_dump_mmu(Monitor *mon, CPUPPCState *env) { switch (env->mmu_model) { case POWERPC_MMU_BOOKE: - mmubooke_dump_mmu(env); + mmubooke_dump_mmu(mon, env); break; case POWERPC_MMU_BOOKE206: - mmubooke206_dump_mmu(env); + mmubooke206_dump_mmu(mon, env); break; case POWERPC_MMU_SOFT_6xx: - mmu6xx_dump_mmu(env); + mmu6xx_dump_mmu(mon, env); break; #if defined(TARGET_PPC64) case POWERPC_MMU_64B: diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c index a25d86a8d1..e798c30f91 100644 --- a/target/ppc/ppc-qmp-cmds.c +++ b/target/ppc/ppc-qmp-cmds.c @@ -88,7 +88,7 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) monitor_printf(mon, "No CPU available\n"); return; } - dump_mmu(env1); + ppc_dump_mmu(mon, env1); } const MonitorDef monitor_defs[] = { From patchwork Thu Mar 21 15:48:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5A794C54E58 for ; Thu, 21 Mar 2024 15:51:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKgg-0008Eb-00; Thu, 21 Mar 2024 11:50:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKgc-0007sa-NG for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:35 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKgY-000201-RX for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:34 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-568a53d2ce0so1551729a12.0 for ; Thu, 21 Mar 2024 08:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036229; x=1711641029; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2zDd1vJ1m0kg+6reKiJJAv3Gd7RU3RjeGbW9KAoTqqc=; b=u2rQNocduOI+t1ABSpdjW3mvJpfffGYmGgPrJVlFVeDA3vtsDLVcP5Cxx93Tr7L9qz hTNbCMpaZ8cvsb/UbkofxlsdwT3hdM+rwC4+61rTStbUCPyniEOZIPeqTStEzlN6OM5T vTrY7zF8tGoLmWPFpo67vXHHMTQOCBgE7bfWVwyeJ05NDA4370uH+HAdvNwi0FqlVP3/ okWJcwPgn5lEC3tu/ADITvHQtCkkL7sx58fnHs5rVQth2bBcDzFur8DtMqyMvUljBu8+ aZbFK/ew7Z8NBibcoevMEh5Cm4gDB4qwCNH1Ty6GXCe3FDrVHaNEpoLhs52dFqFttGyd bZSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036229; x=1711641029; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2zDd1vJ1m0kg+6reKiJJAv3Gd7RU3RjeGbW9KAoTqqc=; b=Ku5ToJc+3RH/nEmi4KPjO1DX4PjhO6joE6GvCrCFq9jeTjaKq5ZhhRxMk4wVbXNqgF TG5dfBO7M3MVMog6hbKMMalqpN87AfMld7yQxk9JrkANfq3rjtFEKyIdt0AfQBxzkqb4 ivxOfnZn3AloBsRxBF96C3o5kOnpyPtrnpQFhzASXRL4BTqA50m3STQX1mAlrIvG3cgW yexsqRxv+AVJW6k+UMByxRvZG+LVYDGSS0qF6Px2H/beQ4tOz9SAhu5619uGGIkwBE5t BCDsELUuACPQX5WprHsghYIGnrzxsdXDsA3wVGqNbelOmTVgzSiopFGP6atKWL7IfS9Q yjUw== X-Gm-Message-State: AOJu0YwefEHyTM4H5oQO4DI0PgTkoizOBsKTnM34o0GYM301Ldwq7QIU vS1QjvkqbhL/DtTztTSkycLkxHrxLMuDWAQPeUxWbKOXYi7KsRXVF4dKppPigTG4jgQYw/6MQ01 6/RA= X-Google-Smtp-Source: AGHT+IE2nkP3/s+ZVl7OIbnsBZ7cJXuE1J4tybtt6Fys94AA+96zHcj+6baTb+fsUqIjIJvE7tyf0Q== X-Received: by 2002:a17:906:a44c:b0:a47:e19:81c7 with SMTP id cb12-20020a170906a44c00b00a470e1981c7mr1678931ejb.21.1711036228996; Thu, 21 Mar 2024 08:50:28 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id o26-20020a17090637da00b00a46e68a1fa0sm54362ejc.53.2024.03.21.08.50.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 14/21] target/sh4: Extract sh4_dump_mmu() from hmp_info_tlb() Date: Thu, 21 Mar 2024 16:48:30 +0100 Message-ID: <20240321154838.95771-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philmd@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract sh4_dump_mmu() from hmp_info_tlb(), replacing monitor_printf(FIXED_STRING_WITHOUT_FORMAT) by monitor_puts(). Signed-off-by: Philippe Mathieu-Daudé --- target/sh4/cpu.h | 2 ++ target/sh4/monitor.c | 22 +++++++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9211da6bde..4e2e9ffd66 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -385,4 +385,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, #endif } +void sh4_dump_mmu(Monitor *mon, CPUSH4State *env); + #endif /* SH4_CPU_H */ diff --git a/target/sh4/monitor.c b/target/sh4/monitor.c index 2da6a5426e..1befb42b07 100644 --- a/target/sh4/monitor.c +++ b/target/sh4/monitor.c @@ -39,20 +39,28 @@ static void print_tlb(Monitor *mon, int idx, tlb_t *tlb) tlb->d, tlb->wt); } +void sh4_dump_mmu(Monitor *mon, CPUSH4State *env) +{ + int i; + + monitor_puts(mon, "ITLB:\n"); + for (i = 0 ; i < ITLB_SIZE ; i++) { + print_tlb (mon, i, &env->itlb[i]); + } + monitor_puts(mon, "UTLB:\n"); + for (i = 0 ; i < UTLB_SIZE ; i++) { + print_tlb (mon, i, &env->utlb[i]); + } +} + void hmp_info_tlb(Monitor *mon, const QDict *qdict) { CPUArchState *env = mon_get_cpu_env(mon); - int i; if (!env) { monitor_printf(mon, "No CPU available\n"); return; } - monitor_printf (mon, "ITLB:\n"); - for (i = 0 ; i < ITLB_SIZE ; i++) - print_tlb (mon, i, &env->itlb[i]); - monitor_printf (mon, "UTLB:\n"); - for (i = 0 ; i < UTLB_SIZE ; i++) - print_tlb (mon, i, &env->utlb[i]); + sh4_dump_mmu(mon, env); } From patchwork Thu Mar 21 15:48:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7539ACD11C2 for ; Thu, 21 Mar 2024 15:50:53 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKgp-0000Um-U0; Thu, 21 Mar 2024 11:50:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKgj-0000Hd-O2 for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:41 -0400 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKgf-00025C-Ut for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:50:40 -0400 Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-a4707502aafso204994466b.0 for ; Thu, 21 Mar 2024 08:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036236; x=1711641036; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3j55vDhtvgXvqb+wl9u2AW0u4cGKkyngFQ2jp+MBRmU=; b=en8F9YfVAR5zJfwlRf6vkTDvTDCov1zpNGD37XpiLrHoGTBZcSSMXgegF9trq9NjrO a5d13c6sIEN1pUkcHvSTmaoipJ/cC40n++c8rIaj7l9b0v94xr0GHfY1iWsKX+dwd8mj HEqeVfBD18c86P/eGGX6JnwKrenP6uh3bEXougSc5EfxV1z6Epp1E/4/+aE7EEMfQyrt ih+f26vdxEAvPlKWYRJMKRXCBypC6DA+UTHu2KxAUltw0T4Jmt7YbA1VOnfXME1NKA6e WqX7eu7CcAN56JXfkE462k2W79QINbO5CNiAG7Eg2zibbvHCN9QpNsQrNr+FC183guc/ 4Exw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036236; x=1711641036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3j55vDhtvgXvqb+wl9u2AW0u4cGKkyngFQ2jp+MBRmU=; b=gyCEZWbyzJ+c4ddUVvG8X9Xg7u1piCBCD5koZdcODF6tbLg4ZbbP9SrwUuOBMOTS/5 Kzc+V3L/p3PkPt+DpF0y9fjmiIH6bpb5MZJs4iMh+Mue98FZlleRFht4zR5qoCaLiFWu 3Vd/jjIyzyGSZuzxmwwo+SZ5tteVEi4GXh7aoRa0ZQapfQ0bfRPcECv+5RXvlOXk29HG R1z2reEhMB3OzbEyH6mE5/cmx4bHPPjdWP/mn0P0V8HXQpgNK88sqtMa0tJBTJFvoFS2 J+JoKxxGLTIQnjx78T99ljocf/P6KwBkr895hIXt3JH3tpiNO3k0LGGNn8UOMjbi/kYE RNCw== X-Gm-Message-State: AOJu0YyF0ODRg+pJ42kvlZPLNGBob1ZtunNHjvAgKYmH7/lQWrn3DU7L 3V5EVg9VPo8vdt+EXjNG+46Y8HUADbTAPB84bHkNVvnp6+it2TyiAX+6yZYSuZ2pxnaZrjkqrwd 8w9g= X-Google-Smtp-Source: AGHT+IFRSRO+fdMOTgprlXH0Zd9WRAFvm//y4djnsbaR2xZxibyh6sIRkiLEm5NXNehMk0OBzI8ynw== X-Received: by 2002:a17:906:a48:b0:a46:2b8b:e381 with SMTP id x8-20020a1709060a4800b00a462b8be381mr2607800ejf.8.1711036235960; Thu, 21 Mar 2024 08:50:35 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id c14-20020a170906340e00b00a46baa4723asm48238ejb.119.2024.03.21.08.50.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.0? 15/21] target/sparc: Fix string format errors when DEBUG_MMU is defined Date: Thu, 21 Mar 2024 16:48:31 +0100 Message-ID: <20240321154838.95771-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Fix when building with DEBUG_MMU: target/sparc/ldst_helper.c:245:72: error: format specifies type 'unsigned long' but the argument has type 'uint64_t' (aka 'unsigned long long') [-Werror,-Wformat] DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, ~~~ ^~~~~ %llx target/sparc/ldst_helper.c:1736:60: error: no member named 'immuregs' in 'struct CPUArchState' PRIx64 "\n", reg, oldreg, env->immuregs[reg]); ~~~ ^ target/sparc/ldst_helper.c:1820:60: error: no member named 'dmmuregs' in 'struct CPUArchState' PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); ~~~ ^ Fixes: 96df2bc99f ("target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs") Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/ldst_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index e581bb42ac..064390d1d4 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -242,8 +242,8 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, if (new_vaddr == vaddr || (new_vaddr < vaddr + size && vaddr < new_vaddr + new_size)) { - DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, - new_vaddr); + DPRINTF_MMU("auto demap entry [%d] %"PRIx64"->%"PRIx64"\n", + i, vaddr, new_vaddr); replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); return; } @@ -1733,7 +1733,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, if (oldreg != env->immu.mmuregs[reg]) { DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" - PRIx64 "\n", reg, oldreg, env->immuregs[reg]); + PRIx64 "\n", reg, oldreg, env->immu.mmuregs[reg]); } #ifdef DEBUG_MMU dump_mmu(env); @@ -1817,7 +1817,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, if (oldreg != env->dmmu.mmuregs[reg]) { DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" - PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); + PRIx64 "\n", reg, oldreg, env->dmmu.mmuregs[reg]); } #ifdef DEBUG_MMU dump_mmu(env); From patchwork Thu Mar 21 15:48:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D11F9C54E58 for ; Thu, 21 Mar 2024 15:51:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKhY-0001Z0-2W; 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Thu, 21 Mar 2024 08:50:42 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id g27-20020a170906395b00b00a466fccbe96sm48234eje.122.2024.03.21.08.50.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 16/21] target/sparc: Replace qemu_printf() by monitor_printf() in monitor Date: Thu, 21 Mar 2024 16:48:32 +0100 Message-ID: <20240321154838.95771-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace qemu_printf() by monitor_printf() in monitor.c. Rename dump_mmu() as sparc_dump_mmu(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- target/sparc/cpu.h | 2 +- target/sparc/ldst_helper.c | 18 +++---- target/sparc/mmu_helper.c | 102 ++++++++++++++++++------------------- target/sparc/monitor.c | 2 +- 4 files changed, 62 insertions(+), 62 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index f3cdd17c62..55589c8ae4 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -601,7 +601,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev); -void dump_mmu(CPUSPARCState *env); +void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env); #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr, diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 064390d1d4..44f8b2bb7a 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -195,7 +195,7 @@ static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr, replace_tlb_entry(&tlb[i], 0, 0, env1); #ifdef DEBUG_MMU DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i); - dump_mmu(env1); + sparc_dump_mmu(env1); #endif } } @@ -257,7 +257,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1); #ifdef DEBUG_MMU DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i); - dump_mmu(env1); + sparc_dump_mmu(env1); #endif return; } @@ -276,7 +276,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb, #ifdef DEBUG_MMU DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n", strmmu, (replace_used ? "used" : "unused"), i); - dump_mmu(env1); + sparc_dump_mmu(env1); #endif return; } @@ -995,7 +995,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, break; } #ifdef DEBUG_MMU - dump_mmu(env); + sparc_dump_mmu(env); #endif } break; @@ -1050,7 +1050,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, reg, oldreg, env->mmuregs[reg]); } #ifdef DEBUG_MMU - dump_mmu(env); + sparc_dump_mmu(env); #endif } break; @@ -1736,7 +1736,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, PRIx64 "\n", reg, oldreg, env->immu.mmuregs[reg]); } #ifdef DEBUG_MMU - dump_mmu(env); + sparc_dump_mmu(env); #endif return; } @@ -1760,7 +1760,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, } #ifdef DEBUG_MMU DPRINTF_MMU("immu data access replaced entry [%i]\n", i); - dump_mmu(env); + sparc_dump_mmu(env); #endif return; } @@ -1820,7 +1820,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, PRIx64 "\n", reg, oldreg, env->dmmu.mmuregs[reg]); } #ifdef DEBUG_MMU - dump_mmu(env); + sparc_dump_mmu(env); #endif return; } @@ -1842,7 +1842,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, } #ifdef DEBUG_MMU DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i); - dump_mmu(env); + sparc_dump_mmu(env); #endif return; } diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index ad1591d9fd..f325c9a4cc 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" +#include "monitor/monitor.h" #include "trace.h" /* Sparc MMU emulation */ @@ -344,7 +344,7 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) return 0; } -void dump_mmu(CPUSPARCState *env) +void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env) { CPUState *cs = env_cpu(env); target_ulong va, va1, va2; @@ -352,29 +352,29 @@ void dump_mmu(CPUSPARCState *env) hwaddr pa; uint32_t pde; - qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n", - (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); + monitor_printf(mon, "Root ptr: " HWADDR_FMT_plx ", ctx: %d\n", + (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { pde = mmu_probe(env, va, 2); if (pde) { pa = cpu_get_phys_page_debug(cs, va); - qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx - " PDE: " TARGET_FMT_lx "\n", va, pa, pde); + monitor_printf(mon, "VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx + " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { pde = mmu_probe(env, va1, 1); if (pde) { pa = cpu_get_phys_page_debug(cs, va1); - qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", - va1, pa, pde); + monitor_printf(mon, " VA: " TARGET_FMT_lx ", PA: " + HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", + va1, pa, pde); for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { pde = mmu_probe(env, va2, 0); if (pde) { pa = cpu_get_phys_page_debug(cs, va2); - qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - HWADDR_FMT_plx " PTE: " - TARGET_FMT_lx "\n", - va2, pa, pde); + monitor_printf(mon, " VA: " TARGET_FMT_lx ", PA: " + HWADDR_FMT_plx " PTE: " + TARGET_FMT_lx "\n", + va2, pa, pde); } } } @@ -777,21 +777,21 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, cpu_loop_exit_restore(cs, retaddr); } -void dump_mmu(CPUSPARCState *env) +void sparc_dump_mmu(Monitor *mon, CPUSPARCState *env) { unsigned int i; const char *mask; - qemu_printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" - PRId64 "\n", - env->dmmu.mmu_primary_context, - env->dmmu.mmu_secondary_context); - qemu_printf("DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64 - "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); + monitor_printf(mon, "MMU contexts: Primary: %" PRId64 ", Secondary: %" + PRId64 "\n", + env->dmmu.mmu_primary_context, + env->dmmu.mmu_secondary_context); + monitor_printf(mon, "DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64 + "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target); if ((env->lsu & DMMU_E) == 0) { - qemu_printf("DMMU disabled\n"); + monitor_printf(mon, "DMMU disabled\n"); } else { - qemu_printf("DMMU dump\n"); + monitor_printf(mon, "DMMU dump\n"); for (i = 0; i < 64; i++) { switch (TTE_PGSIZE(env->dtlb[i].tte)) { default: @@ -809,28 +809,28 @@ void dump_mmu(CPUSPARCState *env) break; } if (TTE_IS_VALID(env->dtlb[i].tte)) { - qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n", - i, - env->dtlb[i].tag & (uint64_t)~0x1fffULL, - TTE_PA(env->dtlb[i].tte), - mask, - TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", - TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", - TTE_IS_LOCKED(env->dtlb[i].tte) ? - "locked" : "unlocked", - TTE_IS_IE(env->dtlb[i].tte) ? - "yes" : "no", - env->dtlb[i].tag & (uint64_t)0x1fffULL, - TTE_IS_GLOBAL(env->dtlb[i].tte) ? - "global" : "local"); + monitor_printf(mon, "[%02u] VA: %" PRIx64 ", PA: %llx" + ", %s, %s, %s, %s, ie %s, ctx %" PRId64 " %s\n", + i, + env->dtlb[i].tag & (uint64_t)~0x1fffULL, + TTE_PA(env->dtlb[i].tte), + mask, + TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user", + TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO", + TTE_IS_LOCKED(env->dtlb[i].tte) ? + "locked" : "unlocked", + TTE_IS_IE(env->dtlb[i].tte) ? + "yes" : "no", + env->dtlb[i].tag & (uint64_t)0x1fffULL, + TTE_IS_GLOBAL(env->dtlb[i].tte) ? + "global" : "local"); } } } if ((env->lsu & IMMU_E) == 0) { - qemu_printf("IMMU disabled\n"); + monitor_printf(mon, "IMMU disabled\n"); } else { - qemu_printf("IMMU dump\n"); + monitor_printf(mon, "IMMU dump\n"); for (i = 0; i < 64; i++) { switch (TTE_PGSIZE(env->itlb[i].tte)) { default: @@ -848,18 +848,18 @@ void dump_mmu(CPUSPARCState *env) break; } if (TTE_IS_VALID(env->itlb[i].tte)) { - qemu_printf("[%02u] VA: %" PRIx64 ", PA: %llx" - ", %s, %s, %s, ctx %" PRId64 " %s\n", - i, - env->itlb[i].tag & (uint64_t)~0x1fffULL, - TTE_PA(env->itlb[i].tte), - mask, - TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user", - TTE_IS_LOCKED(env->itlb[i].tte) ? - "locked" : "unlocked", - env->itlb[i].tag & (uint64_t)0x1fffULL, - TTE_IS_GLOBAL(env->itlb[i].tte) ? - "global" : "local"); + monitor_printf(mon, "[%02u] VA: %" PRIx64 ", PA: %llx" + ", %s, %s, %s, ctx %" PRId64 " %s\n", + i, + env->itlb[i].tag & (uint64_t)~0x1fffULL, + TTE_PA(env->itlb[i].tte), + mask, + TTE_IS_PRIV(env->itlb[i].tte) ? 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Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 17/21] target/xtensa: Prefix MMU API with 'xtensa_' Date: Thu, 21 Mar 2024 16:48:33 +0100 Message-ID: <20240321154838.95771-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philmd@linaro.org; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In order to extract the MMU API to a new "mmu.h" header, prefix it with the target name. Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 4 ++-- target/xtensa/cpu.c | 2 +- target/xtensa/mmu_helper.c | 41 +++++++++++++++++++++----------------- target/xtensa/monitor.c | 2 +- 4 files changed, 27 insertions(+), 22 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6b8d0636d2..b2cfc78e9d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -692,8 +692,8 @@ static inline int xtensa_get_cring(const CPUXtensaState *env) int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, uint32_t vaddr, int is_write, int mmu_idx, uint32_t *paddr, uint32_t *page_size, unsigned *access); -void reset_mmu(CPUXtensaState *env); -void dump_mmu(CPUXtensaState *env); +void xtensa_reset_mmu(CPUXtensaState *env); +void xtensa_dump_mmu(CPUXtensaState *env); static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 875cf843c9..ae0c4aab24 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -130,7 +130,7 @@ static void xtensa_cpu_reset_hold(Object *obj) env->exclusive_addr = -1; #ifndef CONFIG_USER_ONLY - reset_mmu(env); + xtensa_reset_mmu(env); cs->halted = env->runstall; #endif set_no_signaling_nans(!dfpu, &env->fp_status); diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 47063b0a57..31ee3fa957 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -139,7 +139,8 @@ static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, * Get bit mask for the 'VPN without index' field. * See ISA, 4.6.5.6, data format for RxTLB0 */ -static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) +static uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, + uint32_t way) { if (way < 4) { bool is32 = (dtlb ? @@ -168,9 +169,10 @@ static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) * Split virtual address into VPN (with index) and entry index * for the given TLB way */ -static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, - bool dtlb, uint32_t *vpn, - uint32_t wi, uint32_t *ei) +static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env, + uint32_t v, + bool dtlb, uint32_t *vpn, + uint32_t wi, uint32_t *ei) { bool varway56 = dtlb ? env->config->dtlb.varway56 : @@ -224,13 +226,15 @@ static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, * Split TLB address into TLB way, entry index and VPN (with index). * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format */ -static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, - uint32_t *vpn, uint32_t *wi, uint32_t *ei) +static bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, + uint32_t v, bool dtlb, + uint32_t *vpn, uint32_t *wi, + uint32_t *ei) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { *wi = v & (dtlb ? 0xf : 0x7); if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { - split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); return true; } else { return false; @@ -254,14 +258,14 @@ static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, env->itlb[wi] + ei; } -static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, +static xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, uint32_t v, bool dtlb, uint32_t *pwi) { uint32_t vpn; uint32_t wi; uint32_t ei; - if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { if (pwi) { *pwi = wi; } @@ -405,7 +409,7 @@ static void reset_tlb_region_way0(CPUXtensaState *env, } } -void reset_mmu(CPUXtensaState *env) +void xtensa_reset_mmu(CPUXtensaState *env) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { env->sregs[RASID] = 0x04030201; @@ -470,7 +474,7 @@ static int xtensa_tlb_lookup(const CPUXtensaState *env, for (wi = 0; wi < tlb->nways; ++wi) { uint32_t vpn; uint32_t ei; - split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); + xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { unsigned ring = get_ring(env, entry[wi][ei].asid); if (ring < 4) { @@ -493,10 +497,11 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; - const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); + const xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, &wi); if (entry) { - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + return (entry->vaddr & xtensa_get_vpn_mask(env, dtlb, wi)) + | entry->asid; } else { return 0; } @@ -507,7 +512,7 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { - const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); + const xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, NULL); if (entry) { return entry->paddr | entry->attr; @@ -520,7 +525,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; - xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); + xtensa_tlb_entry *entry = xtensa_get_tlb_entry(env, v, dtlb, &wi); if (entry && entry->variable && entry->asid) { tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid = 0; @@ -559,7 +564,7 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) uint32_t vpn; uint32_t wi; uint32_t ei; - if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); } } @@ -818,7 +823,7 @@ static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, may_lookup_pt && get_pte(env, vaddr, &pte)) { ring = (pte >> 4) & 0x3; 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Thu, 21 Mar 2024 08:50:57 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id z9-20020a05640235c900b00568a08a9aacsm14611edc.22.2024.03.21.08.50.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:50:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 18/21] target/xtensa: Extract MMU API to new mmu.c/mmu.h files Date: Thu, 21 Mar 2024 16:48:34 +0100 Message-ID: <20240321154838.95771-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=philmd@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract the MMU API and expose it via "mmu.h" so we can reuse the methods in target/xtensa/ files. Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 32 +- target/xtensa/mmu.h | 95 ++++ target/xtensa/mmu.c | 889 ++++++++++++++++++++++++++++++++++++ target/xtensa/mmu_helper.c | 892 +------------------------------------ target/xtensa/meson.build | 1 + 5 files changed, 991 insertions(+), 918 deletions(-) create mode 100644 target/xtensa/mmu.h create mode 100644 target/xtensa/mmu.c diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b2cfc78e9d..b67ee987f3 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -34,6 +34,10 @@ #include "hw/clock.h" #include "xtensa-isa.h" +typedef struct CPUArchState CPUXtensaState; + +#include "mmu.h" + /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -309,28 +313,6 @@ typedef enum { INTTYPE_MAX } interrupt_type; -typedef struct CPUArchState CPUXtensaState; - -typedef struct xtensa_tlb_entry { - uint32_t vaddr; - uint32_t paddr; - uint8_t asid; - uint8_t attr; - bool variable; -} xtensa_tlb_entry; - -typedef struct xtensa_tlb { - unsigned nways; - const unsigned way_size[10]; - bool varway56; - unsigned nrefillentries; -} xtensa_tlb; - -typedef struct xtensa_mpu_entry { - uint32_t vaddr; - uint32_t attr; -} xtensa_mpu_entry; - typedef struct XtensaGdbReg { int targno; unsigned flags; @@ -689,12 +671,6 @@ static inline int xtensa_get_cring(const CPUXtensaState *env) } #ifndef CONFIG_USER_ONLY -int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, unsigned *access); -void xtensa_reset_mmu(CPUXtensaState *env); -void xtensa_dump_mmu(CPUXtensaState *env); - static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) { return env->system_er; diff --git a/target/xtensa/mmu.h b/target/xtensa/mmu.h new file mode 100644 index 0000000000..3e1d2c03ea --- /dev/null +++ b/target/xtensa/mmu.h @@ -0,0 +1,95 @@ +/* + * Xtensa MMU/MPU helpers + * + * SPDX-FileCopyrightText: 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef TARGET_XTENSA_MMU_H +#define TARGET_XTENSA_MMU_H + +#include "cpu.h" + +typedef struct xtensa_tlb_entry { + uint32_t vaddr; + uint32_t paddr; + uint8_t asid; + uint8_t attr; + bool variable; +} xtensa_tlb_entry; + +typedef struct xtensa_tlb { + unsigned nways; + const unsigned way_size[10]; + bool varway56; + unsigned nrefillentries; +} xtensa_tlb; + +typedef struct xtensa_mpu_entry { + uint32_t vaddr; + uint32_t attr; +} xtensa_mpu_entry; + +#define XTENSA_MPU_SEGMENT_MASK 0x0000001f +#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 +#define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 +#define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 +#define XTENSA_MPU_MEM_TYPE_SHIFT 12 +#define XTENSA_MPU_ATTR_MASK 0x001fff00 + +#define XTENSA_MPU_PROBE_B 0x40000000 +#define XTENSA_MPU_PROBE_V 0x80000000 + +#define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 +#define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 +#define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 +#define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 + +#define XTENSA_MPU_TYPE_SYS_C 0x0010 +#define XTENSA_MPU_TYPE_SYS_W 0x0020 +#define XTENSA_MPU_TYPE_SYS_R 0x0040 +#define XTENSA_MPU_TYPE_CPU_C 0x0100 +#define XTENSA_MPU_TYPE_CPU_W 0x0200 +#define XTENSA_MPU_TYPE_CPU_R 0x0400 +#define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 +#define XTENSA_MPU_TYPE_B 0x1000 +#define XTENSA_MPU_TYPE_INT 0x2000 + +unsigned mmu_attr_to_access(uint32_t attr); +unsigned mpu_attr_to_access(uint32_t attr, unsigned ring); +unsigned mpu_attr_to_cpu_cache(uint32_t attr); +unsigned mpu_attr_to_type(uint32_t attr); + +unsigned region_attr_to_access(uint32_t attr); +unsigned cacheattr_attr_to_access(uint32_t attr); + +xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, + uint32_t v, bool dtlb, uint32_t *pwi); +xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei); +void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei, + uint32_t vpn, uint32_t pte); + +uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, + uint32_t way); +uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, + uint32_t way); + +bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, + uint32_t *vpn, uint32_t *wi, uint32_t *ei); + +int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, + uint32_t *pwi, uint32_t *pei, uint8_t *pring); +int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, + uint32_t vaddr, unsigned *segment); + +int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access); + +void xtensa_reset_mmu(CPUXtensaState *env); +void xtensa_dump_mmu(CPUXtensaState *env); + +#endif diff --git a/target/xtensa/mmu.c b/target/xtensa/mmu.c new file mode 100644 index 0000000000..4f17fb2980 --- /dev/null +++ b/target/xtensa/mmu.c @@ -0,0 +1,889 @@ +/* + * Copyright (c) 2011 - 2019, Max Filippov, Open Source and Linux Lab. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of the Open Source and Linux Lab nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "cpu.h" +#include "mmu.h" + +static uint32_t get_page_size(const CPUXtensaState *env, + bool dtlb, uint32_t way) +{ + uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; + + switch (way) { + case 4: + return (tlbcfg >> 16) & 0x3; + + case 5: + return (tlbcfg >> 20) & 0x1; + + case 6: + return (tlbcfg >> 24) & 0x1; + + default: + return 0; + } +} + +/*! + * Get bit mask for the virtual address bits translated by the TLB way + */ +uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, + bool dtlb, uint32_t way) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + bool varway56 = dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + switch (way) { + case 4: + return 0xfff00000 << get_page_size(env, dtlb, way) * 2; + + case 5: + if (varway56) { + return 0xf8000000 << get_page_size(env, dtlb, way); + } else { + return 0xf8000000; + } + + case 6: + if (varway56) { + return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); + } else { + return 0xf0000000; + } + + default: + return 0xfffff000; + } + } else { + return REGION_PAGE_MASK; + } +} + +/*! + * Get bit mask for the 'VPN without index' field. + * See ISA, 4.6.5.6, data format for RxTLB0 + */ +uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way) +{ + if (way < 4) { + bool is32 = (dtlb ? + env->config->dtlb.nrefillentries : + env->config->itlb.nrefillentries) == 32; + return is32 ? 0xffff8000 : 0xffffc000; + } else if (way == 4) { + return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; + } else if (way <= 6) { + uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); + bool varway56 = dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + if (varway56) { + return mask << (way == 5 ? 2 : 3); + } else { + return mask << 1; + } + } else { + return 0xfffff000; + } +} + +/*! + * Split virtual address into VPN (with index) and entry index + * for the given TLB way + */ +static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env, + uint32_t v, + bool dtlb, uint32_t *vpn, + uint32_t wi, uint32_t *ei) +{ + bool varway56 = dtlb ? + env->config->dtlb.varway56 : + env->config->itlb.varway56; + + if (!dtlb) { + wi &= 7; + } + + if (wi < 4) { + bool is32 = (dtlb ? + env->config->dtlb.nrefillentries : + env->config->itlb.nrefillentries) == 32; + *ei = (v >> 12) & (is32 ? 0x7 : 0x3); + } else { + switch (wi) { + case 4: + { + uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; + *ei = (v >> eibase) & 0x3; + } + break; + + case 5: + if (varway56) { + uint32_t eibase = 27 + get_page_size(env, dtlb, wi); + *ei = (v >> eibase) & 0x3; + } else { + *ei = (v >> 27) & 0x1; + } + break; + + case 6: + if (varway56) { + uint32_t eibase = 29 - get_page_size(env, dtlb, wi); + *ei = (v >> eibase) & 0x7; + } else { + *ei = (v >> 28) & 0x1; + } + break; + + default: + *ei = 0; + break; + } + } + *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); +} + +/*! + * Split TLB address into TLB way, entry index and VPN (with index). + * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format + */ +bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, + uint32_t *vpn, uint32_t *wi, uint32_t *ei) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + *wi = v & (dtlb ? 0xf : 0x7); + if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { + xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + return true; + } else { + return false; + } + } else { + *vpn = v & REGION_PAGE_MASK; + *wi = 0; + *ei = (v >> 29) & 0x7; + return true; + } +} + +xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei) +{ + const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; + + assert(wi < tlb->nways && ei < tlb->way_size[wi]); + return dtlb ? + env->dtlb[wi] + ei : + env->itlb[wi] + ei; +} + +xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, uint32_t v, + bool dtlb, uint32_t *pwi) +{ + uint32_t vpn; + uint32_t wi; + uint32_t ei; + + if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (pwi) { + *pwi = wi; + } + return xtensa_tlb_get_entry(env, dtlb, wi, ei); + } else { + return NULL; + } +} + +static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, + xtensa_tlb_entry *entry, bool dtlb, + unsigned wi, unsigned ei, uint32_t vpn, + uint32_t pte) +{ + entry->vaddr = vpn; + entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); + entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; + entry->attr = pte & 0xf; +} + +void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, + unsigned wi, unsigned ei, + uint32_t vpn, uint32_t pte) +{ + CPUState *cs = env_cpu(env); + xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); + + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + if (entry->variable) { + if (entry->asid) { + tlb_flush_page(cs, entry->vaddr); + } + xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); + tlb_flush_page(cs, entry->vaddr); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s %d, %d, %d trying to set immutable entry\n", + __func__, dtlb, wi, ei); + } + } else { + tlb_flush_page(cs, entry->vaddr); + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_REGION_TRANSLATION)) { + entry->paddr = pte & REGION_PAGE_MASK; + } + entry->attr = pte & 0xf; + } +} + +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + uint32_t paddr; + uint32_t page_size; + unsigned access; + + if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, + &paddr, &page_size, &access) == 0) { + return paddr; + } + if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, + &paddr, &page_size, &access) == 0) { + return paddr; + } + return ~0; +} + +static void reset_tlb_mmu_all_ways(CPUXtensaState *env, const xtensa_tlb *tlb, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) +{ + unsigned wi, ei; + + for (wi = 0; wi < tlb->nways; ++wi) { + for (ei = 0; ei < tlb->way_size[wi]; ++ei) { + entry[wi][ei].asid = 0; + entry[wi][ei].variable = true; + } + } +} + +static void reset_tlb_mmu_ways56(CPUXtensaState *env, const xtensa_tlb *tlb, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) +{ + if (!tlb->varway56) { + static const xtensa_tlb_entry way5[] = { + { + .vaddr = 0xd0000000, + .paddr = 0, + .asid = 1, + .attr = 7, + .variable = false, + }, { + .vaddr = 0xd8000000, + .paddr = 0, + .asid = 1, + .attr = 3, + .variable = false, + } + }; + static const xtensa_tlb_entry way6[] = { + { + .vaddr = 0xe0000000, + .paddr = 0xf0000000, + .asid = 1, + .attr = 7, + .variable = false, + }, { + .vaddr = 0xf0000000, + .paddr = 0xf0000000, + .asid = 1, + .attr = 3, + .variable = false, + } + }; + memcpy(entry[5], way5, sizeof(way5)); + memcpy(entry[6], way6, sizeof(way6)); + } else { + uint32_t ei; + for (ei = 0; ei < 8; ++ei) { + entry[6][ei].vaddr = ei << 29; + entry[6][ei].paddr = ei << 29; + entry[6][ei].asid = 1; + entry[6][ei].attr = 3; + } + } +} + +static void reset_tlb_region_way0(CPUXtensaState *env, + xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) +{ + unsigned ei; + + for (ei = 0; ei < 8; ++ei) { + entry[0][ei].vaddr = ei << 29; + entry[0][ei].paddr = ei << 29; + entry[0][ei].asid = 1; + entry[0][ei].attr = 2; + entry[0][ei].variable = true; + } +} + +void xtensa_reset_mmu(CPUXtensaState *env) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + env->sregs[RASID] = 0x04030201; + env->sregs[ITLBCFG] = 0; + env->sregs[DTLBCFG] = 0; + env->autorefill_idx = 0; + reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); + reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); + reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); + reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { + unsigned i; + + env->sregs[MPUENB] = 0; + env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; + env->sregs[CACHEADRDIS] = 0; + assert(env->config->n_mpu_bg_segments > 0 && + env->config->mpu_bg[0].vaddr == 0); + for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { + assert(env->config->mpu_bg[i].vaddr >= + env->config->mpu_bg[i - 1].vaddr); + } + } else { + env->sregs[CACHEATTR] = 0x22222222; + reset_tlb_region_way0(env, env->itlb); + reset_tlb_region_way0(env, env->dtlb); + } +} + +static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) +{ + unsigned i; + for (i = 0; i < 4; ++i) { + if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { + return i; + } + } + return 0xff; +} + +/*! + * Lookup xtensa TLB for the given virtual address. + * See ISA, 4.6.2.2 + * + * \param pwi: [out] way index + * \param pei: [out] entry index + * \param pring: [out] access ring + * \return 0 if ok, exception cause code otherwise + */ +int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb, + uint32_t *pwi, uint32_t *pei, uint8_t *pring) +{ + const xtensa_tlb *tlb = dtlb ? + &env->config->dtlb : &env->config->itlb; + const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? + env->dtlb : env->itlb; + + int nhits = 0; + unsigned wi; + + for (wi = 0; wi < tlb->nways; ++wi) { + uint32_t vpn; + uint32_t ei; + xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); + if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { + unsigned ring = get_ring(env, entry[wi][ei].asid); + if (ring < 4) { + if (++nhits > 1) { + return dtlb ? + LOAD_STORE_TLB_MULTI_HIT_CAUSE : + INST_TLB_MULTI_HIT_CAUSE; + } + *pwi = wi; + *pei = ei; + *pring = ring; + } + } + } + return nhits ? 0 : + (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); +} + +/*! + * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, 4.6.5.10 + */ +unsigned mmu_attr_to_access(uint32_t attr) +{ + unsigned access = 0; + + if (attr < 12) { + access |= PAGE_READ; + if (attr & 0x1) { + access |= PAGE_EXEC; + } + if (attr & 0x2) { + access |= PAGE_WRITE; + } + + switch (attr & 0xc) { + case 0: + access |= PAGE_CACHE_BYPASS; + break; + + case 4: + access |= PAGE_CACHE_WB; + break; + + case 8: + access |= PAGE_CACHE_WT; + break; + } + } else if (attr == 13) { + access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; + } + return access; +} + +/*! + * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, 4.6.3.3 + */ +unsigned region_attr_to_access(uint32_t attr) +{ + static const unsigned access[16] = { + [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, + [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, + [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, + [3] = PAGE_EXEC | PAGE_CACHE_WB, + [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, + }; + + return access[attr & 0xf]; +} + +/*! + * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. + * See ISA, A.2.14 The Cache Attribute Register + */ +unsigned cacheattr_attr_to_access(uint32_t attr) +{ + static const unsigned access[16] = { + [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, + [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, + [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, + [3] = PAGE_EXEC | PAGE_CACHE_WB, + [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, + [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, + }; + + return access[attr & 0xf]; +} + +struct attr_pattern { + uint32_t mask; + uint32_t value; +}; + +static int attr_pattern_match(uint32_t attr, + const struct attr_pattern *pattern, + size_t n) +{ + size_t i; + + for (i = 0; i < n; ++i) { + if ((attr & pattern[i].mask) == pattern[i].value) { + return 1; + } + } + return 0; +} + +unsigned mpu_attr_to_cpu_cache(uint32_t attr) +{ + static const struct attr_pattern cpu_c[] = { + { .mask = 0x18f, .value = 0x089 }, + { .mask = 0x188, .value = 0x080 }, + { .mask = 0x180, .value = 0x180 }, + }; + + unsigned type = 0; + + if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { + type |= XTENSA_MPU_TYPE_CPU_CACHE; + if (attr & 0x10) { + type |= XTENSA_MPU_TYPE_CPU_C; + } + if (attr & 0x20) { + type |= XTENSA_MPU_TYPE_CPU_W; + } + if (attr & 0x40) { + type |= XTENSA_MPU_TYPE_CPU_R; + } + } + return type; +} + +unsigned mpu_attr_to_type(uint32_t attr) +{ + static const struct attr_pattern device_type[] = { + { .mask = 0x1f6, .value = 0x000 }, + { .mask = 0x1f6, .value = 0x006 }, + }; + static const struct attr_pattern sys_nc_type[] = { + { .mask = 0x1fe, .value = 0x018 }, + { .mask = 0x1fe, .value = 0x01e }, + { .mask = 0x18f, .value = 0x089 }, + }; + static const struct attr_pattern sys_c_type[] = { + { .mask = 0x1f8, .value = 0x010 }, + { .mask = 0x188, .value = 0x080 }, + { .mask = 0x1f0, .value = 0x030 }, + { .mask = 0x180, .value = 0x180 }, + }; + static const struct attr_pattern b[] = { + { .mask = 0x1f7, .value = 0x001 }, + { .mask = 0x1f7, .value = 0x007 }, + { .mask = 0x1ff, .value = 0x019 }, + { .mask = 0x1ff, .value = 0x01f }, + }; + + unsigned type = 0; + + attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; + if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { + type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; + if (attr & 0x80) { + type |= XTENSA_MPU_TYPE_INT; + } + } + if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { + type |= XTENSA_MPU_SYSTEM_TYPE_NC; + } + if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { + type |= XTENSA_MPU_SYSTEM_TYPE_C; + if (attr & 0x1) { + type |= XTENSA_MPU_TYPE_SYS_C; + } + if (attr & 0x2) { + type |= XTENSA_MPU_TYPE_SYS_W; + } + if (attr & 0x4) { + type |= XTENSA_MPU_TYPE_SYS_R; + } + } + if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { + type |= XTENSA_MPU_TYPE_B; + } + type |= mpu_attr_to_cpu_cache(attr); + + return type; +} + +unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) +{ + static const unsigned access[2][16] = { + [0] = { + [4] = PAGE_READ, + [5] = PAGE_READ | PAGE_EXEC, + [6] = PAGE_READ | PAGE_WRITE, + [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [8] = PAGE_WRITE, + [9] = PAGE_READ | PAGE_WRITE, + [10] = PAGE_READ | PAGE_WRITE, + [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [12] = PAGE_READ, + [13] = PAGE_READ | PAGE_EXEC, + [14] = PAGE_READ | PAGE_WRITE, + [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, + }, + [1] = { + [8] = PAGE_WRITE, + [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, + [10] = PAGE_READ, + [11] = PAGE_READ | PAGE_EXEC, + [12] = PAGE_READ, + [13] = PAGE_READ | PAGE_EXEC, + [14] = PAGE_READ | PAGE_WRITE, + [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, + }, + }; + unsigned rv; + unsigned type; + + type = mpu_attr_to_cpu_cache(attr); + rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> + XTENSA_MPU_ACC_RIGHTS_SHIFT]; + + if (type & XTENSA_MPU_TYPE_CPU_CACHE) { + rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; + } else { + rv |= PAGE_CACHE_BYPASS; + } + return rv; +} + +static bool is_access_granted(unsigned access, int is_write) +{ + switch (is_write) { + case 0: + return access & PAGE_READ; + + case 1: + return access & PAGE_WRITE; + + case 2: + return access & PAGE_EXEC; + + default: + return 0; + } +} + +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); + +static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access, bool may_lookup_pt) +{ + bool dtlb = is_write != 2; + uint32_t wi; + uint32_t ei; + uint8_t ring; + uint32_t vpn; + uint32_t pte; + const xtensa_tlb_entry *entry = NULL; + xtensa_tlb_entry tmp_entry; + int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); + + if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && + may_lookup_pt && get_pte(env, vaddr, &pte)) { + ring = (pte >> 4) & 0x3; + wi = 0; + xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); + + if (update_tlb) { + wi = ++env->autorefill_idx & 0x3; + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); + env->sregs[EXCVADDR] = vaddr; + qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", + __func__, vaddr, vpn, pte); + } else { + xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); + entry = &tmp_entry; + } + ret = 0; + } + if (ret != 0) { + return ret; + } + + if (entry == NULL) { + entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); + } + + if (ring < mmu_idx) { + return dtlb ? + LOAD_STORE_PRIVILEGE_CAUSE : + INST_FETCH_PRIVILEGE_CAUSE; + } + + *access = mmu_attr_to_access(entry->attr) & + ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); + if (!is_access_granted(*access, is_write)) { + return dtlb ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + + *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); + *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; + + return 0; +} + +static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) +{ + CPUState *cs = env_cpu(env); + uint32_t paddr; + uint32_t page_size; + unsigned access; + uint32_t pt_vaddr = + (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; + int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, + &paddr, &page_size, &access, false); + + if (ret == 0) { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", + __func__, vaddr, pt_vaddr, paddr); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", + __func__, vaddr, pt_vaddr, ret); + } + + if (ret == 0) { + MemTxResult result; + + *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, + &result); + if (result != MEMTX_OK) { + qemu_log_mask(CPU_LOG_MMU, + "%s: couldn't load PTE: transaction failed (%u)\n", + __func__, (unsigned)result); + ret = 1; + } + } + return ret == 0; +} + +static int get_physical_addr_region(CPUXtensaState *env, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + bool dtlb = is_write != 2; + uint32_t wi = 0; + uint32_t ei = (vaddr >> 29) & 0x7; + const xtensa_tlb_entry *entry = + xtensa_tlb_get_entry(env, dtlb, wi, ei); + + *access = region_attr_to_access(entry->attr); + if (!is_access_granted(*access, is_write)) { + return dtlb ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + + *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); + *page_size = ~REGION_PAGE_MASK + 1; + + return 0; +} + +int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, + uint32_t vaddr, unsigned *segment) +{ + unsigned nhits = 0; + unsigned i; + + for (i = 0; i < n; ++i) { + if (vaddr >= entry[i].vaddr && + (i == n - 1 || vaddr < entry[i + 1].vaddr)) { + if (nhits++) { + break; + } + *segment = i; + } + } + return nhits; +} + +static int get_physical_addr_mpu(CPUXtensaState *env, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + unsigned nhits; + unsigned segment; + uint32_t attr; + + nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, + vaddr, &segment); + if (nhits > 1) { + return is_write < 2 ? + LOAD_STORE_TLB_MULTI_HIT_CAUSE : + INST_TLB_MULTI_HIT_CAUSE; + } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { + attr = env->mpu_fg[segment].attr; + } else { + xtensa_mpu_lookup(env->config->mpu_bg, + env->config->n_mpu_bg_segments, + vaddr, &segment); + attr = env->config->mpu_bg[segment].attr; + } + + *access = mpu_attr_to_access(attr, mmu_idx); + if (!is_access_granted(*access, is_write)) { + return is_write < 2 ? + (is_write ? + STORE_PROHIBITED_CAUSE : + LOAD_PROHIBITED_CAUSE) : + INST_FETCH_PROHIBITED_CAUSE; + } + *paddr = vaddr; + *page_size = env->config->mpu_align; + return 0; +} + +/*! + * Convert virtual address to physical addr. + * MMU may issue pagewalk and change xtensa autorefill TLB way entry. + * + * \return 0 if ok, exception cause code otherwise + */ +int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, + uint32_t vaddr, int is_write, int mmu_idx, + uint32_t *paddr, uint32_t *page_size, + unsigned *access) +{ + if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { + return get_physical_addr_mmu(env, update_tlb, + vaddr, is_write, mmu_idx, paddr, + page_size, access, true); + } else if (xtensa_option_bits_enabled(env->config, + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | + XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { + return get_physical_addr_region(env, vaddr, is_write, mmu_idx, + paddr, page_size, access); + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { + return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, + paddr, page_size, access); + } else { + *paddr = vaddr; + *page_size = TARGET_PAGE_SIZE; + *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> + ((vaddr & 0xe0000000) >> 27)); + return 0; + } +} diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 31ee3fa957..8be8d79dcd 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -26,38 +26,12 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/qemu-print.h" #include "qemu/units.h" -#include "cpu.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" #include "exec/exec-all.h" - -#define XTENSA_MPU_SEGMENT_MASK 0x0000001f -#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 -#define XTENSA_MPU_ACC_RIGHTS_SHIFT 8 -#define XTENSA_MPU_MEM_TYPE_MASK 0x001ff000 -#define XTENSA_MPU_MEM_TYPE_SHIFT 12 -#define XTENSA_MPU_ATTR_MASK 0x001fff00 - -#define XTENSA_MPU_PROBE_B 0x40000000 -#define XTENSA_MPU_PROBE_V 0x80000000 - -#define XTENSA_MPU_SYSTEM_TYPE_DEVICE 0x0001 -#define XTENSA_MPU_SYSTEM_TYPE_NC 0x0002 -#define XTENSA_MPU_SYSTEM_TYPE_C 0x0003 -#define XTENSA_MPU_SYSTEM_TYPE_MASK 0x0003 - -#define XTENSA_MPU_TYPE_SYS_C 0x0010 -#define XTENSA_MPU_TYPE_SYS_W 0x0020 -#define XTENSA_MPU_TYPE_SYS_R 0x0040 -#define XTENSA_MPU_TYPE_CPU_C 0x0100 -#define XTENSA_MPU_TYPE_CPU_W 0x0200 -#define XTENSA_MPU_TYPE_CPU_R 0x0400 -#define XTENSA_MPU_TYPE_CPU_CACHE 0x0800 -#define XTENSA_MPU_TYPE_B 0x1000 -#define XTENSA_MPU_TYPE_INT 0x2000 +#include "cpu.h" +#include "mmu.h" void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr) { @@ -78,421 +52,6 @@ void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v) } } -static uint32_t get_page_size(const CPUXtensaState *env, - bool dtlb, uint32_t way) -{ - uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG]; - - switch (way) { - case 4: - return (tlbcfg >> 16) & 0x3; - - case 5: - return (tlbcfg >> 20) & 0x1; - - case 6: - return (tlbcfg >> 24) & 0x1; - - default: - return 0; - } -} - -/*! - * Get bit mask for the virtual address bits translated by the TLB way - */ -static uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, - bool dtlb, uint32_t way) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - bool varway56 = dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - switch (way) { - case 4: - return 0xfff00000 << get_page_size(env, dtlb, way) * 2; - - case 5: - if (varway56) { - return 0xf8000000 << get_page_size(env, dtlb, way); - } else { - return 0xf8000000; - } - - case 6: - if (varway56) { - return 0xf0000000 << (1 - get_page_size(env, dtlb, way)); - } else { - return 0xf0000000; - } - - default: - return 0xfffff000; - } - } else { - return REGION_PAGE_MASK; - } -} - -/*! - * Get bit mask for the 'VPN without index' field. - * See ISA, 4.6.5.6, data format for RxTLB0 - */ -static uint32_t xtensa_get_vpn_mask(const CPUXtensaState *env, bool dtlb, - uint32_t way) -{ - if (way < 4) { - bool is32 = (dtlb ? - env->config->dtlb.nrefillentries : - env->config->itlb.nrefillentries) == 32; - return is32 ? 0xffff8000 : 0xffffc000; - } else if (way == 4) { - return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2; - } else if (way <= 6) { - uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way); - bool varway56 = dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - if (varway56) { - return mask << (way == 5 ? 2 : 3); - } else { - return mask << 1; - } - } else { - return 0xfffff000; - } -} - -/*! - * Split virtual address into VPN (with index) and entry index - * for the given TLB way - */ -static void xtensa_split_tlb_entry_spec_way(const CPUXtensaState *env, - uint32_t v, - bool dtlb, uint32_t *vpn, - uint32_t wi, uint32_t *ei) -{ - bool varway56 = dtlb ? - env->config->dtlb.varway56 : - env->config->itlb.varway56; - - if (!dtlb) { - wi &= 7; - } - - if (wi < 4) { - bool is32 = (dtlb ? - env->config->dtlb.nrefillentries : - env->config->itlb.nrefillentries) == 32; - *ei = (v >> 12) & (is32 ? 0x7 : 0x3); - } else { - switch (wi) { - case 4: - { - uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2; - *ei = (v >> eibase) & 0x3; - } - break; - - case 5: - if (varway56) { - uint32_t eibase = 27 + get_page_size(env, dtlb, wi); - *ei = (v >> eibase) & 0x3; - } else { - *ei = (v >> 27) & 0x1; - } - break; - - case 6: - if (varway56) { - uint32_t eibase = 29 - get_page_size(env, dtlb, wi); - *ei = (v >> eibase) & 0x7; - } else { - *ei = (v >> 28) & 0x1; - } - break; - - default: - *ei = 0; - break; - } - } - *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi); -} - -/*! - * Split TLB address into TLB way, entry index and VPN (with index). - * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format - */ -static bool xtensa_split_tlb_entry_spec(CPUXtensaState *env, - uint32_t v, bool dtlb, - uint32_t *vpn, uint32_t *wi, - uint32_t *ei) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - *wi = v & (dtlb ? 0xf : 0x7); - if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { - xtensa_split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); - return true; - } else { - return false; - } - } else { - *vpn = v & REGION_PAGE_MASK; - *wi = 0; - *ei = (v >> 29) & 0x7; - return true; - } -} - -static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, - unsigned wi, unsigned ei) -{ - const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; - - assert(wi < tlb->nways && ei < tlb->way_size[wi]); - return dtlb ? - env->dtlb[wi] + ei : - env->itlb[wi] + ei; -} - -static xtensa_tlb_entry *xtensa_get_tlb_entry(CPUXtensaState *env, - uint32_t v, bool dtlb, uint32_t *pwi) -{ - uint32_t vpn; - uint32_t wi; - uint32_t ei; - - if (xtensa_split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { - if (pwi) { - *pwi = wi; - } - return xtensa_tlb_get_entry(env, dtlb, wi, ei); - } else { - return NULL; - } -} - -static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, - xtensa_tlb_entry *entry, bool dtlb, - unsigned wi, unsigned ei, uint32_t vpn, - uint32_t pte) -{ - entry->vaddr = vpn; - entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi); - entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff; - entry->attr = pte & 0xf; -} - -static void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb, - unsigned wi, unsigned ei, - uint32_t vpn, uint32_t pte) -{ - CPUState *cs = env_cpu(env); - xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); - - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - if (entry->variable) { - if (entry->asid) { - tlb_flush_page(cs, entry->vaddr); - } - xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte); - tlb_flush_page(cs, entry->vaddr); - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s %d, %d, %d trying to set immutable entry\n", - __func__, dtlb, wi, ei); - } - } else { - tlb_flush_page(cs, entry->vaddr); - if (xtensa_option_enabled(env->config, - XTENSA_OPTION_REGION_TRANSLATION)) { - entry->paddr = pte & REGION_PAGE_MASK; - } - entry->attr = pte & 0xf; - } -} - -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - XtensaCPU *cpu = XTENSA_CPU(cs); - uint32_t paddr; - uint32_t page_size; - unsigned access; - - if (xtensa_get_physical_addr(&cpu->env, false, addr, 0, 0, - &paddr, &page_size, &access) == 0) { - return paddr; - } - if (xtensa_get_physical_addr(&cpu->env, false, addr, 2, 0, - &paddr, &page_size, &access) == 0) { - return paddr; - } - return ~0; -} - -static void reset_tlb_mmu_all_ways(CPUXtensaState *env, - const xtensa_tlb *tlb, - xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - unsigned wi, ei; - - for (wi = 0; wi < tlb->nways; ++wi) { - for (ei = 0; ei < tlb->way_size[wi]; ++ei) { - entry[wi][ei].asid = 0; - entry[wi][ei].variable = true; - } - } -} - -static void reset_tlb_mmu_ways56(CPUXtensaState *env, - const xtensa_tlb *tlb, - xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - if (!tlb->varway56) { - static const xtensa_tlb_entry way5[] = { - { - .vaddr = 0xd0000000, - .paddr = 0, - .asid = 1, - .attr = 7, - .variable = false, - }, { - .vaddr = 0xd8000000, - .paddr = 0, - .asid = 1, - .attr = 3, - .variable = false, - } - }; - static const xtensa_tlb_entry way6[] = { - { - .vaddr = 0xe0000000, - .paddr = 0xf0000000, - .asid = 1, - .attr = 7, - .variable = false, - }, { - .vaddr = 0xf0000000, - .paddr = 0xf0000000, - .asid = 1, - .attr = 3, - .variable = false, - } - }; - memcpy(entry[5], way5, sizeof(way5)); - memcpy(entry[6], way6, sizeof(way6)); - } else { - uint32_t ei; - for (ei = 0; ei < 8; ++ei) { - entry[6][ei].vaddr = ei << 29; - entry[6][ei].paddr = ei << 29; - entry[6][ei].asid = 1; - entry[6][ei].attr = 3; - } - } -} - -static void reset_tlb_region_way0(CPUXtensaState *env, - xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) -{ - unsigned ei; - - for (ei = 0; ei < 8; ++ei) { - entry[0][ei].vaddr = ei << 29; - entry[0][ei].paddr = ei << 29; - entry[0][ei].asid = 1; - entry[0][ei].attr = 2; - entry[0][ei].variable = true; - } -} - -void xtensa_reset_mmu(CPUXtensaState *env) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - env->sregs[RASID] = 0x04030201; - env->sregs[ITLBCFG] = 0; - env->sregs[DTLBCFG] = 0; - env->autorefill_idx = 0; - reset_tlb_mmu_all_ways(env, &env->config->itlb, env->itlb); - reset_tlb_mmu_all_ways(env, &env->config->dtlb, env->dtlb); - reset_tlb_mmu_ways56(env, &env->config->itlb, env->itlb); - reset_tlb_mmu_ways56(env, &env->config->dtlb, env->dtlb); - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { - unsigned i; - - env->sregs[MPUENB] = 0; - env->sregs[MPUCFG] = env->config->n_mpu_fg_segments; - env->sregs[CACHEADRDIS] = 0; - assert(env->config->n_mpu_bg_segments > 0 && - env->config->mpu_bg[0].vaddr == 0); - for (i = 1; i < env->config->n_mpu_bg_segments; ++i) { - assert(env->config->mpu_bg[i].vaddr >= - env->config->mpu_bg[i - 1].vaddr); - } - } else { - env->sregs[CACHEATTR] = 0x22222222; - reset_tlb_region_way0(env, env->itlb); - reset_tlb_region_way0(env, env->dtlb); - } -} - -static unsigned get_ring(const CPUXtensaState *env, uint8_t asid) -{ - unsigned i; - for (i = 0; i < 4; ++i) { - if (((env->sregs[RASID] >> i * 8) & 0xff) == asid) { - return i; - } - } - return 0xff; -} - -/*! - * Lookup xtensa TLB for the given virtual address. - * See ISA, 4.6.2.2 - * - * \param pwi: [out] way index - * \param pei: [out] entry index - * \param pring: [out] access ring - * \return 0 if ok, exception cause code otherwise - */ -static int xtensa_tlb_lookup(const CPUXtensaState *env, - uint32_t addr, bool dtlb, - uint32_t *pwi, uint32_t *pei, uint8_t *pring) -{ - const xtensa_tlb *tlb = dtlb ? - &env->config->dtlb : &env->config->itlb; - const xtensa_tlb_entry (*entry)[MAX_TLB_WAY_SIZE] = dtlb ? - env->dtlb : env->itlb; - - int nhits = 0; - unsigned wi; - - for (wi = 0; wi < tlb->nways; ++wi) { - uint32_t vpn; - uint32_t ei; - xtensa_split_tlb_entry_spec_way(env, addr, dtlb, &vpn, wi, &ei); - if (entry[wi][ei].vaddr == vpn && entry[wi][ei].asid) { - unsigned ring = get_ring(env, entry[wi][ei].asid); - if (ring < 4) { - if (++nhits > 1) { - return dtlb ? - LOAD_STORE_TLB_MULTI_HIT_CAUSE : - INST_TLB_MULTI_HIT_CAUSE; - } - *pwi = wi; - *pei = ei; - *pring = ring; - } - } - } - return nhits ? 0 : - (dtlb ? LOAD_STORE_TLB_MISS_CAUSE : INST_TLB_MISS_CAUSE); -} - uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { @@ -569,384 +128,6 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) } } -/*! - * Convert MMU ATTR to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, 4.6.5.10 - */ -static unsigned mmu_attr_to_access(uint32_t attr) -{ - unsigned access = 0; - - if (attr < 12) { - access |= PAGE_READ; - if (attr & 0x1) { - access |= PAGE_EXEC; - } - if (attr & 0x2) { - access |= PAGE_WRITE; - } - - switch (attr & 0xc) { - case 0: - access |= PAGE_CACHE_BYPASS; - break; - - case 4: - access |= PAGE_CACHE_WB; - break; - - case 8: - access |= PAGE_CACHE_WT; - break; - } - } else if (attr == 13) { - access |= PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE; - } - return access; -} - -/*! - * Convert region protection ATTR to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, 4.6.3.3 - */ -static unsigned region_attr_to_access(uint32_t attr) -{ - static const unsigned access[16] = { - [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, - [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, - [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, - [3] = PAGE_EXEC | PAGE_CACHE_WB, - [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [5] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, - }; - - return access[attr & 0xf]; -} - -/*! - * Convert cacheattr to PAGE_{READ,WRITE,EXEC} mask. - * See ISA, A.2.14 The Cache Attribute Register - */ -static unsigned cacheattr_attr_to_access(uint32_t attr) -{ - static const unsigned access[16] = { - [0] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_WT, - [1] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WT, - [2] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_BYPASS, - [3] = PAGE_EXEC | PAGE_CACHE_WB, - [4] = PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_CACHE_WB, - [14] = PAGE_READ | PAGE_WRITE | PAGE_CACHE_ISOLATE, - }; - - return access[attr & 0xf]; -} - -struct attr_pattern { - uint32_t mask; - uint32_t value; -}; - -static int attr_pattern_match(uint32_t attr, - const struct attr_pattern *pattern, - size_t n) -{ - size_t i; - - for (i = 0; i < n; ++i) { - if ((attr & pattern[i].mask) == pattern[i].value) { - return 1; - } - } - return 0; -} - -static unsigned mpu_attr_to_cpu_cache(uint32_t attr) -{ - static const struct attr_pattern cpu_c[] = { - { .mask = 0x18f, .value = 0x089 }, - { .mask = 0x188, .value = 0x080 }, - { .mask = 0x180, .value = 0x180 }, - }; - - unsigned type = 0; - - if (attr_pattern_match(attr, cpu_c, ARRAY_SIZE(cpu_c))) { - type |= XTENSA_MPU_TYPE_CPU_CACHE; - if (attr & 0x10) { - type |= XTENSA_MPU_TYPE_CPU_C; - } - if (attr & 0x20) { - type |= XTENSA_MPU_TYPE_CPU_W; - } - if (attr & 0x40) { - type |= XTENSA_MPU_TYPE_CPU_R; - } - } - return type; -} - -static unsigned mpu_attr_to_type(uint32_t attr) -{ - static const struct attr_pattern device_type[] = { - { .mask = 0x1f6, .value = 0x000 }, - { .mask = 0x1f6, .value = 0x006 }, - }; - static const struct attr_pattern sys_nc_type[] = { - { .mask = 0x1fe, .value = 0x018 }, - { .mask = 0x1fe, .value = 0x01e }, - { .mask = 0x18f, .value = 0x089 }, - }; - static const struct attr_pattern sys_c_type[] = { - { .mask = 0x1f8, .value = 0x010 }, - { .mask = 0x188, .value = 0x080 }, - { .mask = 0x1f0, .value = 0x030 }, - { .mask = 0x180, .value = 0x180 }, - }; - static const struct attr_pattern b[] = { - { .mask = 0x1f7, .value = 0x001 }, - { .mask = 0x1f7, .value = 0x007 }, - { .mask = 0x1ff, .value = 0x019 }, - { .mask = 0x1ff, .value = 0x01f }, - }; - - unsigned type = 0; - - attr = (attr & XTENSA_MPU_MEM_TYPE_MASK) >> XTENSA_MPU_MEM_TYPE_SHIFT; - if (attr_pattern_match(attr, device_type, ARRAY_SIZE(device_type))) { - type |= XTENSA_MPU_SYSTEM_TYPE_DEVICE; - if (attr & 0x80) { - type |= XTENSA_MPU_TYPE_INT; - } - } - if (attr_pattern_match(attr, sys_nc_type, ARRAY_SIZE(sys_nc_type))) { - type |= XTENSA_MPU_SYSTEM_TYPE_NC; - } - if (attr_pattern_match(attr, sys_c_type, ARRAY_SIZE(sys_c_type))) { - type |= XTENSA_MPU_SYSTEM_TYPE_C; - if (attr & 0x1) { - type |= XTENSA_MPU_TYPE_SYS_C; - } - if (attr & 0x2) { - type |= XTENSA_MPU_TYPE_SYS_W; - } - if (attr & 0x4) { - type |= XTENSA_MPU_TYPE_SYS_R; - } - } - if (attr_pattern_match(attr, b, ARRAY_SIZE(b))) { - type |= XTENSA_MPU_TYPE_B; - } - type |= mpu_attr_to_cpu_cache(attr); - - return type; -} - -static unsigned mpu_attr_to_access(uint32_t attr, unsigned ring) -{ - static const unsigned access[2][16] = { - [0] = { - [4] = PAGE_READ, - [5] = PAGE_READ | PAGE_EXEC, - [6] = PAGE_READ | PAGE_WRITE, - [7] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, - [8] = PAGE_WRITE, - [9] = PAGE_READ | PAGE_WRITE, - [10] = PAGE_READ | PAGE_WRITE, - [11] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, - [12] = PAGE_READ, - [13] = PAGE_READ | PAGE_EXEC, - [14] = PAGE_READ | PAGE_WRITE, - [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, - }, - [1] = { - [8] = PAGE_WRITE, - [9] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, - [10] = PAGE_READ, - [11] = PAGE_READ | PAGE_EXEC, - [12] = PAGE_READ, - [13] = PAGE_READ | PAGE_EXEC, - [14] = PAGE_READ | PAGE_WRITE, - [15] = PAGE_READ | PAGE_WRITE | PAGE_EXEC, - }, - }; - unsigned rv; - unsigned type; - - type = mpu_attr_to_cpu_cache(attr); - rv = access[ring != 0][(attr & XTENSA_MPU_ACC_RIGHTS_MASK) >> - XTENSA_MPU_ACC_RIGHTS_SHIFT]; - - if (type & XTENSA_MPU_TYPE_CPU_CACHE) { - rv |= (type & XTENSA_MPU_TYPE_CPU_C) ? PAGE_CACHE_WB : PAGE_CACHE_WT; - } else { - rv |= PAGE_CACHE_BYPASS; - } - return rv; -} - -static bool is_access_granted(unsigned access, int is_write) -{ - switch (is_write) { - case 0: - return access & PAGE_READ; - - case 1: - return access & PAGE_WRITE; - - case 2: - return access & PAGE_EXEC; - - default: - return 0; - } -} - -static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte); - -static int get_physical_addr_mmu(CPUXtensaState *env, bool update_tlb, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, - unsigned *access, bool may_lookup_pt) -{ - bool dtlb = is_write != 2; - uint32_t wi; - uint32_t ei; - uint8_t ring; - uint32_t vpn; - uint32_t pte; - const xtensa_tlb_entry *entry = NULL; - xtensa_tlb_entry tmp_entry; - int ret = xtensa_tlb_lookup(env, vaddr, dtlb, &wi, &ei, &ring); - - if ((ret == INST_TLB_MISS_CAUSE || ret == LOAD_STORE_TLB_MISS_CAUSE) && - may_lookup_pt && get_pte(env, vaddr, &pte)) { - ring = (pte >> 4) & 0x3; - wi = 0; - xtensa_split_tlb_entry_spec_way(env, vaddr, dtlb, &vpn, wi, &ei); - - if (update_tlb) { - wi = ++env->autorefill_idx & 0x3; - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, pte); - env->sregs[EXCVADDR] = vaddr; - qemu_log_mask(CPU_LOG_MMU, "%s: autorefill(%08x): %08x -> %08x\n", - __func__, vaddr, vpn, pte); - } else { - xtensa_tlb_set_entry_mmu(env, &tmp_entry, dtlb, wi, ei, vpn, pte); - entry = &tmp_entry; - } - ret = 0; - } - if (ret != 0) { - return ret; - } - - if (entry == NULL) { - entry = xtensa_tlb_get_entry(env, dtlb, wi, ei); - } - - if (ring < mmu_idx) { - return dtlb ? - LOAD_STORE_PRIVILEGE_CAUSE : - INST_FETCH_PRIVILEGE_CAUSE; - } - - *access = mmu_attr_to_access(entry->attr) & - ~(dtlb ? PAGE_EXEC : PAGE_READ | PAGE_WRITE); - if (!is_access_granted(*access, is_write)) { - return dtlb ? - (is_write ? - STORE_PROHIBITED_CAUSE : - LOAD_PROHIBITED_CAUSE) : - INST_FETCH_PROHIBITED_CAUSE; - } - - *paddr = entry->paddr | (vaddr & ~xtensa_tlb_get_addr_mask(env, dtlb, wi)); - *page_size = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; - - return 0; -} - -static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte) -{ - CPUState *cs = env_cpu(env); - uint32_t paddr; - uint32_t page_size; - unsigned access; - uint32_t pt_vaddr = - (env->sregs[PTEVADDR] | (vaddr >> 10)) & 0xfffffffc; - int ret = get_physical_addr_mmu(env, false, pt_vaddr, 0, 0, - &paddr, &page_size, &access, false); - - if (ret == 0) { - qemu_log_mask(CPU_LOG_MMU, - "%s: autorefill(%08x): PTE va = %08x, pa = %08x\n", - __func__, vaddr, pt_vaddr, paddr); - } else { - qemu_log_mask(CPU_LOG_MMU, - "%s: autorefill(%08x): PTE va = %08x, failed (%d)\n", - __func__, vaddr, pt_vaddr, ret); - } - - if (ret == 0) { - MemTxResult result; - - *pte = address_space_ldl(cs->as, paddr, MEMTXATTRS_UNSPECIFIED, - &result); - if (result != MEMTX_OK) { - qemu_log_mask(CPU_LOG_MMU, - "%s: couldn't load PTE: transaction failed (%u)\n", - __func__, (unsigned)result); - ret = 1; - } - } - return ret == 0; -} - -static int get_physical_addr_region(CPUXtensaState *env, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, - unsigned *access) -{ - bool dtlb = is_write != 2; - uint32_t wi = 0; - uint32_t ei = (vaddr >> 29) & 0x7; - const xtensa_tlb_entry *entry = - xtensa_tlb_get_entry(env, dtlb, wi, ei); - - *access = region_attr_to_access(entry->attr); - if (!is_access_granted(*access, is_write)) { - return dtlb ? - (is_write ? - STORE_PROHIBITED_CAUSE : - LOAD_PROHIBITED_CAUSE) : - INST_FETCH_PROHIBITED_CAUSE; - } - - *paddr = entry->paddr | (vaddr & ~REGION_PAGE_MASK); - *page_size = ~REGION_PAGE_MASK + 1; - - return 0; -} - -static int xtensa_mpu_lookup(const xtensa_mpu_entry *entry, unsigned n, - uint32_t vaddr, unsigned *segment) -{ - unsigned nhits = 0; - unsigned i; - - for (i = 0; i < n; ++i) { - if (vaddr >= entry[i].vaddr && - (i == n - 1 || vaddr < entry[i + 1].vaddr)) { - if (nhits++) { - break; - } - *segment = i; - } - } - return nhits; -} - void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v) { v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1; @@ -1013,75 +194,6 @@ uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) } } -static int get_physical_addr_mpu(CPUXtensaState *env, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, - unsigned *access) -{ - unsigned nhits; - unsigned segment; - uint32_t attr; - - nhits = xtensa_mpu_lookup(env->mpu_fg, env->config->n_mpu_fg_segments, - vaddr, &segment); - if (nhits > 1) { - return is_write < 2 ? - LOAD_STORE_TLB_MULTI_HIT_CAUSE : - INST_TLB_MULTI_HIT_CAUSE; - } else if (nhits == 1 && (env->sregs[MPUENB] & (1u << segment))) { - attr = env->mpu_fg[segment].attr; - } else { - xtensa_mpu_lookup(env->config->mpu_bg, - env->config->n_mpu_bg_segments, - vaddr, &segment); - attr = env->config->mpu_bg[segment].attr; - } - - *access = mpu_attr_to_access(attr, mmu_idx); - if (!is_access_granted(*access, is_write)) { - return is_write < 2 ? - (is_write ? - STORE_PROHIBITED_CAUSE : - LOAD_PROHIBITED_CAUSE) : - INST_FETCH_PROHIBITED_CAUSE; - } - *paddr = vaddr; - *page_size = env->config->mpu_align; - return 0; -} - -/*! - * Convert virtual address to physical addr. - * MMU may issue pagewalk and change xtensa autorefill TLB way entry. - * - * \return 0 if ok, exception cause code otherwise - */ -int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, - uint32_t vaddr, int is_write, int mmu_idx, - uint32_t *paddr, uint32_t *page_size, - unsigned *access) -{ - if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { - return get_physical_addr_mmu(env, update_tlb, - vaddr, is_write, mmu_idx, paddr, - page_size, access, true); - } else if (xtensa_option_bits_enabled(env->config, - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION))) { - return get_physical_addr_region(env, vaddr, is_write, mmu_idx, - paddr, page_size, access); - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { - return get_physical_addr_mpu(env, vaddr, is_write, mmu_idx, - paddr, page_size, access); - } else { - *paddr = vaddr; - *page_size = TARGET_PAGE_SIZE; - *access = cacheattr_attr_to_access(env->sregs[CACHEATTR] >> - ((vaddr & 0xe0000000) >> 27)); - return 0; - } -} - static void dump_tlb(CPUXtensaState *env, bool dtlb) { unsigned wi, ei; diff --git a/target/xtensa/meson.build b/target/xtensa/meson.build index f8d60101e3..46010c35c4 100644 --- a/target/xtensa/meson.build +++ b/target/xtensa/meson.build @@ -18,6 +18,7 @@ xtensa_ss.add(files( xtensa_system_ss = ss.source_set() xtensa_system_ss.add(files( 'dbg_helper.c', + 'mmu.c', 'mmu_helper.c', 'monitor.c', 'xtensa-semi.c', From patchwork Thu Mar 21 15:48:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D518C54E68 for ; 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Thu, 21 Mar 2024 08:51:03 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id c5-20020a170906694500b00a4131367204sm55036ejs.80.2024.03.21.08.51.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:51:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 19/21] target/xtensa: Simplify dump_mpu() and dump_tlb() Date: Thu, 21 Mar 2024 16:48:35 +0100 Message-ID: <20240321154838.95771-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Remove few qemu_printf() calls in xtensa_dump_mmu() by slightly reworking dump_mpu() and dump_tlb(). Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/mmu_helper.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 8be8d79dcd..3b4f53feb0 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -203,6 +203,7 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb) xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? mmu_attr_to_access : region_attr_to_access; + qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB"); for (wi = 0; wi < conf->nways; ++wi) { uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; const char *sz_text; @@ -252,11 +253,12 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb) } } -static void dump_mpu(CPUXtensaState *env, +static void dump_mpu(CPUXtensaState *env, const char *map_desc, const xtensa_mpu_entry *entry, unsigned n) { unsigned i; + qemu_printf("%s map:\n", map_desc); qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" "\t%s ---------- ---------- ----- ----- ------------- ---------\n", env ? "En" : " ", @@ -316,15 +318,15 @@ void xtensa_dump_mmu(CPUXtensaState *env) XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { - qemu_printf("ITLB:\n"); dump_tlb(env, false); - qemu_printf("\nDTLB:\n"); + qemu_printf("\n"); dump_tlb(env, true); } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { - qemu_printf("Foreground map:\n"); - dump_mpu(env, env->mpu_fg, env->config->n_mpu_fg_segments); - qemu_printf("\nBackground map:\n"); - dump_mpu(NULL, env->config->mpu_bg, env->config->n_mpu_bg_segments); + dump_mpu(env, "Foreground", + env->mpu_fg, env->config->n_mpu_fg_segments); + qemu_printf("\n"); + dump_mpu(NULL, "Background", + env->config->mpu_bg, env->config->n_mpu_bg_segments); } else { qemu_printf("No TLB for this CPU core\n"); } From patchwork Thu Mar 21 15:48:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13599039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DA7CCCD11C2 for ; Thu, 21 Mar 2024 15:53:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnKhz-00037x-FX; Thu, 21 Mar 2024 11:51:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnKhS-0001Yy-UM for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:51:28 -0400 Received: from mail-lj1-x234.google.com ([2a00:1450:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnKhM-0002Eh-2A for qemu-devel@nongnu.org; Thu, 21 Mar 2024 11:51:23 -0400 Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2d28051376eso23474901fa.0 for ; Thu, 21 Mar 2024 08:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711036271; x=1711641071; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8h5t/FA85YtkYkt5jLzh3FCMifcHYByW2n7FfuuxlSE=; b=NNYMF4P7+0rvbRQgPuHTkgYYjjr3wzT8Pwm5/SX0I5LzCQUzHnvQRSelseRfjOM9rR YZy2egRi6XFPab6IxMJ+G+SuFdRX650D42N+VpwXspDOZ5EaPi7slK9K7AMjaivNyANd Ut1y+Oy4NpXutPUUh8S3Zm03LBUGEHUXk54l3p3eIb3nk1cywN4QTYStAhtCip0mFxfi Qm9FAIUD7kwDZMfZ5ejDLVWhG57ryZBOeFNV0g9ZLZEjn2X+lJO1D6NOIvltQz0MUlNy 6I0QS8nNKR3FEAUZWy2YGQDpyqAo5IyJcGtGOHdlzRtG46/ExozC6CEN5aMbKvVjvtoa aEQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711036271; x=1711641071; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8h5t/FA85YtkYkt5jLzh3FCMifcHYByW2n7FfuuxlSE=; b=TA9baR6rnEgrR/uegMHNecd/Zf5rleyiIklaKFK4OVOvmTJf3mfA6h/3m2RuBz/g3u JLwX0NAkc5HkHCT844BT48LU4kdLnh095pLoyHxz5n80bqbPKDiqQqV0CWwnqgA30+oM BdX+926TpFCbFeNEae+WabxjRhaFZMgmWJAeDK/QMXwEBhez7NpjdEhapJCHVXa5J0Md ZzRB9mEMtfEmYLYF0JD0TB4qAZKcjvhKGXoNz5XwXAoeLuIilZPxc5WzLExTUflL/2W5 gf9HTbFR2MapviPeFHjhOmGhUoZ4nNyr7HSTr4JEt3omEO2HtZ8iaE6xmhlkUreQpBMC lPzg== X-Gm-Message-State: AOJu0YzrvYpWjkjT/YmYgt3fvK34YkROPgirKXV13uE/OQ69zhkrfoE9 083TuL43oxFs97teh8yq5kIWQ/G3QNjyyR7Skunw+1M386/g02AM+DtTpVau3TuhO5GDhcYbl0K ggKw= X-Google-Smtp-Source: AGHT+IHBplfjpFB1vOCGbIjl6ktfDRjEjyU1MULPF6t37s/XrZTWksZKQ9OFd/03Vz5z4YtjEImoig== X-Received: by 2002:a05:651c:87:b0:2d4:714b:4c5d with SMTP id 7-20020a05651c008700b002d4714b4c5dmr2030881ljq.44.1711036270926; Thu, 21 Mar 2024 08:51:10 -0700 (PDT) Received: from m1x-phil.lan ([176.187.206.222]) by smtp.gmail.com with ESMTPSA id e7-20020a170906314700b00a46e3669dd3sm48752eje.128.2024.03.21.08.51.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 21 Mar 2024 08:51:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Artyom Tarasenko , Chris Wulff , "Edgar E. Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 20/21] target/xtensa: Move monitor commands to monitor.c Date: Thu, 21 Mar 2024 16:48:36 +0100 Message-ID: <20240321154838.95771-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::234; envelope-from=philmd@linaro.org; helo=mail-lj1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/mmu_helper.c | 140 ------------------------------------ target/xtensa/monitor.c | 144 ++++++++++++++++++++++++++++++++++++- 2 files changed, 143 insertions(+), 141 deletions(-) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 3b4f53feb0..892730f0f0 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -26,8 +26,6 @@ */ #include "qemu/osdep.h" -#include "qemu/qemu-print.h" -#include "qemu/units.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "cpu.h" @@ -193,141 +191,3 @@ uint32_t HELPER(pptlb)(CPUXtensaState *env, uint32_t v) return env->config->mpu_bg[bg_segment].attr | segment; } } - -static void dump_tlb(CPUXtensaState *env, bool dtlb) -{ - unsigned wi, ei; - const xtensa_tlb *conf = - dtlb ? &env->config->dtlb : &env->config->itlb; - unsigned (*attr_to_access)(uint32_t) = - xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? - mmu_attr_to_access : region_attr_to_access; - - qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB"); - for (wi = 0; wi < conf->nways; ++wi) { - uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; - const char *sz_text; - bool print_header = true; - - if (sz >= 0x100000) { - sz /= MiB; - sz_text = "MB"; - } else { - sz /= KiB; - sz_text = "KB"; - } - - for (ei = 0; ei < conf->way_size[wi]; ++ei) { - const xtensa_tlb_entry *entry = - xtensa_tlb_get_entry(env, dtlb, wi, ei); - - if (entry->asid) { - static const char * const cache_text[8] = { - [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", - [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", - [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", - [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", - }; - unsigned access = attr_to_access(entry->attr); - unsigned cache_idx = (access & PAGE_CACHE_MASK) >> - PAGE_CACHE_SHIFT; - - if (print_header) { - print_header = false; - qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); - qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" - "\t---------- ---------- ---- ---- --- -------\n"); - } - qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", - entry->vaddr, - entry->paddr, - entry->asid, - entry->attr, - (access & PAGE_READ) ? 'R' : '-', - (access & PAGE_WRITE) ? 'W' : '-', - (access & PAGE_EXEC) ? 'X' : '-', - cache_text[cache_idx] ? - cache_text[cache_idx] : "Invalid"); - } - } - } -} - -static void dump_mpu(CPUXtensaState *env, const char *map_desc, - const xtensa_mpu_entry *entry, unsigned n) -{ - unsigned i; - - qemu_printf("%s map:\n", map_desc); - qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" - "\t%s ---------- ---------- ----- ----- ------------- ---------\n", - env ? "En" : " ", - env ? "--" : " "); - - for (i = 0; i < n; ++i) { - uint32_t attr = entry[i].attr; - unsigned access0 = mpu_attr_to_access(attr, 0); - unsigned access1 = mpu_attr_to_access(attr, 1); - unsigned type = mpu_attr_to_type(attr); - char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; - - qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", - env ? - ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', - entry[i].vaddr, attr, - (access0 & PAGE_READ) ? 'R' : '-', - (access0 & PAGE_WRITE) ? 'W' : '-', - (access0 & PAGE_EXEC) ? 'X' : '-', - (access1 & PAGE_READ) ? 'R' : '-', - (access1 & PAGE_WRITE) ? 'W' : '-', - (access1 & PAGE_EXEC) ? 'X' : '-'); - - switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { - case XTENSA_MPU_SYSTEM_TYPE_DEVICE: - qemu_printf("Device %cB %3s\n", - (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', - (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); - break; - case XTENSA_MPU_SYSTEM_TYPE_NC: - qemu_printf("Sys NC %cB %c%c%c\n", - (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', - (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); - break; - case XTENSA_MPU_SYSTEM_TYPE_C: - qemu_printf("Sys C %c%c%c %c%c%c\n", - (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', - (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', - (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', - (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); - break; - default: - qemu_printf("Unknown\n"); - break; - } - } -} - -void xtensa_dump_mmu(CPUXtensaState *env) -{ - if (xtensa_option_bits_enabled(env->config, - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | - XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { - - dump_tlb(env, false); - qemu_printf("\n"); - dump_tlb(env, true); - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { - dump_mpu(env, "Foreground", - env->mpu_fg, env->config->n_mpu_fg_segments); - qemu_printf("\n"); - dump_mpu(NULL, "Background", - env->config->mpu_bg, env->config->n_mpu_bg_segments); - } else { - qemu_printf("No TLB for this CPU core\n"); - } -} diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c index ce1b791a5c..9ba068d624 100644 --- a/target/xtensa/monitor.c +++ b/target/xtensa/monitor.c @@ -22,10 +22,152 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "cpu.h" +#include "qemu/qemu-print.h" +#include "qemu/units.h" #include "monitor/monitor.h" #include "monitor/hmp-target.h" #include "monitor/hmp.h" +#include "cpu.h" +#include "mmu.h" + + +static void dump_tlb(CPUXtensaState *env, bool dtlb) +{ + unsigned wi, ei; + const xtensa_tlb *conf = + dtlb ? &env->config->dtlb : &env->config->itlb; + unsigned (*attr_to_access)(uint32_t) = + xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? + mmu_attr_to_access : region_attr_to_access; + + qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB"); + for (wi = 0; wi < conf->nways; ++wi) { + uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; + const char *sz_text; + bool print_header = true; + + if (sz >= 0x100000) { + sz /= MiB; + sz_text = "MB"; + } else { + sz /= KiB; + sz_text = "KB"; + } + + for (ei = 0; ei < conf->way_size[wi]; ++ei) { + const xtensa_tlb_entry *entry = + xtensa_tlb_get_entry(env, dtlb, wi, ei); + + if (entry->asid) { + static const char * const cache_text[8] = { + [PAGE_CACHE_BYPASS >> PAGE_CACHE_SHIFT] = "Bypass", + [PAGE_CACHE_WT >> PAGE_CACHE_SHIFT] = "WT", + [PAGE_CACHE_WB >> PAGE_CACHE_SHIFT] = "WB", + [PAGE_CACHE_ISOLATE >> PAGE_CACHE_SHIFT] = "Isolate", + }; + unsigned access = attr_to_access(entry->attr); + unsigned cache_idx = (access & PAGE_CACHE_MASK) >> + PAGE_CACHE_SHIFT; + + if (print_header) { + print_header = false; + qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); + qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" + "\t---------- ---------- ---- ---- --- -------\n"); + } + qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", + entry->vaddr, + entry->paddr, + entry->asid, + entry->attr, + (access & PAGE_READ) ? 'R' : '-', + (access & PAGE_WRITE) ? 'W' : '-', + (access & PAGE_EXEC) ? 'X' : '-', + cache_text[cache_idx] ? + cache_text[cache_idx] : "Invalid"); + } + } + } +} + +static void dump_mpu(CPUXtensaState *env, const char *map_desc, + const xtensa_mpu_entry *entry, unsigned n) +{ + unsigned i; + + qemu_printf("%s map:\n", map_desc); + qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" + "\t%s ---------- ---------- ----- ----- ------------- ---------\n", + env ? "En" : " ", + env ? "--" : " "); + + for (i = 0; i < n; ++i) { + uint32_t attr = entry[i].attr; + unsigned access0 = mpu_attr_to_access(attr, 0); + unsigned access1 = mpu_attr_to_access(attr, 1); + unsigned type = mpu_attr_to_type(attr); + char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; + + qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", + env ? + ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', + entry[i].vaddr, attr, + (access0 & PAGE_READ) ? 'R' : '-', + (access0 & PAGE_WRITE) ? 'W' : '-', + (access0 & PAGE_EXEC) ? 'X' : '-', + (access1 & PAGE_READ) ? 'R' : '-', + (access1 & PAGE_WRITE) ? 'W' : '-', + (access1 & PAGE_EXEC) ? 'X' : '-'); + + switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { + case XTENSA_MPU_SYSTEM_TYPE_DEVICE: + qemu_printf("Device %cB %3s\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); + break; + case XTENSA_MPU_SYSTEM_TYPE_NC: + qemu_printf("Sys NC %cB %c%c%c\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); + break; + case XTENSA_MPU_SYSTEM_TYPE_C: + qemu_printf("Sys C %c%c%c %c%c%c\n", + (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', + (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', + (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 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Iglesias" , Marek Vasut , Max Filippov , "Dr . David Alan Gilbert" , Jiaxun Yang , Nicholas Piggin , Paolo Bonzini , Daniel Henrique Barboza , Yoshinori Sato , Markus Armbruster , Richard Henderson , qemu-ppc@nongnu.org, Laurent Vivier , Mark Cave-Ayland , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH-for-9.1 21/21] target/xtensa: Replace qemu_printf() by monitor_printf() in monitor Date: Thu, 21 Mar 2024 16:48:37 +0100 Message-ID: <20240321154838.95771-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240321154838.95771-1-philmd@linaro.org> References: <20240321154838.95771-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- target/xtensa/mmu.h | 2 +- target/xtensa/monitor.c | 117 ++++++++++++++++++++-------------------- 2 files changed, 61 insertions(+), 58 deletions(-) diff --git a/target/xtensa/mmu.h b/target/xtensa/mmu.h index 3e1d2c03ea..ef7504e16e 100644 --- a/target/xtensa/mmu.h +++ b/target/xtensa/mmu.h @@ -90,6 +90,6 @@ int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb, unsigned *access); void xtensa_reset_mmu(CPUXtensaState *env); -void xtensa_dump_mmu(CPUXtensaState *env); +void xtensa_dump_mmu(Monitor *mon, CPUXtensaState *env); #endif diff --git a/target/xtensa/monitor.c b/target/xtensa/monitor.c index 9ba068d624..1c3dc85ea1 100644 --- a/target/xtensa/monitor.c +++ b/target/xtensa/monitor.c @@ -22,7 +22,6 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "qemu/qemu-print.h" #include "qemu/units.h" #include "monitor/monitor.h" #include "monitor/hmp-target.h" @@ -31,7 +30,7 @@ #include "mmu.h" -static void dump_tlb(CPUXtensaState *env, bool dtlb) +static void dump_tlb(Monitor *mon, CPUXtensaState *env, bool dtlb) { unsigned wi, ei; const xtensa_tlb *conf = @@ -40,7 +39,7 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb) xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) ? mmu_attr_to_access : region_attr_to_access; - qemu_printf("%s:\n", dtlb ? "DTLB" : "IBLB"); + monitor_puts(mon, dtlb ? "DTLB\n" : "IBLB\n"); for (wi = 0; wi < conf->nways; ++wi) { uint32_t sz = ~xtensa_tlb_get_addr_mask(env, dtlb, wi) + 1; const char *sz_text; @@ -71,35 +70,39 @@ static void dump_tlb(CPUXtensaState *env, bool dtlb) if (print_header) { print_header = false; - qemu_printf("Way %u (%d %s)\n", wi, sz, sz_text); - qemu_printf("\tVaddr Paddr ASID Attr RWX Cache\n" - "\t---------- ---------- ---- ---- --- -------\n"); + monitor_printf(mon, + "Way %u (%d %s)\n", wi, sz, sz_text); + monitor_puts(mon, + "\tVaddr Paddr ASID Attr RWX Cache\n" + "\t---------- ---------- ---- ---- --- -------\n"); } - qemu_printf("\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", - entry->vaddr, - entry->paddr, - entry->asid, - entry->attr, - (access & PAGE_READ) ? 'R' : '-', - (access & PAGE_WRITE) ? 'W' : '-', - (access & PAGE_EXEC) ? 'X' : '-', - cache_text[cache_idx] ? - cache_text[cache_idx] : "Invalid"); + monitor_printf(mon, + "\t0x%08x 0x%08x 0x%02x 0x%02x %c%c%c %s\n", + entry->vaddr, + entry->paddr, + entry->asid, + entry->attr, + (access & PAGE_READ) ? 'R' : '-', + (access & PAGE_WRITE) ? 'W' : '-', + (access & PAGE_EXEC) ? 'X' : '-', + cache_text[cache_idx] ? + cache_text[cache_idx] : "Invalid"); } } } } -static void dump_mpu(CPUXtensaState *env, const char *map_desc, +static void dump_mpu(Monitor *mon, CPUXtensaState *env, const char *map_desc, const xtensa_mpu_entry *entry, unsigned n) { unsigned i; - qemu_printf("%s map:\n", map_desc); - qemu_printf("\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" - "\t%s ---------- ---------- ----- ----- ------------- ---------\n", - env ? "En" : " ", - env ? "--" : " "); + monitor_printf(mon, "%s map:\n", map_desc); + monitor_printf(mon, + "\t%s Vaddr Attr Ring0 Ring1 System Type CPU cache\n" + "\t%s ---------- ---------- ----- ----- ------------- ---------\n", + env ? "En" : " ", + env ? "--" : " "); for (i = 0; i < n; ++i) { uint32_t attr = entry[i].attr; @@ -108,64 +111,64 @@ static void dump_mpu(CPUXtensaState *env, const char *map_desc, unsigned type = mpu_attr_to_type(attr); char cpu_cache = (type & XTENSA_MPU_TYPE_CPU_CACHE) ? '-' : ' '; - qemu_printf("\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", - env ? - ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', - entry[i].vaddr, attr, - (access0 & PAGE_READ) ? 'R' : '-', - (access0 & PAGE_WRITE) ? 'W' : '-', - (access0 & PAGE_EXEC) ? 'X' : '-', - (access1 & PAGE_READ) ? 'R' : '-', - (access1 & PAGE_WRITE) ? 'W' : '-', - (access1 & PAGE_EXEC) ? 'X' : '-'); + monitor_printf(mon, "\t %c 0x%08x 0x%08x %c%c%c %c%c%c ", + env ? + ((env->sregs[MPUENB] & (1u << i)) ? '+' : '-') : ' ', + entry[i].vaddr, attr, + (access0 & PAGE_READ) ? 'R' : '-', + (access0 & PAGE_WRITE) ? 'W' : '-', + (access0 & PAGE_EXEC) ? 'X' : '-', + (access1 & PAGE_READ) ? 'R' : '-', + (access1 & PAGE_WRITE) ? 'W' : '-', + (access1 & PAGE_EXEC) ? 'X' : '-'); switch (type & XTENSA_MPU_SYSTEM_TYPE_MASK) { case XTENSA_MPU_SYSTEM_TYPE_DEVICE: - qemu_printf("Device %cB %3s\n", - (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', - (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); + monitor_printf(mon, "Device %cB %3s\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_INT) ? "int" : ""); break; case XTENSA_MPU_SYSTEM_TYPE_NC: - qemu_printf("Sys NC %cB %c%c%c\n", - (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', - (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); + monitor_printf(mon, "Sys NC %cB %c%c%c\n", + (type & XTENSA_MPU_TYPE_B) ? ' ' : 'n', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); break; case XTENSA_MPU_SYSTEM_TYPE_C: - qemu_printf("Sys C %c%c%c %c%c%c\n", - (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', - (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', - (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', - (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, - (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); + monitor_printf(mon, "Sys C %c%c%c %c%c%c\n", + (type & XTENSA_MPU_TYPE_SYS_R) ? 'R' : '-', + (type & XTENSA_MPU_TYPE_SYS_W) ? 'W' : '-', + (type & XTENSA_MPU_TYPE_SYS_C) ? 'C' : '-', + (type & XTENSA_MPU_TYPE_CPU_R) ? 'r' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_W) ? 'w' : cpu_cache, + (type & XTENSA_MPU_TYPE_CPU_C) ? 'c' : cpu_cache); break; default: - qemu_printf("Unknown\n"); + monitor_puts(mon, "Unknown\n"); break; } } } -void xtensa_dump_mmu(CPUXtensaState *env) +void xtensa_dump_mmu(Monitor *mon, CPUXtensaState *env) { if (xtensa_option_bits_enabled(env->config, XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) | XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION) | XTENSA_OPTION_BIT(XTENSA_OPTION_MMU))) { - dump_tlb(env, false); - qemu_printf("\n"); - dump_tlb(env, true); + dump_tlb(mon, env, false); + monitor_puts(mon, "\n"); + dump_tlb(mon, env, true); } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_MPU)) { - dump_mpu(env, "Foreground", + dump_mpu(mon, env, "Foreground", env->mpu_fg, env->config->n_mpu_fg_segments); - qemu_printf("\n"); - dump_mpu(NULL, "Background", + monitor_puts(mon, "\n"); + dump_mpu(mon, NULL, "Background", env->config->mpu_bg, env->config->n_mpu_bg_segments); } else { - qemu_printf("No TLB for this CPU core\n"); + monitor_puts(mon, "No TLB for this CPU core\n"); } } @@ -177,5 +180,5 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict) monitor_printf(mon, "No CPU available\n"); return; } - xtensa_dump_mmu(env1); + xtensa_dump_mmu(mon, env1); }