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[114.35.142.126]) by smtp.gmail.com with ESMTPSA id z14-20020a170903018e00b001e088a9e2bcsm1380380plg.292.2024.03.22.02.26.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 02:26:10 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson Subject: [PATCH v2 1/4] target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and vfncvt.f.f.w instructions Date: Fri, 22 Mar 2024 17:25:55 +0800 Message-Id: <20240322092600.1198921-2-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240322092600.1198921-1-max.chou@sifive.com> References: <20240322092600.1198921-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=max.chou@sifive.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w instructions will be affected by Zvfhmin extension. And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the conversions of * From 1*SEW(16/32) to 2*SEW(32/64) * From 2*SEW(32/64) to 1*SEW(16/32) Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7d84e7d8124..ef568e263d1 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s) } } +static bool require_rvfmin(DisasContext *s) +{ + if (s->mstatus_fs == EXT_STATUS_DISABLED) { + return false; + } + + switch (s->sew) { + case MO_16: + return s->cfg_ptr->ext_zvfhmin; + case MO_32: + return s->cfg_ptr->ext_zve32f; + default: + return false; + } +} + static bool require_scale_rvf(DisasContext *s) { if (s->mstatus_fs == EXT_STATUS_DISABLED) { @@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s) } switch (s->sew) { - case MO_8: - return s->cfg_ptr->ext_zvfhmin; case MO_16: return s->cfg_ptr->ext_zve32f; case MO_32: @@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && + require_rvfmin(s) && require_scale_rvfmin(s) && (s->sew != MO_8); } @@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && + require_rvfmin(s) && require_scale_rvfmin(s) && (s->sew != MO_8); } From patchwork Fri Mar 22 09:25:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13599851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D7736C47DD9 for ; Fri, 22 Mar 2024 09:33:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnbGH-0006XO-Ly; Fri, 22 Mar 2024 05:32:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnbG9-0006WT-8K for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:32:21 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnbG5-0007rD-NB for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:32:20 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-6e6ca2ac094so1695311b3a.0 for ; Fri, 22 Mar 2024 02:32:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711099935; x=1711704735; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=amxbPeLbXqo1zWE4TFT0EG8FVb63cJF/WE2DZa4oq1U=; b=Gx3LKD6o7jLatyJQvoFtNV82MAlHbgapj8AssepvcrczlJsaJQiqeNrO8x3OBZuqAY /EmFKlapiW88IuZ/3k2NaPDWVqp0rU8/zAgA1pC4aEo8CzG9W83XswP8TjkRgqPqQMre VbF3n11m+R+59BvNdMNRwuIURUdFhOloEbm0FDwnZ3E3pzVNcy1yGVdvTZH2Pe54LGhO St76aSRH9IU0z9sFcpu7gOQuyw14BzJJflFXWZkdwI3TcVHgHpfdKVn8GQLOREaYD/rU mJ2N2waOmh6Uv95wnloMcyFH354hRfPhNNRBwYY3QhGe+7xrS+NzXxsR0AwZP1vTRMYz Odpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711099935; x=1711704735; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=amxbPeLbXqo1zWE4TFT0EG8FVb63cJF/WE2DZa4oq1U=; b=mYzFjMSHKFPbjp/DeQqSPKpzKpXDi+A7lAgyvoAUCv5EqVnenmyqpJ/VHdG+I1aqGC GzrwhPTXm0ly4vCaNYFg/8Dd+WUtw3CNxj0oapQ6I2EJLxz2QmDGWud1HVUStYazkVD6 2++BRE6RNM0x2KTvVOkLUnqDP0nOZr2EuJAvWSp5TvdAQ9ee9jd1f8FY6dNaiwGEXn+e BDBZO1xivXNOtu7TDFJHz6i4X2JDaOM+tTS5kIPSgHGTePBFji71RLBFXxIc6675Ctpy RsyXk84kqAVqrK6A62feMBvGi4LCig794wIy37XI8dnYGUZ94zU93LtlCcwdIxGabREH 92cg== X-Gm-Message-State: AOJu0YzuuM6DkNPRKDwD+g7phWZdxoFL9DLyjl1ndJ2iXOnfqKftV9ZL tcyAzq3LKsrUEqKzv11gKE+b5GuM0rg0u9ZRpAh/t+smNkDx2pOoydmWx2BJd9vPeVMUZpPcqrc gnW8YTNAlhJuekzUFAqp7B/SNYBxT19l+Of3kwXMjWGLfM1ZLPWsdkKGZ1xByjxxy7nrVCHz+CW sU7xEFw820swDDHcC3e6PxOtTAuhKy9IaZulbv4g== X-Google-Smtp-Source: AGHT+IG5IZkGhxJhqO0EdzGXlNDu4cIS+WC6cZJdvk0/yA9LjjS7ybyWW4hJKJ5n5CicdKJXtKNGjQ== X-Received: by 2002:a05:6a20:f21:b0:1a3:57b4:ed1c with SMTP id fl33-20020a056a200f2100b001a357b4ed1cmr1674613pzb.25.1711099576574; Fri, 22 Mar 2024 02:26:16 -0700 (PDT) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id z14-20020a170903018e00b001e088a9e2bcsm1380380plg.292.2024.03.22.02.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 02:26:16 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson Subject: [PATCH v2 2/4] target/riscv: rvv: Check single width operator for vector fp widen instructions Date: Fri, 22 Mar 2024 17:25:56 +0800 Message-Id: <20240322092600.1198921-3-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240322092600.1198921-1-max.chou@sifive.com> References: <20240322092600.1198921-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The require_scale_rvf function only checks the double width operator for the vector floating point widen instructions, so most of the widen checking functions need to add require_rvf for single width operator. The vfwcvt.f.x.v and vfwcvt.f.xu.v instructions convert single width integer to double width float, so the opfxv_widen_check function doesn’t need require_rvf for the single width operator(integer). Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ef568e263d1..6cb9bc9fde8 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2331,6 +2331,7 @@ GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2370,6 +2371,7 @@ GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2402,6 +2404,7 @@ GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2441,6 +2444,7 @@ GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) { return require_rvv(s) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8) && vext_check_isa_ill(s) && @@ -2941,6 +2945,7 @@ GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_widen_check(s, a) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8); } From patchwork Fri Mar 22 09:25:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13599852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A373EC47DD9 for ; Fri, 22 Mar 2024 09:33:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnbGd-0006fX-AQ; Fri, 22 Mar 2024 05:32:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnbGb-0006fL-BT for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:32:49 -0400 Received: from mail-qt1-x830.google.com ([2607:f8b0:4864:20::830]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnbGZ-000807-Vz for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:32:49 -0400 Received: by mail-qt1-x830.google.com with SMTP id d75a77b69052e-429de32dad9so12514641cf.2 for ; Fri, 22 Mar 2024 02:32:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711099966; x=1711704766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NK+9yRKUKzgO+toUFNyttunP9TjjWWzFsOj48XWUWIU=; b=ELGatM7yx6RR0FqCxnD4lFIBLOBOAlXaZxs7mmcYnn8XPkR/X9UlahYQDcf/KC03Zb u8M0g9/xy8fkFfb0xs/ryNkEeZs+sjyqHtpGi5ZV5zyq860NjiD1X9hckGfIap+8PYwV +QfPAK6OogYTg8HItHhKRFnlgZ+RGZqe+6vuXtFcHkwC2sDWZtge9MI4k38V9UAyv6hI gZI52AoTRBwEAfVz52YanyytIBl+1V8louN+9MjHuzNke36Dq79/kgKtnfXjBoxeqoN+ d3p4Kp8I8xZmsupv8SQ5ztq/7SWAVxcsAjOftUwlSu/ErCDfREY0rPiE4ig15qgKWkO8 WZdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711099966; x=1711704766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NK+9yRKUKzgO+toUFNyttunP9TjjWWzFsOj48XWUWIU=; b=nCChSWSNxn/ckLS3mCgki0XpFtLjx+qYv73xadT7cPU6sxE8mW1/EqEU5W/uAQFZKk f6Zc3XV1dDifb4Qejcc1cIeSvAhaxrqqQRRwD1T83tQElGUKwple3WDgQe+cbOudpD+F XH0lzLr/tsnDeotps3ixLgTnJXh3uHDhDFUcCUUItNfXFjujOaJqQf+tAIl/9ynyZUH8 An/uydz4/npOxk6jqsyHychz07JBhO30ILcgMrUk0nXnQ8LSBUC1ECNu3xeotqjbSiCs 8ud+kS9DFNEI4fv4nNeS3hXYs+t6+FuZmX7rQFRJf4Ds311XcSKN+o2vutQr4ZPkrmAO qKZg== X-Gm-Message-State: AOJu0YzrMmoP//ZMeXXzjMSEo9M6g6WXEliSrhxubZMF4CqAyDZN0tCq bySI1Uh386WpCXQ0evlj3AYOQ0sL0GJsDUMGmUygBW/Pw7y9GsjIUNKWa6WoTXOerbw0cOck74R lr2dH18+C2TncnME5/Z9F8fGzTgKmkQQpJksXpM6dDAT7L9lDItPpE+hASQ6nKgCebWjkX7L8zd CXcDWGE92rctl02vBo40B28oQyuZ1jJzt7jgURYg== X-Google-Smtp-Source: AGHT+IFFJCsdCgR5DUtw1hd2CwOyWmrOEhbETvWEYEROB7qnCvIBf4WgLwDNwQL5ZlvLFBkDw+G/Sg== X-Received: by 2002:a05:6a20:1b27:b0:1a3:703c:c809 with SMTP id ch39-20020a056a201b2700b001a3703cc809mr1743467pzb.21.1711099580884; Fri, 22 Mar 2024 02:26:20 -0700 (PDT) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id z14-20020a170903018e00b001e088a9e2bcsm1380380plg.292.2024.03.22.02.26.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 02:26:20 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson Subject: [PATCH v2 3/4] target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w Date: Fri, 22 Mar 2024 17:25:57 +0800 Message-Id: <20240322092600.1198921-4-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240322092600.1198921-1-max.chou@sifive.com> References: <20240322092600.1198921-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::830; envelope-from=max.chou@sifive.com; helo=mail-qt1-x830.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The opfv_narrow_check needs to check the single width float operator by require_rvf. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 6cb9bc9fde8..19059fea5f7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2817,6 +2817,7 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && + require_rvf(s) && require_scale_rvf(s) && (s->sew != MO_8); } From patchwork Fri Mar 22 09:25:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Chou X-Patchwork-Id: 13599827 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 219E7C47DD9 for ; Fri, 22 Mar 2024 09:26:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rnbAT-0004TG-AR; Fri, 22 Mar 2024 05:26:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rnbAS-0004Sx-9n for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:26:28 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rnbAQ-0006a6-Ny for qemu-devel@nongnu.org; Fri, 22 Mar 2024 05:26:28 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1e04ac200a6so14109965ad.1 for ; Fri, 22 Mar 2024 02:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711099585; x=1711704385; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oIE+jL5V4NFcGQVFSirTmvs1fIjF9x6KbRW+rLR/yNo=; b=RN7NB76VrbzNggcMeZu5W7doFSnNIfurYg9Jc9DFx0SeTGtlNVaIGnIAZmdrZh9rGQ ngi21lQ3rfsW/NbvRPg1Zjv/3MqtUhAynFs0pmtXK7qI1usB6On/Lq7oEJywqY8Q6f8O 7+jeyfoWPzHimq9A/Fjzh2BRFwuE9O+xbLpEddNafxvkzzShgdkn/u2KTE3hmV57YlBj aErL+mqYJ5vYItl++fSDaLq64WPw2Xi+Rq95Z/fKAlKIhkClJOTFAyaJuJOhyeLuMkHD fQLu5mLfge0jIhTB6CxZEw+1kqL1z02xvGcxeoTT14BXDPwa7znRXzn/zr9AJikssGKQ YEfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711099585; x=1711704385; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oIE+jL5V4NFcGQVFSirTmvs1fIjF9x6KbRW+rLR/yNo=; b=LWA0N3hF+ewRFZPE4TDUtlSbfSSR1WjxX1fo3fvTDhp97xjDeGpVbIg66nUSGqsKKO 3i4SN4d1bJogZdfvxTByqqWaGid2KnPeU6oY0VMhHosKwCO1BlAI9GiJwqH526rPulGr Dz3FX+TNtoqHzivmPBR1or0un3iWcmnv1b8wzLc5BZAMozNaX1aEpstQXCP2XvqyVmkc Z7hABlAPThUOc//g/TTZTA2OhTjwxap6icC0kIHuZfQp0DGyyXCyrwn+hxsCb7rK14/Z gSs+bYRpnjM5gS6fmnN0vx2yg2cxbiDgb9WXSUt9h8ZzbFvTKsBuCep+eE//X5xpmdD9 w+KA== X-Gm-Message-State: AOJu0YxR5DxCLnBoOxxK2wuMHEKYF2rhEWfHRg5N8FXGqbzP7N9cD7Cl MtyeJQbBtueu6GbHD3xuvx3VcBZEfdterKCWmEfNpaDFnYUs3FjG7AfhQcV+TD3/F1gM0CBfGy/ Z53qbJbo85rpf+bOCgqMd9qdelfc0xNyjKa+HYBDMWaePo3xC5pkZnqOu7bt/0yR5STrhJSJFIc OMJFNF/KryWM1e+GRWEJtr8b5kShB+PKKShLRXqA== X-Google-Smtp-Source: AGHT+IFw7e3WoILatcfaBF/HJNBuuMaSUQvcohj0Y7vtZhXvpLFnLFMMiZGMFS/DNTTwRrGULy3xUg== X-Received: by 2002:a17:903:244d:b0:1de:de58:2a5f with SMTP id l13-20020a170903244d00b001dede582a5fmr2057305pls.33.1711099585117; Fri, 22 Mar 2024 02:26:25 -0700 (PDT) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id z14-20020a170903018e00b001e088a9e2bcsm1380380plg.292.2024.03.22.02.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Mar 2024 02:26:24 -0700 (PDT) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Max Chou , Daniel Henrique Barboza , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson Subject: [PATCH v2 4/4] target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions Date: Fri, 22 Mar 2024 17:25:58 +0800 Message-Id: <20240322092600.1198921-5-max.chou@sifive.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240322092600.1198921-1-max.chou@sifive.com> References: <20240322092600.1198921-1-max.chou@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=max.chou@sifive.com; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org If the checking functions check both the single and double width operators at the same time, then the single width operator checking functions (require_rvf[min]) will check whether the SEW is 8. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza --- target/riscv/insn_trans/trans_rvv.c.inc | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 19059fea5f7..08c22f48cb4 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2333,7 +2333,6 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2373,7 +2372,6 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_ds(s, a->rd, a->rs2, a->vm); } @@ -2406,7 +2404,6 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); } @@ -2446,7 +2443,6 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && - (s->sew != MO_8) && vext_check_isa_ill(s) && vext_check_dd(s, a->rd, a->rs2, a->vm); } @@ -2704,8 +2700,7 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) { return opfv_widen_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } #define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2810,16 +2805,14 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s) && - (s->sew != MO_8); + require_scale_rvfmin(s); } static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) { return opfv_narrow_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } #define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ @@ -2947,8 +2940,7 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) { return reduction_widen_check(s, a) && require_rvf(s) && - require_scale_rvf(s) && - (s->sew != MO_8); + require_scale_rvf(s); } GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check)