From patchwork Tue Mar 26 04:08:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 13603574 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2057.outbound.protection.outlook.com [40.107.100.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 731141292FD; Tue, 26 Mar 2024 04:08:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.100.57 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711426116; cv=fail; b=OUGj9bQ13ODTRLtyseVAwKx3CBEcI+S0wIG0Xk3wk4xwkMzUAhENhB00JjJGrcSVPOBKUGnMw48M2uWh3kO8ACH2rwLcpwuTWx3AJlDONM5bu3whXax5JlWQj7Kd64OKmvF3d48ipqehFR1OX/SMQsWpgDAzwvc7sgDeB6nugiI= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711426116; c=relaxed/simple; bh=3MfbvHfZMvHx2cdIOJF5L5eMAFPXcXs5Te+ZUwM7kAI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=JTckWRdhuSgYz/Qf8rfDJMseeeIC0jyLdgF5+NtmxO+dZSN5yQypd2tvw2lX/07xlYJNygGgX0QnfWMXgZd29QMbPaPVLf5OVWdHrJBP01eJ9m6K8+Hhz0aVKxwlLKZQsZGYo0W/clJSgTo/bxJKMxHckWua0/lP0jMz1infaak= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=0RhkwUC9; arc=fail smtp.client-ip=40.107.100.57 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="0RhkwUC9" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TzshYhdsjt9wrnAlONh3s+qWELBmCNCocvkSXSFNZ9YQyQ6HvIhX36wGl7+O/1smsxaIZ5Ggip7JTssfudXm4Jn+mj3AM5n+dYb4WVaICO4uPMxy5u6s/kUbAK/oA+BRWoYBUN5VqliqqPbH3MUUnxCVeJ2/tFaCCIpVQ1IMLGwo2Q/J7Gy0KGH5qkXdmo7kuHcYN0aR1GEXSxscEcCWup6WqHuKCQrf+4s0fMIJErz2x8r1PI6SSpYYcPiOOSMIH1etBj0ogfe3Htv8t/nxGzcW647yIR/EJkPYVnCI78jWhzHK6Y4EAGMQkpCsOkonGQ5GqpNJ7lECrBwyOULb1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bhZgpX5T3qGDr28ATiTErkgqzVOC1njc+qjZoXkQSD0=; b=iPWVQOgwsxunvMQeSb+z7abLZyXc/f6vZwuwc0ixkK3/pyKwQXtguMo9gOIoVkaBZmPxgTdr0FuWIKDFpCkEClILO90FQhB9rfeAN1wuaY4l6O9TpL1zMo+yO/qfb5QM6RAsQyeH2mA+5IK1//A1SciH9GquDqjyNmsepF/bDtBfapk5SFP+3ZsxNEu3lmsMuxsVuR/xoVIqF+IXoyWDDFyZpYETogFGS55AwDjfn2C/Gj0vZQgRE4M1z4SHFQTMUVdcvn4W9oASvrkY0KCS30kjGLj166mCywCIwVDVHCrOgN0b/g03fbnbKEmvPi4/dH6pyKN8kHM92+RYaMCcwQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=redhat.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bhZgpX5T3qGDr28ATiTErkgqzVOC1njc+qjZoXkQSD0=; b=0RhkwUC9twUW0xQf7a6oxOuypORWYLz9giy05jrjTHTRSobz9wueTV/q0od056cxUWtzc71fBZ5cxlDRR2e0f6twg1qXMaI4ptYGxWCqznR2HA+Oxm+bBZxECvUX1haaioombcdOwz9ILplTnK/oKMaonq6RgSjrn3KxoVjMm6s= Received: from PH8PR05CA0003.namprd05.prod.outlook.com (2603:10b6:510:2cc::24) by CH3PR12MB7641.namprd12.prod.outlook.com (2603:10b6:610:150::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.31; Tue, 26 Mar 2024 04:08:29 +0000 Received: from CY4PEPF0000FCC2.namprd03.prod.outlook.com (2603:10b6:510:2cc:cafe::a8) by PH8PR05CA0003.outlook.office365.com (2603:10b6:510:2cc::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.12 via Frontend Transport; Tue, 26 Mar 2024 04:08:28 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCC2.mail.protection.outlook.com (10.167.242.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Tue, 26 Mar 2024 04:08:28 +0000 Received: from SATLEXMB06.amd.com (10.181.40.147) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Mar 2024 23:08:13 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB06.amd.com (10.181.40.147) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Mar 2024 23:08:13 -0500 Received: from xhdipdslab41.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Mar 2024 23:08:09 -0500 From: Nipun Gupta To: , , , , CC: , , , , , , , , Nipun Gupta Subject: [PATCH v5 1/2] genirq/msi: add wrapper msi allocation API and export msi functions Date: Tue, 26 Mar 2024 09:38:03 +0530 Message-ID: <20240326040804.640860-1-nipun.gupta@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC2:EE_|CH3PR12MB7641:EE_ X-MS-Office365-Filtering-Correlation-Id: aa0cf3aa-744e-4087-4091-08dc4d4a6458 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: wRO26eC1883RoWUWIfYhLLH7qhOdhXKP0UTaPDi/yOu+uUUVxIz0A9apcCHgmL70Jmj2TeAVMGeeRJpOV/D3EqcYC07c8q2KRL2ywU+hN4g7YAPftvkkDsRHNl4vnSGB/+ZfK13RQQ2QuGII7q7jS2sz5SIYWAU3Ipi+JVv7vwy0Fx/i3VV+BBuG+3OHXjFHBAqKUasdoC5As9Qn14zPleSZmBy1i10ohId1IcUOtAJTRASF/em559sbKwt9N9go7nkI2P2loBV8cPzrrn7WkhRAVpB1VVcNfscuuQBjQkHWCGtw+/0irOVPxu2bqYSH4ecGpSzJELCNfQKBDaO2DR9LaAeF1KgaNZZARM+Hf7iNTV5jc11KlGWctFDpich0zriEsSlljZdlsgzLMYQSRGxj1NcDnYjYCIOIY7sPRCUvz/tb4FpjGC6HCDaxO5xbelHF86kivXbEptvKPJA/TAZ8o1UNyhAgGbYM8scNrgu1j0jMh8HzS4LTrEPIMmyignj4bwEr9/hsckn6mwYcdSIz/VsMV5gYeNd81QqSVo32e2L5AUA2LqLWxzKn2BvjMstu/6WETNgiZgn7wWgpXgbt7uRorjDVVAce6j18LpJ67mZ+0IIeIzhb9E4ZXy8+n/8wKUX5g3e+0Mt+gGshuoT/fTlaAN8Ty8dRWiN71UeGOswdcL6gSO1/rZ7lF+4NQNj0BzgEnI1HcZv7NdXqiSSePdgyL0e3NIrfC9knF+iZO+uTRxhttZw6+t9B0gqh X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(82310400014)(376005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2024 04:08:28.4473 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa0cf3aa-744e-4087-4091-08dc4d4a6458 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7641 MSI functions for allocation and free can be directly used by the device drivers without any wrapper provided by bus drivers. So export these MSI functions. Also, add a wrapper API to allocate MSIs providing only the number of interrupts rather than range for simpler driver usage. Signed-off-by: Nipun Gupta Reviewed-by: Thomas Gleixner --- Changes in v4->v5: - updated commit description as per the comments. - Rebased on 6.9-rc1 Changes in v3->v4: - No change Changes in v3: - New in this patch series. VFIO-CDX uses the new wrapper API msi_domain_alloc_irqs and exported APIs. (This patch is moved from CDX interrupt support to vfio-cdx patch, where these APIs are used). include/linux/msi.h | 6 ++++++ kernel/irq/msi.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/include/linux/msi.h b/include/linux/msi.h index 26d07e23052e..765a65581a66 100644 --- a/include/linux/msi.h +++ b/include/linux/msi.h @@ -676,6 +676,12 @@ int platform_device_msi_init_and_alloc_irqs(struct device *dev, unsigned int nve void platform_device_msi_free_irqs_all(struct device *dev); bool msi_device_has_isolated_msi(struct device *dev); + +static inline int msi_domain_alloc_irqs(struct device *dev, unsigned int domid, int nirqs) +{ + return msi_domain_alloc_irqs_range(dev, domid, 0, nirqs - 1); +} + #else /* CONFIG_GENERIC_MSI_IRQ */ static inline bool msi_device_has_isolated_msi(struct device *dev) { diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index f90952ebc494..2024f89baea4 100644 --- a/kernel/irq/msi.c +++ b/kernel/irq/msi.c @@ -1434,6 +1434,7 @@ int msi_domain_alloc_irqs_range(struct device *dev, unsigned int domid, msi_unlock_descs(dev); return ret; } +EXPORT_SYMBOL_GPL(msi_domain_alloc_irqs_range); /** * msi_domain_alloc_irqs_all_locked - Allocate all interrupts from a MSI interrupt domain @@ -1680,6 +1681,7 @@ void msi_domain_free_irqs_range(struct device *dev, unsigned int domid, msi_domain_free_irqs_range_locked(dev, domid, first, last); msi_unlock_descs(dev); } +EXPORT_SYMBOL_GPL(msi_domain_free_irqs_all); /** * msi_domain_free_irqs_all_locked - Free all interrupts from a MSI interrupt domain From patchwork Tue Mar 26 04:08:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nipun Gupta X-Patchwork-Id: 13603575 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2067.outbound.protection.outlook.com [40.107.94.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 099E612A173; Tue, 26 Mar 2024 04:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.94.67 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711426121; cv=fail; b=GyQ3PEzK98U7Marc06dpqAy/Lj4E2rloEVWwAcq7ELvORhQl96pLaOwISm+c14QfHYPtWR34w8hUMVvrFdedIgwY1qALz+z8/zTVYd2Fj7ZH4yx/q+XonhSl8JDJc8t5Q0RzfUJ0Mah94Tchjz5e1id/ClhUffe9P3+kZM5xVhQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711426121; c=relaxed/simple; bh=Jw3usVh/MIiMvENiqk9Af4G2zGU9jUrAQs0WCWqqumI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hQjOEvBRjmjS8X52txSy3/4+Cm9HVgA9ZJfcSBFayFgIhGIFvVLyOV6wqBq/3DuyWFVYZM702gJCdfCBRurqekoZk2ZHSZvwofJ4JaAU+R5ZOtYpvkOAeM3vnaImFSbyMvd+HsvrdsvwtzHerfpwLqfu7U8h0Qo1B5epz+Ppb8M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=gSaZsCO/; arc=fail smtp.client-ip=40.107.94.67 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="gSaZsCO/" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HERzXsNAhTB6utGRADwAHNLAZW+Juvq79ebSnAoicN4OkOKg4GAheAwajN1yE/mz/NIsw4lLQQeGpS6L0pyFvIsXb7S1mYV+jRTImzU6rZ+sI0cjJuZhA/0eeA9jh9CmrAQuF+yosvPMPhXJNWk+itcPXc4wK/v1AuUfe8g3PtDfUNHBx2qxK1Sb6lgrbxGCFSr7i97me1iGd6f9MnevmX0QVWLmXzT7zOSOMXGgLeQkWNLFzfnTroLpVHgDAsi1Fa1eutTNwgAcdYPiy9JzB9GI5inLu/KrGR+wsQt0dHesJO4OOlv15mKpg5fG+b3rs5IsfSwT5OZztcOsDzdKag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GFmtx1aRVfCgDYTiofdBxSuFuo08LfM6PPB6t/IFGug=; b=TWXxHuRGyuWyeD85eZxaPJ+C1iHLZHt/iI32gPgerslKVv1qR1RG6tk4dVMxVnwWLj/gXkraVRBXZFVQw8LvYpdiyuUByrXNtYuhZIazopPww6jVADbmUF2IktljlyLwqOsRZsuawYkKiVPbwGkScjXOqP0VtBeWOXAnitnRpzs1RfF0Dxr5+mqdvnXBnKbjPmlK72TRgsEeBWSPECOlwLBRTiMk1jGhlJ3srxsBl85gBSundr9z6ASRRIwqtpNpopnFJKcvGUyWLBAffT9tIAT7Etc3T1xS03oVKYuC9XymX0MpxOV5GP3bhDyzi9L7Wy8+wZcPXceAkJFefAfzNg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=redhat.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GFmtx1aRVfCgDYTiofdBxSuFuo08LfM6PPB6t/IFGug=; b=gSaZsCO/WCw8p1eOCy43SwV+TYTz8gDlHnYgMHdI4eSoxWLcfOXuX1g7Ts+weieC4MHhnr+LVk1erfmWfX+3RJ1XL1XiRmr980DfD1+nGq+ZiFBDnQa8BawrHKs4gBSQJbpEf9XF/mxf4H4gXWhglV5onj80KUYS5B7Ab54CmnE= Received: from PH8PR05CA0021.namprd05.prod.outlook.com (2603:10b6:510:2cc::9) by DS0PR12MB8044.namprd12.prod.outlook.com (2603:10b6:8:148::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.31; Tue, 26 Mar 2024 04:08:36 +0000 Received: from CY4PEPF0000FCC2.namprd03.prod.outlook.com (2603:10b6:510:2cc:cafe::f1) by PH8PR05CA0021.outlook.office365.com (2603:10b6:510:2cc::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.12 via Frontend Transport; Tue, 26 Mar 2024 04:08:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000FCC2.mail.protection.outlook.com (10.167.242.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Tue, 26 Mar 2024 04:08:29 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 25 Mar 2024 23:08:18 -0500 Received: from xhdipdslab41.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 25 Mar 2024 23:08:15 -0500 From: Nipun Gupta To: , , , , CC: , , , , , , , , Nipun Gupta Subject: [PATCH v5 2/2] vfio/cdx: add interrupt support Date: Tue, 26 Mar 2024 09:38:04 +0530 Message-ID: <20240326040804.640860-2-nipun.gupta@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240326040804.640860-1-nipun.gupta@amd.com> References: <20240326040804.640860-1-nipun.gupta@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: nipun.gupta@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC2:EE_|DS0PR12MB8044:EE_ X-MS-Office365-Filtering-Correlation-Id: 361dc4e1-5bba-4a82-3828-08dc4d4a6512 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F5dKAqziI5kRMKroJyuMrDbi9F3wEmPAi3qa2663B5Tte5YQI99p4Mp1F8qTpKOqdSb3N1EjBoGechGXICiEbmI86FQFXrbM0ruckxyys0rq6ZzJuSugxibpXU999ApLaNP9sLhRzxMtLHk37nHhxEANDAxTMeU5TRmIAnl8PbGZb8+NNwvFqT5jmSCeFQN1Rzt2hUyAnqayfxy2tS+knAj1gNKBCPueFSGMjf62HFJeA6/x6mBXO1PB4jyYjbsX+F+6gRk7Jr8UUtok0sRyGqD3l8lni6o6kZbrTynuDygMM8hOf2Fa2HZ6VowqV5MuLY+r22OBWLI3vox2xDT8KuUD4lBLMu9CxnuYAAvJIP/S6pi4ObhWNzUjxm5pyTzoaq6s8FFSXQEQpWMs/XHokInkdxRL3DKIyT1xRttzdsUc56oyper+3f1L/dzSe9vWQTcUpH4jvcfu7CHiO5mCRNTw3/kfZl8goj8pVNzIa/9iNVAFMqcS5UKrFRte3rGlHWUOLVyHVRMyHJjeJ6fy9M1S9aFTZPornpH1LGTMMR1Zl7hqkyc6bCHp5W09RihdloVQpJwR3ynb4vK4yr2Hnhzm7Py1Bvw0vf8u1WOLmDt0c1CMy/L6yZG6ussBM3k214mmxowuy8uUQedf7pRWOtwut6/efgakFMT0oO/JWNbbYPFwWyNoKB3U1zYfRtUQ4L2lw2h5W1UkiU+7ywttWZRgocjMtZRLL4QVd0CDnqP0LBIQUJYqQE3SLD4YkZy/ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(36860700004)(82310400014)(376005)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Mar 2024 04:08:29.6348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 361dc4e1-5bba-4a82-3828-08dc4d4a6512 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8044 Support the following ioctls for CDX devices: - VFIO_DEVICE_GET_IRQ_INFO - VFIO_DEVICE_SET_IRQS This allows user to set an eventfd for cdx device interrupts and trigger this interrupt eventfd from userspace. All CDX device interrupts are MSIs. The MSIs are allocated from the CDX-MSI domain. Signed-off-by: Nipun Gupta Reviewed-by: Pieter Jansen van Vuuren --- Changes v4->v5: - Rebased on 6.9-rc1 Changes v3->v4: - Added VFIO_IRQ_INFO_NORESIZE flag Changes v2->v3: - Use generic MSI alloc/free APIs instead of CDX MSI APIs - Rebased on Linux 6.8-rc6 Changes v1->v2: - Rebased on Linux 6.7-rc1 drivers/vfio/cdx/Makefile | 2 +- drivers/vfio/cdx/intr.c | 211 +++++++++++++++++++++++++++++++++++++ drivers/vfio/cdx/main.c | 60 ++++++++++- drivers/vfio/cdx/private.h | 18 ++++ 4 files changed, 289 insertions(+), 2 deletions(-) create mode 100644 drivers/vfio/cdx/intr.c diff --git a/drivers/vfio/cdx/Makefile b/drivers/vfio/cdx/Makefile index cd4a2e6fe609..df92b320122a 100644 --- a/drivers/vfio/cdx/Makefile +++ b/drivers/vfio/cdx/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_VFIO_CDX) += vfio-cdx.o -vfio-cdx-objs := main.o +vfio-cdx-objs := main.o intr.o diff --git a/drivers/vfio/cdx/intr.c b/drivers/vfio/cdx/intr.c new file mode 100644 index 000000000000..4637b57d0242 --- /dev/null +++ b/drivers/vfio/cdx/intr.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include +#include + +#include "linux/cdx/cdx_bus.h" +#include "private.h" + +static irqreturn_t vfio_cdx_msihandler(int irq_no, void *arg) +{ + struct eventfd_ctx *trigger = arg; + + eventfd_signal(trigger); + return IRQ_HANDLED; +} + +static int vfio_cdx_msi_enable(struct vfio_cdx_device *vdev, int nvec) +{ + struct cdx_device *cdx_dev = to_cdx_device(vdev->vdev.dev); + struct device *dev = vdev->vdev.dev; + int msi_idx, ret; + + vdev->cdx_irqs = kcalloc(nvec, sizeof(struct vfio_cdx_irq), GFP_KERNEL); + if (!vdev->cdx_irqs) + return -ENOMEM; + + ret = cdx_enable_msi(cdx_dev); + if (ret) { + kfree(vdev->cdx_irqs); + return ret; + } + + /* Allocate cdx MSIs */ + ret = msi_domain_alloc_irqs(dev, MSI_DEFAULT_DOMAIN, nvec); + if (ret) { + cdx_disable_msi(cdx_dev); + kfree(vdev->cdx_irqs); + return ret; + } + + for (msi_idx = 0; msi_idx < nvec; msi_idx++) + vdev->cdx_irqs[msi_idx].irq_no = msi_get_virq(dev, msi_idx); + + vdev->irq_count = nvec; + vdev->config_msi = 1; + + return 0; +} + +static int vfio_cdx_msi_set_vector_signal(struct vfio_cdx_device *vdev, + int vector, int fd) +{ + struct eventfd_ctx *trigger; + int irq_no, ret; + + if (vector < 0 || vector >= vdev->irq_count) + return -EINVAL; + + irq_no = vdev->cdx_irqs[vector].irq_no; + + if (vdev->cdx_irqs[vector].trigger) { + free_irq(irq_no, vdev->cdx_irqs[vector].trigger); + kfree(vdev->cdx_irqs[vector].name); + eventfd_ctx_put(vdev->cdx_irqs[vector].trigger); + vdev->cdx_irqs[vector].trigger = NULL; + } + + if (fd < 0) + return 0; + + vdev->cdx_irqs[vector].name = kasprintf(GFP_KERNEL, "vfio-msi[%d](%s)", + vector, dev_name(vdev->vdev.dev)); + if (!vdev->cdx_irqs[vector].name) + return -ENOMEM; + + trigger = eventfd_ctx_fdget(fd); + if (IS_ERR(trigger)) { + kfree(vdev->cdx_irqs[vector].name); + return PTR_ERR(trigger); + } + + ret = request_irq(irq_no, vfio_cdx_msihandler, 0, + vdev->cdx_irqs[vector].name, trigger); + if (ret) { + kfree(vdev->cdx_irqs[vector].name); + eventfd_ctx_put(trigger); + return ret; + } + + vdev->cdx_irqs[vector].trigger = trigger; + + return 0; +} + +static int vfio_cdx_msi_set_block(struct vfio_cdx_device *vdev, + unsigned int start, unsigned int count, + int32_t *fds) +{ + int i, j, ret = 0; + + if (start >= vdev->irq_count || start + count > vdev->irq_count) + return -EINVAL; + + for (i = 0, j = start; i < count && !ret; i++, j++) { + int fd = fds ? fds[i] : -1; + + ret = vfio_cdx_msi_set_vector_signal(vdev, j, fd); + } + + if (ret) { + for (--j; j >= (int)start; j--) + vfio_cdx_msi_set_vector_signal(vdev, j, -1); + } + + return ret; +} + +static void vfio_cdx_msi_disable(struct vfio_cdx_device *vdev) +{ + struct cdx_device *cdx_dev = to_cdx_device(vdev->vdev.dev); + struct device *dev = vdev->vdev.dev; + + vfio_cdx_msi_set_block(vdev, 0, vdev->irq_count, NULL); + + if (!vdev->config_msi) + return; + + msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN); + cdx_disable_msi(cdx_dev); + kfree(vdev->cdx_irqs); + + vdev->cdx_irqs = NULL; + vdev->irq_count = 0; + vdev->config_msi = 0; +} + +static int vfio_cdx_set_msi_trigger(struct vfio_cdx_device *vdev, + unsigned int index, unsigned int start, + unsigned int count, u32 flags, + void *data) +{ + struct cdx_device *cdx_dev = to_cdx_device(vdev->vdev.dev); + int i; + + if (start + count > cdx_dev->num_msi) + return -EINVAL; + + if (!count && (flags & VFIO_IRQ_SET_DATA_NONE)) { + vfio_cdx_msi_disable(vdev); + return 0; + } + + if (flags & VFIO_IRQ_SET_DATA_EVENTFD) { + s32 *fds = data; + int ret; + + if (vdev->config_msi) + return vfio_cdx_msi_set_block(vdev, start, count, + fds); + ret = vfio_cdx_msi_enable(vdev, cdx_dev->num_msi); + if (ret) + return ret; + + ret = vfio_cdx_msi_set_block(vdev, start, count, fds); + if (ret) + vfio_cdx_msi_disable(vdev); + + return ret; + } + + for (i = start; i < start + count; i++) { + if (!vdev->cdx_irqs[i].trigger) + continue; + if (flags & VFIO_IRQ_SET_DATA_NONE) + eventfd_signal(vdev->cdx_irqs[i].trigger); + } + + return 0; +} + +int vfio_cdx_set_irqs_ioctl(struct vfio_cdx_device *vdev, + u32 flags, unsigned int index, + unsigned int start, unsigned int count, + void *data) +{ + if (flags & VFIO_IRQ_SET_ACTION_TRIGGER) + return vfio_cdx_set_msi_trigger(vdev, index, start, + count, flags, data); + else + return -EINVAL; +} + +/* Free All IRQs for the given device */ +void vfio_cdx_irqs_cleanup(struct vfio_cdx_device *vdev) +{ + /* + * Device does not support any interrupt or the interrupts + * were not configured + */ + if (!vdev->cdx_irqs) + return; + + vfio_cdx_set_msi_trigger(vdev, 1, 0, 0, VFIO_IRQ_SET_DATA_NONE, NULL); +} diff --git a/drivers/vfio/cdx/main.c b/drivers/vfio/cdx/main.c index 9cff8d75789e..f0861a38ae10 100644 --- a/drivers/vfio/cdx/main.c +++ b/drivers/vfio/cdx/main.c @@ -61,6 +61,7 @@ static void vfio_cdx_close_device(struct vfio_device *core_vdev) kfree(vdev->regions); cdx_dev_reset(core_vdev->dev); + vfio_cdx_irqs_cleanup(vdev); } static int vfio_cdx_bm_ctrl(struct vfio_device *core_vdev, u32 flags, @@ -123,7 +124,7 @@ static int vfio_cdx_ioctl_get_info(struct vfio_cdx_device *vdev, info.flags |= VFIO_DEVICE_FLAGS_RESET; info.num_regions = cdx_dev->res_count; - info.num_irqs = 0; + info.num_irqs = cdx_dev->num_msi ? 1 : 0; return copy_to_user(arg, &info, minsz) ? -EFAULT : 0; } @@ -152,6 +153,59 @@ static int vfio_cdx_ioctl_get_region_info(struct vfio_cdx_device *vdev, return copy_to_user(arg, &info, minsz) ? -EFAULT : 0; } +static int vfio_cdx_ioctl_get_irq_info(struct vfio_cdx_device *vdev, + struct vfio_irq_info __user *arg) +{ + unsigned long minsz = offsetofend(struct vfio_irq_info, count); + struct cdx_device *cdx_dev = to_cdx_device(vdev->vdev.dev); + struct vfio_irq_info info; + + if (copy_from_user(&info, arg, minsz)) + return -EFAULT; + + if (info.argsz < minsz) + return -EINVAL; + + if (info.index >= 1) + return -EINVAL; + + info.flags = VFIO_IRQ_INFO_EVENTFD | VFIO_IRQ_INFO_NORESIZE; + info.count = cdx_dev->num_msi; + + return copy_to_user(arg, &info, minsz) ? -EFAULT : 0; +} + +static int vfio_cdx_ioctl_set_irqs(struct vfio_cdx_device *vdev, + struct vfio_irq_set __user *arg) +{ + unsigned long minsz = offsetofend(struct vfio_irq_set, count); + struct cdx_device *cdx_dev = to_cdx_device(vdev->vdev.dev); + struct vfio_irq_set hdr; + size_t data_size = 0; + u8 *data = NULL; + int ret = 0; + + if (copy_from_user(&hdr, arg, minsz)) + return -EFAULT; + + ret = vfio_set_irqs_validate_and_prepare(&hdr, cdx_dev->num_msi, + 1, &data_size); + if (ret) + return ret; + + if (data_size) { + data = memdup_user(arg->data, data_size); + if (IS_ERR(data)) + return PTR_ERR(data); + } + + ret = vfio_cdx_set_irqs_ioctl(vdev, hdr.flags, hdr.index, + hdr.start, hdr.count, data); + kfree(data); + + return ret; +} + static long vfio_cdx_ioctl(struct vfio_device *core_vdev, unsigned int cmd, unsigned long arg) { @@ -164,6 +218,10 @@ static long vfio_cdx_ioctl(struct vfio_device *core_vdev, return vfio_cdx_ioctl_get_info(vdev, uarg); case VFIO_DEVICE_GET_REGION_INFO: return vfio_cdx_ioctl_get_region_info(vdev, uarg); + case VFIO_DEVICE_GET_IRQ_INFO: + return vfio_cdx_ioctl_get_irq_info(vdev, uarg); + case VFIO_DEVICE_SET_IRQS: + return vfio_cdx_ioctl_set_irqs(vdev, uarg); case VFIO_DEVICE_RESET: return cdx_dev_reset(core_vdev->dev); default: diff --git a/drivers/vfio/cdx/private.h b/drivers/vfio/cdx/private.h index 8e9d25913728..7a8477ae4652 100644 --- a/drivers/vfio/cdx/private.h +++ b/drivers/vfio/cdx/private.h @@ -13,6 +13,14 @@ static inline u64 vfio_cdx_index_to_offset(u32 index) return ((u64)(index) << VFIO_CDX_OFFSET_SHIFT); } +struct vfio_cdx_irq { + u32 flags; + u32 count; + int irq_no; + struct eventfd_ctx *trigger; + char *name; +}; + struct vfio_cdx_region { u32 flags; u32 type; @@ -25,6 +33,16 @@ struct vfio_cdx_device { struct vfio_cdx_region *regions; u32 flags; #define BME_SUPPORT BIT(0) + struct vfio_cdx_irq *cdx_irqs; + u32 irq_count; + u32 config_msi; }; +int vfio_cdx_set_irqs_ioctl(struct vfio_cdx_device *vdev, + u32 flags, unsigned int index, + unsigned int start, unsigned int count, + void *data); + +void vfio_cdx_irqs_cleanup(struct vfio_cdx_device *vdev); + #endif /* VFIO_CDX_PRIVATE_H */