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[1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:38 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register Date: Tue, 26 Mar 2024 23:00:24 +0800 Message-Id: <20240326150027.3015958-2-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The AST2500 WDT references the System Control Unit register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..5fd12c057c31 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785000 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785020 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785020 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt3: watchdog@1e785040 { @@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 { reg = <0x1e785040 0x20>; clocks = <&syscon ASPEED_CLK_APB>; status = "disabled"; + aspeed,scu = <&syscon>; }; pwm_tacho: pwm-tacho-controller@1e786000 { From patchwork Tue Mar 26 15:00:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 13604343 Received: from mail-oa1-f44.google.com (mail-oa1-f44.google.com [209.85.160.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1295E13C81B; Tue, 26 Mar 2024 15:00:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465244; cv=none; b=q1YEoar7Tfz39o3rhLDzmFahX9vW5AYlXCAqwg/o+EYmUqS6W9ZzdbdNFxvCA5tA2wjP62oNLDjdoaggoGdvtJtpvngg8u/yVCyCXMH78wwnV0jWgil2SmkYwH/NWHENQ8J+gzvEBUuX7KGnbq93ryF03OdGQ8iyAgou0P0SDQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465244; c=relaxed/simple; bh=OmbQeEpYAXewoGuDq+EgMFX3vG7k0YYOmneTwe9coEE=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jknCEAyMaN6NOSpBP22lwjEzyer4y7Z8jstimFHT7JAUeglPcpEIhzDBKi6aOuHpx12T3WBMIVb2NO6a31gm7goshRDjlsaCMvGODea50yu+auwksoLMhm3j8YI7R7I3eZ8hHufO8pKyawfWJo5qb2VdG2Hm59W/oYr2yM4JP0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ha0RCw0d; arc=none smtp.client-ip=209.85.160.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ha0RCw0d" Received: by mail-oa1-f44.google.com with SMTP id 586e51a60fabf-222ba2a19bdso3497769fac.1; Tue, 26 Mar 2024 08:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711465242; x=1712070042; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=dNSpu6YM8BptgR2qjrv8QihJHcI+7VsMuE3/EFlGmdw=; b=ha0RCw0dT2lnrmP6OHvYdaQouopg6ZDoCY449azy7VBRayhrudLKDQXRg/KN8e/J0f jhvxfwzlP5R/h48b79FlEiqHeWokKasFd3GmzOjsHxGcDBz9U534j5Xa3k5rnS8waJVj w4+f2XcOgrRyQ8shaRClrJA4LadYf5z/33CgEtR4gqbY2k8zJZHW5pLTXD6Z08y6h0nE feHvNV3P5Ki5m3K+bFVrf0ezZd6oywLxrznmgItSnZi0RMmoerNTIT7tpd42u3/a/CO/ tw7TJh+UKpBUOnm6oYqtRFXjo0CTvDaHDnCWFs2JqvvUK2rmgqrvcLTsrIOA+oBONcnN ifJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711465242; x=1712070042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dNSpu6YM8BptgR2qjrv8QihJHcI+7VsMuE3/EFlGmdw=; b=cYE+cCQduQkWfxUErUQF0p9SP2Cs+dU6LQAGFx3IjudtDVKLqvz2lzRd2NGeMMPDWH pe49pJfoY1BV9zkEDUeEEjnMiNO47MwUYkXNY21fK7cG0DmydofGv0uGk8uCSYdHjddj bG/MEUP4fcuYdLJiHVjofsPwWSL5AU6iK1fsPYujqEUtqVCHDWEsEbXxbTksENVs4gaY rK679j0MOViZAA2qIAcdm0mYlTCB3c4mYUE/okg4ylUjYWIOxizD4sEQkDUEn0mM4LX0 f2RVMnfzbLYp4hj9d4xUaWjhh7uOdTZYYIu13uxdgEL3a4Eq2h+ax+LeDFRVO1SBlXA2 B1zQ== X-Forwarded-Encrypted: i=1; AJvYcCVz/szB2lR3/faqW8y69hsY7vhzuPd3TOunbDYubafI4N5si/iM6x4IoPWQJPOCF04NJAXuHw0V8KN+gw9hKXzX1/tbte6VBjcjcCJqCACDLYlHwMF09MnVXlnD04dev8RhwFp25Fabru6iyRBWZJ369Q20VLPLR5pao2wSF9sYKyeQcJG5PQjA X-Gm-Message-State: AOJu0YzvPrNo2b6loLb2cNZgeJ6sVkkHxk0KeIygqEr0txSZmx4oA1g5 Qo758ZhBwZyDEyWYzl3I4jbU20+jfeC/rbd97sdyT4fTQGq+nY/a X-Google-Smtp-Source: AGHT+IG+eQB9Du+89O9YPqZUBHKoPkGBuBszCclR0pKdvZy2gkL+dMe3RVVwPqyf1FUChuKP+urjPg== X-Received: by 2002:a05:6870:5693:b0:222:12dc:8af7 with SMTP id p19-20020a056870569300b0022212dc8af7mr11124988oao.59.1711465242163; Tue, 26 Mar 2024 08:00:42 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (1-34-21-66.hinet-ip.hinet.net. [1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:41 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] ARM: dts: aspeed: Add the AST2600 WDT with SCU register Date: Tue, 26 Mar 2024 23:00:25 +0800 Message-Id: <20240326150027.3015958-3-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The AST2600 Watchdog Timer (WDT) references the System Control Unit (SCU) register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 5f640b7d6b6d..2f7788f2f153 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -558,23 +558,27 @@ uart5: serial@1e784000 { wdt1: watchdog@1e785000 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785000 0x40>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785040 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785040 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt3: watchdog@1e785080 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e785080 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; wdt4: watchdog@1e7850c0 { compatible = "aspeed,ast2600-wdt"; reg = <0x1e7850C0 0x40>; + aspeed,scu = <&syscon>; status = "disabled"; }; From patchwork Tue Mar 26 15:00:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 13604344 Received: from mail-oo1-f48.google.com (mail-oo1-f48.google.com [209.85.161.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CA3D13C9B7; Tue, 26 Mar 2024 15:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.161.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465247; cv=none; b=QesItnVxkVJhG5Uvx+ur4D9MsfIHYNRVnHJOeLq6RyjQMeT85yDe/zbCDOyC6aQzDs7+zz/oOFnnr80TnqaL+bDTsOATGZc0ZBJsbgM8nBzJEoCLJN6r1/0jlOeWYAk2PxjD21YoRPptqinH8fajmhP4RZNVCdRnp6WEw9ZAWAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465247; c=relaxed/simple; bh=uZfnDGW6R8YxxzhmPXNOoQ4C6Vi6QB/c1rE2mdl1BHU=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VdV/Jh9WNwqOtphIHkDyRTaX9r2E7kiGzkmcAysEqV8EDkSKfgMPvcGbBgykRRwk4zqqdypj9zRV+6cNCa9wfMEBMn5TN/0Bgm8QWqBV4Y2h7JdeV4Y4hLvcCGjfUNZuI4rwon5ewQvI2LvgwgA8hmsg0Gan6BRv1JGBEleZw0A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FDyghkxZ; arc=none smtp.client-ip=209.85.161.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FDyghkxZ" Received: by mail-oo1-f48.google.com with SMTP id 006d021491bc7-5a4f9f94e77so3175481eaf.3; Tue, 26 Mar 2024 08:00:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711465245; x=1712070045; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=b9G+01fnYmsgdrsm4iyF3y0ufJf0ihC4vR7iu7tY8Oc=; b=FDyghkxZErRKWH5L8jX19hT8MKBL7kY+Y1/F5qq3oIZfY9n9xJ3yhxbPd1cWuL7W8k UJOWsYIfIc0yqTjcoGjV7CCDiFjho1pyk6TkIz3wGniSt5J+t+/uw9mT4tInQTXu77hw WfoKQZ0UuzXO7MYuVzRYd9Dd9hWaaj1ECA0XK/ImKovRybvA0sea0egAmOulKiK4zPtU AtRDYX6dmJsy2SjvSt3VEh9KSn9EtP1iWaEnAz12I5D6ZedXZ0bLFj/l9+os8soExRf0 F3lWaxEtxsEl2gvUz20vd5AgAFlQuPqvlHwm33mtFpH269gWPmzdDnZ5jRLZNgN0om/a vD3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711465245; x=1712070045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b9G+01fnYmsgdrsm4iyF3y0ufJf0ihC4vR7iu7tY8Oc=; b=XAjgmdWqCfODhbczRhoUeCFVntW1KtXHbYVMCRx7lY7tdQqPuYVTpl+Kmn0gAe9g+t s2dWzk+WuFfA5EDpXBlaqI15u2giovZcmNI45TFnQoWG7GIITJtt7WqaB71YvGjoqXdf wtEXgOQ55lbmM9q+phoqcH5c6BZbNlU942MUkthQITELkkpIIYxY88JfdaTyO7acAhnM y5Qfln9M0epAfzoiNw6KxcfQD8zvO/1oH00Wuag80uqjyiO2O8zf7ja6OhaRI+QTjuJO RP5uM43hhsfXuXJ3l3lokGFJZCsPl1ls6HXTGu1G8zV8SILJ/og7hW54mEZXisi+nUMY NMvw== X-Forwarded-Encrypted: i=1; AJvYcCU9jks7wiucwlvx4Qs1t72IlxrrPw467NHWT0V8bAU5ALU8MI5Ir9DSGLq9FU8QkUnjy96Sby9kDe8Fqsf6brFR7mQ9AaI0AFeEycsdccko+WR/re9L1L05xFLKilafwr+2NTqy6A+jCTG9/eJNsveCPxBCFHB8P0X0CpqS7NQwYuXkHljaiBOL X-Gm-Message-State: AOJu0Yx6ls9gmeF+qMQq4ugTuc/S89+T+P0hHt+qyEH7jmM0/n8aWT/O sGlrOEJDkuy7B/TBYY7NNodOoJcsBGRE/eh/HWKZH1XVmEAVusxR X-Google-Smtp-Source: AGHT+IHN+fopr69FJ89Yh2+C9kaCZwgQMMF/ZNQmyQw3jN0rS6V6fpUrceswbHdxV8p2In3aXxih/w== X-Received: by 2002:a05:6359:4c1b:b0:17f:5a02:e938 with SMTP id kj27-20020a0563594c1b00b0017f5a02e938mr12309821rwc.1.1711465245390; Tue, 26 Mar 2024 08:00:45 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (1-34-21-66.hinet-ip.hinet.net. [1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:44 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: watchdog: aspeed-wdt: Add aspeed,scu Date: Tue, 26 Mar 2024 23:00:26 +0800 Message-Id: <20240326150027.3015958-4-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 To use the SCU register to obtain reset flags for supporting bootstatus. Signed-off-by: Peter Yin --- Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt index 3208adb3e52e..80a1f58b5a2e 100644 --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt @@ -8,6 +8,8 @@ Required properties: - reg: physical base address of the controller and length of memory mapped region + - aspeed,scu: a reference to the System Control Unit node of the Aspeed + SOC. Optional properties: @@ -62,6 +64,7 @@ Examples: reg = <0x1e785000 0x1c>; aspeed,reset-type = "system"; aspeed,external-signal; + aspeed,scu = <&syscon>; }; #include @@ -70,4 +73,5 @@ Examples: reg = <0x1e785040 0x40>; aspeed,reset-mask = ; + aspeed,scu = <&syscon>; }; From patchwork Tue Mar 26 15:00:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Yin X-Patchwork-Id: 13604345 Received: from mail-pf1-f182.google.com (mail-pf1-f182.google.com [209.85.210.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51BC813C82D; Tue, 26 Mar 2024 15:00:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465250; cv=none; b=PiJ5wc2NCX8KtLiiRS+1RHCPxIS7ejQkMhRgaTvxB6cOsTz53ScXuJqY91XQbnM8vGqwnvchKi7OjBBgs+gSWTb75cdqaZBqeUvte/ubRzJE0BoMZOx2DrAfi+CS5JlUomgXrzT/j7QnUoit2eImevqnmphmrplJBSyStBYG7Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711465250; c=relaxed/simple; bh=pdFwi5vtNrKZeNALNYwLixoxGMXi0UyYvxxlVlUCD0M=; h=From:To:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dpkOqHZ9d25a80Qcp4KpCCNU+6FpTWXMV4mTJUod38jEhqAPI+u6J+ORZEAHJ9hp/9D6tURBqiHhH5Gh7EGiURdzOXM9A8p17+k4zgVFeCroeAPaYL9Sk0Hw0s+DJBVywfz+6o/UqxzCFuWQX8qHNudJg9BLQNeNlg/c1PVh0hs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gcyKEEem; arc=none smtp.client-ip=209.85.210.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gcyKEEem" Received: by mail-pf1-f182.google.com with SMTP id d2e1a72fcca58-6ea9a60f7f5so2481670b3a.3; Tue, 26 Mar 2024 08:00:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711465248; x=1712070048; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fxIIBTP4rXppfPhTT/4q0S1EVkuGtE5Ah2bvfj9/Kl4=; b=gcyKEEem0DFob2sI1L0xA6gdTtrEeKTXRMNOy6AmIdu+axpXnt1illAHPVH5ZBEwtR i+Y5vrIgRrk/G56yehIdoMsLOgbMxYYCicMW7UKHaVuwdPRZBoInjcwIzNwSGdn5ZWuc 0A6AQiC6A11UoiQPhXflaZiNpYpc1sHwPXbY60SUnR8R26E0DLhT3Bq7xR0F8/lAV/ut O56TGbe/q6sX+R1MGKCVNqj9nKkLJLMYxVg2Wcvs3vERxDtZOjDNBxk5yf1Ngo97Hv2W uJoz6YjOUmOG74nS2mKcjMxaFhoKiVbxuEDrIIoCGkiiNshYE/2dSowJhCPIwYodsBg0 XQ5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711465248; x=1712070048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fxIIBTP4rXppfPhTT/4q0S1EVkuGtE5Ah2bvfj9/Kl4=; b=xMo/1SmA026zyNvsUZQ6h+FnCYxvj0dPp+krzvLQ0eoM9OodF3+5WuaRO2ygwt9A9l vB0Y9Bz64xLaGSqmMSLaLXwAN0BdHLnvegxYV3cc9LA/W0Sop38k1AFuPggOThiQ2COK YBrIIfDzxuCWA9I2BHtncuMs/aBXH7JlXQ7GnRz8QoilJHBymjvsCEe6F7Psh6m8gOft Pin3DMnkDD2JNqRlwSgJKDP67CZDcAIFr8yWC6Rt50DxEPbpI9DXvrKuxCe2n42ldL82 VKzWunA1dHWVyDE7iyA6Ohl4ZcU89EzyRPrsfsVrRwkHKw1Qp9gIRgM+7XXZWWF27E9/ H9EA== X-Forwarded-Encrypted: i=1; AJvYcCU2eFaWS7wHXOEGdR52axpCbAk7ahZDGKJVEIUaECDvwBWNZFKNDZHkXr6+f488pfCK2qBVpY82ToGkdCQ5yC2QqieIuxRf9Kj3QFznVy2j+CCImXrtqjGgTL/ZIzTcDyEKUEnPTc4LocEJ0/qwJicxNqJOSIyduBo8va191qcf5xhutmaDwW2F X-Gm-Message-State: AOJu0YwMGGeGHAW7dcfY0/RUscoTdSVuiaa0Oyfgaw2y35FkYsVLXq68 RpssDsTPB9Ch6M1z0F5UNawjImAk/iDHDesRjy744iBZimGzR0kL X-Google-Smtp-Source: AGHT+IH1cX47UcVDJeEEPc3BtsiLHnch3pmt/eT/zXRUGHXwiIA0NbF5hbSlAoW8eYDLcPteprOuGw== X-Received: by 2002:a05:6a20:6a22:b0:1a3:c3e6:aef7 with SMTP id p34-20020a056a206a2200b001a3c3e6aef7mr7554771pzk.54.1711465248497; Tue, 26 Mar 2024 08:00:48 -0700 (PDT) Received: from peter-bmc.dhcpserver.bu9bmc.local (1-34-21-66.hinet-ip.hinet.net. [1.34.21.66]) by smtp.gmail.com with ESMTPSA id l27-20020a635b5b000000b005dcbb855530sm7658404pgm.76.2024.03.26.08.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Mar 2024 08:00:48 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus Date: Tue, 26 Mar 2024 23:00:27 +0800 Message-Id: <20240326150027.3015958-5-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> References: <20240326150027.3015958-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-watchdog@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600 Regarding the AST2600 specification, the WDTn Timeout Status Register (WDT10) has bit 1 reserved. Bit 1 of the status register indicates on ast2500 if the boot was from the second boot source. It does not indicate that the most recent reset was triggered by the watchdog. The code should just be changed to set WDIOF_CARDRESET if bit 0 of the status register is set. Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or ast2500 SCU3C when bit1 is set. Signed-off-by: Peter Yin --- drivers/watchdog/aspeed_wdt.c | 53 ++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 16 deletions(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index b4773a6aaf8c..52afc5240b1c 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -11,10 +11,12 @@ #include #include #include +#include #include #include #include #include +#include #include static bool nowayout = WATCHDOG_NOWAYOUT; @@ -65,23 +67,32 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_RELOAD_VALUE 0x04 #define WDT_RESTART 0x08 #define WDT_CTRL 0x0C -#define WDT_CTRL_BOOT_SECONDARY BIT(7) -#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) -#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) -#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) -#define WDT_CTRL_1MHZ_CLK BIT(4) -#define WDT_CTRL_WDT_EXT BIT(3) -#define WDT_CTRL_WDT_INTR BIT(2) -#define WDT_CTRL_RESET_SYSTEM BIT(1) -#define WDT_CTRL_ENABLE BIT(0) +#define WDT_CTRL_BOOT_SECONDARY BIT(7) +#define WDT_CTRL_RESET_MODE_SOC (0x00 << 5) +#define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5) +#define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5) +#define WDT_CTRL_1MHZ_CLK BIT(4) +#define WDT_CTRL_WDT_EXT BIT(3) +#define WDT_CTRL_WDT_INTR BIT(2) +#define WDT_CTRL_RESET_SYSTEM BIT(1) +#define WDT_CTRL_ENABLE BIT(0) #define WDT_TIMEOUT_STATUS 0x10 -#define WDT_TIMEOUT_STATUS_IRQ BIT(2) -#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_IRQ BIT(2) +#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_EVENT BIT(0) #define WDT_CLEAR_TIMEOUT_STATUS 0x14 -#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) #define WDT_RESET_MASK1 0x1c #define WDT_RESET_MASK2 0x20 +/* + * Ast2600 SCU74 bit1 is External reset flag + * Ast2500 SCU3C bit1 is External reset flag + */ +#define EXTERN_RESET_FLAG BIT(1) +#define AST2500_SYSTEM_RESET_EVENT (0x3C) +#define AST2600_SYSTEM_RESET_EVENT (0x74) + /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: @@ -458,15 +469,25 @@ static int aspeed_wdt_probe(struct platform_device *pdev) writel(duration - 1, wdt->base + WDT_RESET_WIDTH); } + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node, + "aspeed,scu"); status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { + if (status & WDT_TIMEOUT_STATUS_EVENT) wdt->wdd.bootstatus = WDIOF_CARDRESET; - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || - of_device_is_compatible(np, "aspeed,ast2500-wdt")) - wdt->wdd.groups = bswitch_groups; + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + regmap_read(scu_base, AST2600_SYSTEM_RESET_EVENT, &status); + } else { + regmap_read(scu_base, AST2500_SYSTEM_RESET_EVENT, &status); + wdt->wdd.groups = bswitch_groups; } + /* + * Reset cause by Extern Reset + */ + if (status & EXTERN_RESET_FLAG) + wdt->wdd.bootstatus |= WDIOF_EXTERN1; + dev_set_drvdata(dev, wdt); return devm_watchdog_register_device(dev, &wdt->wdd);