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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD75.mail.protection.outlook.com (10.167.244.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Wed, 27 Mar 2024 05:43:11 +0000 Received: from chalupa-4a00host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 27 Mar 2024 00:43:09 -0500 From: Manali Shukla To: , CC: , , , , , Subject: [PATCH v1 1/3] KVM: selftests: Add safe_halt() and cli() helpers to common code Date: Wed, 27 Mar 2024 05:42:53 +0000 Message-ID: <20240327054255.24626-2-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327054255.24626-1-manali.shukla@amd.com> References: <20240327054255.24626-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD75:EE_|CH3PR12MB7761:EE_ X-MS-Office365-Filtering-Correlation-Id: d4f7ce94-b90c-4404-aad1-08dc4e20ca09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- .../selftests/kvm/include/x86_64/processor.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/testing/selftests/kvm/include/x86_64/processor.h b/tools/testing/selftests/kvm/include/x86_64/processor.h index 20c9e3b33b07..6de37f6b8ddc 100644 --- a/tools/testing/selftests/kvm/include/x86_64/processor.h +++ b/tools/testing/selftests/kvm/include/x86_64/processor.h @@ -1217,6 +1217,23 @@ static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size, GUEST_ASSERT(!ret); } +/* + * Execute HLT in an STI interrupt shadow to ensure that a pending IRQ that's + * intended to be a wake event arrives *after* HLT is executed. Modern CPUs, + * except for a few oddballs that KVM is unlikely to run on, block IRQs for one + * instruction after STI, *if* RFLAGS.IF=0 before STI. Note, Intel CPUs may + * block other events beyond regular IRQs, e.g. may block NMIs and SMIs too. + */ +static inline void safe_halt(void) +{ + asm volatile("sti; hlt"); +} + +static inline void cli(void) +{ + asm volatile ("cli"); +} + void __vm_xsave_require_permission(uint64_t xfeature, const char *name); #define vm_xsave_require_permission(xfeature) \ From patchwork Wed Mar 27 05:42:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manali Shukla X-Patchwork-Id: 13605582 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2077.outbound.protection.outlook.com [40.107.96.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 813AA12B93; Wed, 27 Mar 2024 05:43:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.96.77 ARC-Seal: i=2; a=rsa-sha256; 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Wed, 27 Mar 2024 05:43:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD7A.mail.protection.outlook.com (10.167.244.59) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Wed, 27 Mar 2024 05:43:11 +0000 Received: from chalupa-4a00host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 27 Mar 2024 00:43:10 -0500 From: Manali Shukla To: , CC: , , , , , Subject: [PATCH v1 2/3] KVM: selftests: Change __vm_create() to create a vm without in-kernel APIC Date: Wed, 27 Mar 2024 05:42:54 +0000 Message-ID: <20240327054255.24626-3-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327054255.24626-1-manali.shukla@amd.com> References: <20240327054255.24626-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7A:EE_|PH7PR12MB7938:EE_ X-MS-Office365-Filtering-Correlation-Id: 8db197ee-3856-467b-8756-08dc4e20ca4d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2024 05:43:11.9141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8db197ee-3856-467b-8756-08dc4e20ca4d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7938 Change __vm_create() to incorporate creation of a vm without in-kernel APIC. Currently, all the vms are created with in-kernel APIC support in KVM selftests because KVM_CREATE_IRQCHIP ioctl is called by default from kvm_arch_vm_post_create(). Add a flag in __vm_create() for a userspace to decide whether to start a vm with in-kernel APIC or without in-kernel APIC. It is a preparatory patch to create a vm without in-kernel APIC support for the KVM_X86_DISABLE_EXITS_HLT test. Signed-off-by: Manali Shukla --- tools/testing/selftests/kvm/dirty_log_test.c | 2 +- tools/testing/selftests/kvm/include/kvm_util_base.h | 4 ++-- tools/testing/selftests/kvm/lib/kvm_util.c | 11 ++++++++--- .../selftests/kvm/x86_64/ucna_injection_test.c | 2 +- 4 files changed, 12 insertions(+), 7 deletions(-) diff --git a/tools/testing/selftests/kvm/dirty_log_test.c b/tools/testing/selftests/kvm/dirty_log_test.c index 6cbecf499767..667a83d67bfe 100644 --- a/tools/testing/selftests/kvm/dirty_log_test.c +++ b/tools/testing/selftests/kvm/dirty_log_test.c @@ -699,7 +699,7 @@ static struct kvm_vm *create_vm(enum vm_guest_mode mode, struct kvm_vcpu **vcpu, pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode)); - vm = __vm_create(VM_SHAPE(mode), 1, extra_mem_pages); + vm = __vm_create(VM_SHAPE(mode), 1, extra_mem_pages, true); log_mode_create_vm_done(vm); *vcpu = vm_vcpu_add(vm, 0, guest_code); diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h index 4a40b332115d..00e37c376cf3 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_base.h +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h @@ -879,7 +879,7 @@ static inline vm_paddr_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, */ struct kvm_vm *____vm_create(struct vm_shape shape); struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, - uint64_t nr_extra_pages); + uint64_t nr_extra_pages, bool is_in_kernel_apic); static inline struct kvm_vm *vm_create_barebones(void) { @@ -900,7 +900,7 @@ static inline struct kvm_vm *vm_create_barebones_protected_vm(void) static inline struct kvm_vm *vm_create(uint32_t nr_runnable_vcpus) { - return __vm_create(VM_SHAPE_DEFAULT, nr_runnable_vcpus, 0); + return __vm_create(VM_SHAPE_DEFAULT, nr_runnable_vcpus, 0, true); } struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus, diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c index adc51b0712ca..9c2a9e216d80 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -354,7 +354,7 @@ static uint64_t vm_nr_pages_required(enum vm_guest_mode mode, } struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, - uint64_t nr_extra_pages) + uint64_t nr_extra_pages, bool is_in_kernel_apic) { uint64_t nr_pages = vm_nr_pages_required(shape.mode, nr_runnable_vcpus, nr_extra_pages); @@ -382,7 +382,12 @@ struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus, slot0 = memslot2region(vm, 0); ucall_init(vm, slot0->region.guest_phys_addr + slot0->region.memory_size); - kvm_arch_vm_post_create(vm); + if (is_in_kernel_apic) { + kvm_arch_vm_post_create(vm); + } else { + sync_global_to_guest(vm, host_cpu_is_intel); + sync_global_to_guest(vm, host_cpu_is_amd); + } return vm; } @@ -415,7 +420,7 @@ struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus, TEST_ASSERT(!nr_vcpus || vcpus, "Must provide vCPU array"); - vm = __vm_create(shape, nr_vcpus, extra_mem_pages); + vm = __vm_create(shape, nr_vcpus, extra_mem_pages, true); for (i = 0; i < nr_vcpus; ++i) vcpus[i] = vm_vcpu_add(vm, i, guest_code); diff --git a/tools/testing/selftests/kvm/x86_64/ucna_injection_test.c b/tools/testing/selftests/kvm/x86_64/ucna_injection_test.c index 0ed32ec903d0..095188562709 100644 --- a/tools/testing/selftests/kvm/x86_64/ucna_injection_test.c +++ b/tools/testing/selftests/kvm/x86_64/ucna_injection_test.c @@ -271,7 +271,7 @@ int main(int argc, char *argv[]) kvm_check_cap(KVM_CAP_MCE); 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Wed, 27 Mar 2024 05:43:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH1PEPF0000AD77.mail.protection.outlook.com (10.167.244.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Wed, 27 Mar 2024 05:43:12 +0000 Received: from chalupa-4a00host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 27 Mar 2024 00:43:11 -0500 From: Manali Shukla To: , CC: , , , , , Subject: [PATCH v1 3/3] KVM: selftests: Add a test case for KVM_X86_DISABLE_EXITS_HLT Date: Wed, 27 Mar 2024 05:42:55 +0000 Message-ID: <20240327054255.24626-4-manali.shukla@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327054255.24626-1-manali.shukla@amd.com> References: <20240327054255.24626-1-manali.shukla@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD77:EE_|DM4PR12MB5866:EE_ X-MS-Office365-Filtering-Correlation-Id: 527d1de0-10e3-4892-894c-08dc4e20cac9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2024 05:43:12.7268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 527d1de0-10e3-4892-894c-08dc4e20cac9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD77.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5866 By default, HLT instruction executed by guest is intercepted by hypervisor. However, KVM_CAP_X86_DISABLE_EXITS capability can be used to not intercept HLT by setting KVM_X86_DISABLE_EXITS_HLT. Add a test case to test KVM_X86_DISABLE_EXITS_HLT functionality. Suggested-by: Sean Christopherson Signed-off-by: Manali Shukla --- tools/testing/selftests/kvm/Makefile | 1 + .../kvm/x86_64/halt_disable_exit_test.c | 113 ++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 tools/testing/selftests/kvm/x86_64/halt_disable_exit_test.c diff --git a/tools/testing/selftests/kvm/Makefile b/tools/testing/selftests/kvm/Makefile index c75251d5c97c..9f72abb95d2e 100644 --- a/tools/testing/selftests/kvm/Makefile +++ b/tools/testing/selftests/kvm/Makefile @@ -89,6 +89,7 @@ TEST_GEN_PROGS_x86_64 += x86_64/set_sregs_test TEST_GEN_PROGS_x86_64 += x86_64/smaller_maxphyaddr_emulation_test TEST_GEN_PROGS_x86_64 += x86_64/smm_test TEST_GEN_PROGS_x86_64 += x86_64/state_test +TEST_GEN_PROGS_x86_64 += x86_64/halt_disable_exit_test TEST_GEN_PROGS_x86_64 += x86_64/vmx_preemption_timer_test TEST_GEN_PROGS_x86_64 += x86_64/svm_vmcall_test TEST_GEN_PROGS_x86_64 += x86_64/svm_int_ctl_test diff --git a/tools/testing/selftests/kvm/x86_64/halt_disable_exit_test.c b/tools/testing/selftests/kvm/x86_64/halt_disable_exit_test.c new file mode 100644 index 000000000000..b7279dd0eaff --- /dev/null +++ b/tools/testing/selftests/kvm/x86_64/halt_disable_exit_test.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * KVM disable halt exit test + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + */ +#include +#include +#include "kvm_util.h" +#include "svm_util.h" +#include "processor.h" +#include "test_util.h" + +pthread_t task_thread, vcpu_thread; +#define SIG_IPI SIGUSR1 + +static void guest_code(uint8_t is_hlt_exec) +{ + while (!READ_ONCE(is_hlt_exec)) + ; + + safe_halt(); + GUEST_DONE(); +} + +static void *task_worker(void *arg) +{ + uint8_t *is_hlt_exec = (uint8_t *)arg; + + usleep(1000); + WRITE_ONCE(*is_hlt_exec, 1); + pthread_kill(vcpu_thread, SIG_IPI); + return 0; +} + +static void *vcpu_worker(void *arg) +{ + int ret; + int sig = -1; + uint8_t *is_hlt_exec = (uint8_t *)arg; + struct kvm_vm *vm; + struct kvm_run *run; + struct kvm_vcpu *vcpu; + struct kvm_signal_mask *sigmask = alloca(offsetof(struct kvm_signal_mask, sigset) + + sizeof(sigset_t)); + sigset_t *sigset = (sigset_t *) &sigmask->sigset; + + /* Create a VM without in kernel APIC support */ + vm = __vm_create(VM_SHAPE_DEFAULT, 1, 0, false); + vm_enable_cap(vm, KVM_CAP_X86_DISABLE_EXITS, KVM_X86_DISABLE_EXITS_HLT); + vcpu = vm_vcpu_add(vm, 0, guest_code); + vcpu_args_set(vcpu, 1, *is_hlt_exec); + + /* + * SIG_IPI is unblocked atomically while in KVM_RUN. It causes the + * ioctl to return with -EINTR, but it is still pending and we need + * to accept it with the sigwait. + */ + sigmask->len = 8; + pthread_sigmask(0, NULL, sigset); + sigdelset(sigset, SIG_IPI); + vcpu_ioctl(vcpu, KVM_SET_SIGNAL_MASK, sigmask); + sigemptyset(sigset); + sigaddset(sigset, SIG_IPI); + run = vcpu->run; + +again: + ret = __vcpu_run(vcpu); + TEST_ASSERT_EQ(errno, EINTR); + + if (ret == -1 && errno == EINTR) { + sigwait(sigset, &sig); + assert(sig == SIG_IPI); + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_INTR); + goto again; + } + + if (run->exit_reason == KVM_EXIT_HLT) + TEST_FAIL("Expected KVM_EXIT_INTR, got KVM_EXIT_HLT"); + + TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO); + kvm_vm_free(vm); + return 0; +} + +int main(int argc, char *argv[]) +{ + int ret; + void *retval; + uint8_t is_halt_exec; + sigset_t sigset; + + TEST_REQUIRE(kvm_has_cap(KVM_CAP_X86_DISABLE_EXITS)); + + /* Ensure that vCPU threads start with SIG_IPI blocked. */ + sigemptyset(&sigset); + sigaddset(&sigset, SIG_IPI); + pthread_sigmask(SIG_BLOCK, &sigset, NULL); + + ret = pthread_create(&vcpu_thread, NULL, vcpu_worker, &is_halt_exec); + TEST_ASSERT(ret == 0, "pthread_create vcpu thread failed errno=%d", errno); + + ret = pthread_create(&task_thread, NULL, task_worker, &is_halt_exec); + TEST_ASSERT(ret == 0, "pthread_create task thread failed errno=%d", errno); + + pthread_join(vcpu_thread, &retval); + TEST_ASSERT(ret == 0, "pthread_join on vcpu thread failed with errno=%d", ret); + + pthread_join(task_thread, &retval); + TEST_ASSERT(ret == 0, "pthread_join on task thread failed with errno=%d", ret); + + return 0; +}