From patchwork Fri Mar 29 00:13:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13609769 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709F8747F; Fri, 29 Mar 2024 00:13:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711671238; cv=none; b=XfEFJ5CTiAAnhm5vuMNTuq2v+T8bE88Fdy6mDXHPwD6lwX+gTQHgoA3rbu+xxMN4Ti8EbYptakE/cr2JTnjXtQA+lPa/hpBjIHW1xwWXu/0iH8ogr6B/1zNa1HpXtsoY4rrBwfzGKmPYZSJoztbbCX1n8laz1dn91cBtsfxS1/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711671238; c=relaxed/simple; bh=JDqU0s6FSirWyIEdcD4KYNY0MDkXzITXMMkssZv+Ci0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CF4Rha4MIgF6A5q8cXoCrllfVu5z8iF5VmqysNEStKZMu9SsSgADu2npdEXKcIolrwB2893UZWEBpFxt6LXLFDAgXhO6GVBNF1VeIJsZe8oUDtFxxfZmMC3/JpoTBPCxlzJh6wgyukrMuMiON8a+BFqS1GwhIAHkzh5lgbAEMOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DoIFU6vi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DoIFU6vi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33CF3C433A6; Fri, 29 Mar 2024 00:13:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711671238; bh=JDqU0s6FSirWyIEdcD4KYNY0MDkXzITXMMkssZv+Ci0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DoIFU6viMdIEQSjd1ljsnK+ZpW0bbV/0JAXzdlCF6cJ+R/ewGKrRxtA3s0HTX7NV7 OFHxkraqGqc44OEgWxZAgvrNZV05+Yl0arDidXk6EM0T69K0X3RuYJvBoygWni/D13 U0fKTM9YdH471HvJ5LiwAMuDgMkdRkq1DBC4GeTkx7eMa/EtZM9Ulw2VYNclDZk4fL QTBTYaFHKnS8zL4QhbkBhARSJrB3K+9A2/jZ4H1ywxAGce4sNE3MTVCyOD6dm6/ZQ2 bzWQkuHWdAMP1GyZ7ofWtn0vO4oZVHW1dKeqMFUt4oGcwXxAYUIca0Uu8PWH0BqPF+ H4pdpA05eePAQ== From: Mark Brown Date: Fri, 29 Mar 2024 00:13:42 +0000 Subject: [PATCH v6 1/5] KVM: arm64: Share all userspace hardened thread data with the hypervisor Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-arm64-2023-dpisa-v6-1-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> In-Reply-To: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5078; i=broonie@kernel.org; h=from:subject:message-id; bh=JDqU0s6FSirWyIEdcD4KYNY0MDkXzITXMMkssZv+Ci0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmBge7EkB6Mfpz5ZYw9vj91uP4suY44c/0Q98N5j4g zzMaKumJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZgYHuwAKCRAk1otyXVSH0LqyB/ 9OffvPdwI5dRB5X9kyU+h1Z0YEVGX9PcGwLXagaEC8Sr0NavGQIBaaZN/8Bwlr/L+xfkAbEsscgkNL 5/GFB+gs2tznIxTxnfp5W+BaFZ05PAzkvcNH1Bbj+guArM7iD013hsOFBIm+acpvFsVfwmXx64b8/v lqd1i3sdG1c8Hwtyi3rH80ZxRx0klE8086uscaiMIlSJQ5PIxjhS318my4VBtzbMjY11TPFrtIEpXk 5IiDF5kGYZtQ5UJHQBmzuOjh13vdGWCH37jJkHNYx3JpfTNJAzSY943AvNAfeRsvYSuWOIJqIuQf2x gxGePTmtHa9uofZPBFfNzIN2G7uowN X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As part of the lazy FPSIMD state transitioning done by the hypervisor we currently share the userpsace FPSIMD state in thread->uw.fpsimd_state with the host. Since this struct is non-extensible userspace ABI we have to keep the definition as is but the addition of FPMR in the 2023 dpISA means that we will want to share more storage with the host. To facilitate this refactor the current code to share the entire thread->uw rather than just the one field. The large number of references to fpsimd_state make it very inconvenient to add an additional wrapper struct. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 3 ++- arch/arm64/include/asm/processor.h | 2 +- arch/arm64/kvm/fpsimd.c | 13 ++++++------- arch/arm64/kvm/hyp/include/hyp/switch.h | 2 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 4 ++-- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 9e8a496fb284..8a251f0da900 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #include #include #include +#include #include #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -640,7 +641,7 @@ struct kvm_vcpu_arch { struct kvm_guest_debug_arch vcpu_debug_state; struct kvm_guest_debug_arch external_debug_state; - struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ + struct thread_struct_uw *host_uw; /* hyp VA */ struct task_struct *parent_task; struct { diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h index f77371232d8c..78781333ee26 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -152,7 +152,7 @@ struct thread_struct { * Maintainers must ensure manually that this contains no * implicit padding. */ - struct { + struct thread_struct_uw { unsigned long tp_value; /* TLS register */ unsigned long tp2_value; u64 fpmr; diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 826307e19e3a..8a0fedbb6f39 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -17,13 +17,13 @@ void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) { struct task_struct *p = vcpu->arch.parent_task; - struct user_fpsimd_state *fpsimd; + struct thread_struct_uw *uw; if (!is_protected_kvm_enabled() || !p) return; - fpsimd = &p->thread.uw.fpsimd_state; - kvm_unshare_hyp(fpsimd, fpsimd + 1); + uw = &p->thread.uw; + kvm_unshare_hyp(uw, uw + 1); put_task_struct(p); } @@ -39,17 +39,16 @@ void kvm_vcpu_unshare_task_fp(struct kvm_vcpu *vcpu) int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu) { int ret; - - struct user_fpsimd_state *fpsimd = ¤t->thread.uw.fpsimd_state; + struct thread_struct_uw *uw = ¤t->thread.uw; kvm_vcpu_unshare_task_fp(vcpu); /* Make sure the host task fpsimd state is visible to hyp: */ - ret = kvm_share_hyp(fpsimd, fpsimd + 1); + ret = kvm_share_hyp(uw, uw + 1); if (ret) return ret; - vcpu->arch.host_fpsimd_state = kern_hyp_va(fpsimd); + vcpu->arch.host_uw = kern_hyp_va(uw); /* * We need to keep current's task_struct pinned until its data has been diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index e3fcf8c4d5b4..a9a11893c191 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -377,7 +377,7 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) /* Write out the host state if it's in the registers */ if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) - __fpsimd_save_state(vcpu->arch.host_fpsimd_state); + __fpsimd_save_state(&(vcpu->arch.host_uw->fpsimd_state)); /* Restore the guest state */ if (sve_guest) diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c index 2385fd03ed87..eb2208009875 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -42,7 +42,7 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) hyp_vcpu->vcpu.arch.fp_state = host_vcpu->arch.fp_state; hyp_vcpu->vcpu.arch.debug_ptr = kern_hyp_va(host_vcpu->arch.debug_ptr); - hyp_vcpu->vcpu.arch.host_fpsimd_state = host_vcpu->arch.host_fpsimd_state; + hyp_vcpu->vcpu.arch.host_uw = host_vcpu->arch.host_uw; hyp_vcpu->vcpu.arch.vsesr_el2 = host_vcpu->arch.vsesr_el2; @@ -64,7 +64,7 @@ static void sync_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vcpu) host_vcpu->arch.fault = hyp_vcpu->vcpu.arch.fault; host_vcpu->arch.iflags = hyp_vcpu->vcpu.arch.iflags; - host_vcpu->arch.fp_state = hyp_vcpu->vcpu.arch.fp_state; + host_vcpu->arch.host_uw = hyp_vcpu->vcpu.arch.host_uw; host_cpu_if->vgic_hcr = hyp_cpu_if->vgic_hcr; for (i = 0; i < hyp_cpu_if->used_lrs; ++i) From patchwork Fri Mar 29 00:13:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13609770 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D53F1097B; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZBtptPS4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6626FC433F1; Fri, 29 Mar 2024 00:13:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711671241; bh=ZafasIdykUQRzTv9jB3X2/BpgZV9b0ujkx1QsU2wROY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ZBtptPS4xr4ntj13FZabRwA4yMMpeR2olu/fuz9M7vwRqDxz5nxE8bZeVfjeBoo02 T6yxnYIINt9pjyQfNPqeqA+q1bdV/iGe0DXM6XT7OMRMWS5teBkbBboS3mlxAMMRme kV5P8pu0juaxLBSiK69MFCqD+1wDiKoQgJWlyPDnzsUnoPgSvB7maYyb5t1Q6NFCHm AzbFa3R1Y6uLmlrw5qzzWo0rtJUWQQrTJMCkHYJy+gSpMahySs/5WNpYBgqjpKsiIX rA638DlYaK+iEVbTUsrs8LdnYfE5A5B29Djh9ucO/S5S4Xaa++Mz5XmGExFUdlMXwI IfZ/wgl8kGCWQ== From: Mark Brown Date: Fri, 29 Mar 2024 00:13:43 +0000 Subject: [PATCH v6 2/5] KVM: arm64: Add newly allocated ID registers to register descriptions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-arm64-2023-dpisa-v6-2-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> In-Reply-To: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1796; i=broonie@kernel.org; h=from:subject:message-id; bh=ZafasIdykUQRzTv9jB3X2/BpgZV9b0ujkx1QsU2wROY=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmBge8CN5tRHW3rA8Bvs8N7qMi+3j8y8mk4z7pHdpR 9S5WNoCJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZgYHvAAKCRAk1otyXVSH0Dy1B/ 9SUa4VUiUG74Rj8TyggAR/LLueU5FDqBOY3ahtZ1KoPZDKuWj/qXQCpbaKTYPp61tya4PX3dwVX2MR cQcA/Usu1uikhE+0yY+ybOgUH9CwBnE3EI5FHbNygvowCEWU+c8xTsa7y+pYSP4kPtbF8q1Gg24vn1 KqGhYXDER/GHwxEPohjNFWFgXoUHrejhFshjolZ+6c0adI8tNJKjI7oOlXyUOfwAmJyiEB12QT6K4F BzrXUOjpoiQeWXGo4oMTGKriNgYohMpWcH5AjCG31886m4fWtJ2DKQizE0lwAIEyY5hsZjfiS1oboG 91NoWFUjR/0DWc2jCZmEgXluAFo8Gn X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions have allocated some new ID registers, add them to the KVM system register descriptions so that they are visible to guests. We make the newly introduced dpISA features writeable, as well as allowing writes to ID_AA64ISAR3_EL1.CPA for FEAT_CPA which only introduces straigforward new instructions with no additional architectural state or traps. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c9f4f387155f..a3c20d1a36aa 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2293,12 +2293,15 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_AA64PFR0_EL1_AdvSIMD | ID_AA64PFR0_EL1_FP), }, ID_SANITISED(ID_AA64PFR1_EL1), - ID_UNALLOCATED(4,2), + ID_WRITABLE(ID_AA64PFR2_EL1, ~(ID_AA64PFR2_EL1_RES0 | + ID_AA64PFR2_EL1_MTEFAR | + ID_AA64PFR2_EL1_MTESTOREONLY | + ID_AA64PFR2_EL1_MTEPERM)), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), ID_HIDDEN(ID_AA64SMFR0_EL1), ID_UNALLOCATED(4,6), - ID_UNALLOCATED(4,7), + ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), /* CRm=5 */ { SYS_DESC(SYS_ID_AA64DFR0_EL1), @@ -2325,7 +2328,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 | ID_AA64ISAR2_EL1_APA3 | ID_AA64ISAR2_EL1_GPA3)), - ID_UNALLOCATED(6,3), + ID_WRITABLE(ID_AA64ISAR3_EL1, ~(ID_AA64ISAR2_EL1_RES0 | + ID_AA64ISAR3_EL1_PACM | + ID_AA64ISAR3_EL1_TLBIW)), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), ID_UNALLOCATED(6,6), From patchwork Fri Mar 29 00:13:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13609771 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDA0112B83; Fri, 29 Mar 2024 00:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711671244; cv=none; b=qE1iomKypBQXCNcQeaWuFOl21dI4epl6D9HHTBqY9+hIT3OpsKtIqKdFYtZF9sDAK05vxifZ5+XSwWfZcNRiZ/v2RAC20B520sFSoiO531M34NaK6b6z9YbDS9/jF4g5tgCo3y/bNpfcutQeYYw5ygng7UylE/etI+fDD4GnKdM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711671244; c=relaxed/simple; bh=TzURQCcdXE/Rwii91k7zKRZL0yNTrQttIJF3XlI51Bk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tt/tNZ+urdc9N21TvPw60+l9x1cMMPyLSD6KnydqD+mZ7VpfzBQw2E4uYMU7eBi9d/TQHqQRLTA8SmkReH3Pbj3S0M43btO/Aq4lDwIQArjaD5eMqp9LeerJR7xJFg2KSKx2LheMGE9bsBvV0Bh+rbsXmCD2WcTNHkTtiF9PTBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L2E+sQXr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L2E+sQXr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9385CC433B1; Fri, 29 Mar 2024 00:14:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711671244; bh=TzURQCcdXE/Rwii91k7zKRZL0yNTrQttIJF3XlI51Bk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=L2E+sQXraEdOfhX2s9ek822i8DJmYqNw+JQlKi1GNGpkTpBRENxt0Qgrk025LTuIu E67cO7v4YY3at0tg+relxPspBCZwvbydm2D2Kt6D41unXQnylkI+PJrRAUmFMqM4I1 jSl6+eCpG0d7T0OaULlIutM1YcarCHKJrwyglVk1VlVWWqqu+GyVCY8aiZBXwwun2+ 7ei3bw7G0MG4TmdSNif1vVRyLEh7mQc8r8O1w1Uyfxvtc/cVHW5uyuHQs6P+9p31fb RLT4e+tHgBavMXUa83Uk9QxdMbpwAODLcDgp2NaRAYAnA1WV6ILSMoKCCp5qzKijoC tc9TTIQ60GbIg== From: Mark Brown Date: Fri, 29 Mar 2024 00:13:44 +0000 Subject: [PATCH v6 3/5] KVM: arm64: Support FEAT_FPMR for guests Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-arm64-2023-dpisa-v6-3-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> In-Reply-To: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5950; i=broonie@kernel.org; h=from:subject:message-id; bh=TzURQCcdXE/Rwii91k7zKRZL0yNTrQttIJF3XlI51Bk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmBge9a6ytdnHHv6IsOV9/3KmwoObVGrmRg1/O2zb5 0oH/4GqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZgYHvQAKCRAk1otyXVSH0LfHB/ 4pIC7S7G54cf6K30Ood+5znP0BciXZDOFr+Nw847igGv/2NPsRtQr4XS5nBoDVEOQkZZC76+fGmzHY OPh8Vt0MCtMZ6usdBXtq3gwb/0DA8st7Z06O27jdJKBXe8Xi7U4jdYte1lud4b60h6FeBQj1o9Mzn7 97BQpAc6plYhSpazTc6sfM9cedHXOJzgJYtGz6cWyWmJJxmqByXEwEQidfgm1mBC/6KYCcxKf9aBqd lnn97AYjBq4BAC3O4tCfKbgokR7WzkrOL+UZDO6G8Mlm82G/UDd2Gv0+E2jBOZT2eppYKOloL2zw3c m1Cwe3qrjGa1Is0abXVmlOIOYqS8Iu X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR introduces a new system register FPMR which allows configuration of floating point behaviour, currently for FP8 specific features. Allow use of this in guests, disabling the trap while guests are running and saving and restoring the value along with the rest of the floating point state if the ID registers indicate that the feature is present. Since FPMR is stored immediately after the main floating point state we share it with the hypervisor by adjusting the size of the shared region. Access to FPMR is covered by both a register specific trap HCRX_EL2.EnFPM and the overall floating point access trap so we just unconditionally enable the FPMR specific trap if the guest has FPMR exposed in the ID registers and rely on the floating point access trap to detect guest floating point usage when FPMR is enabled for the guest. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 3 ++- arch/arm64/kvm/emulate-nested.c | 9 +++++++++ arch/arm64/kvm/fpsimd.c | 2 +- arch/arm64/kvm/hyp/include/hyp/switch.h | 7 ++++++- arch/arm64/kvm/sys_regs.c | 13 +++++++++++++ 5 files changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 8a251f0da900..3f0f31b17d96 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -415,6 +415,8 @@ enum vcpu_sysreg { APGAKEYLO_EL1, APGAKEYHI_EL1, + FPMR, + /* Memory Tagging Extension registers */ RGSR_EL1, /* Random Allocation Tag Seed Register */ GCR_EL1, /* Tag Control Register */ @@ -582,7 +584,6 @@ struct kvm_vcpu_arch { enum fp_type fp_type; unsigned int sve_max_vl; u64 svcr; - u64 fpmr; /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c index 4697ba41b3a9..0289882713f9 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -67,6 +67,8 @@ enum cgt_group_id { CGT_HCR_TTLBIS, CGT_HCR_TTLBOS, + CGT_HCRX_EnFPM, + CGT_MDCR_TPMCR, CGT_MDCR_TPM, CGT_MDCR_TDE, @@ -279,6 +281,12 @@ static const struct trap_bits coarse_trap_bits[] = { .mask = HCR_TTLBOS, .behaviour = BEHAVE_FORWARD_ANY, }, + [CGT_HCRX_EnFPM] = { + .index = HCRX_EL2, + .value = 0, + .mask = HCRX_EL2_EnFPM, + .behaviour = BEHAVE_HANDLE_LOCALLY, + }, [CGT_MDCR_TPMCR] = { .index = MDCR_EL2, .value = MDCR_EL2_TPMCR, @@ -481,6 +489,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { SR_TRAP(SYS_AIDR_EL1, CGT_HCR_TID1), SR_TRAP(SYS_SMIDR_EL1, CGT_HCR_TID1), SR_TRAP(SYS_CTR_EL0, CGT_HCR_TID2), + SR_TRAP(SYS_FPMR, CGT_HCRX_EnFPM), SR_TRAP(SYS_CCSIDR_EL1, CGT_HCR_TID2_TID4), SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4), SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4), diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 8a0fedbb6f39..2f625410c1b7 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -152,7 +152,7 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fp_state.sve_vl = vcpu->arch.sve_max_vl; fp_state.sme_state = NULL; fp_state.svcr = &vcpu->arch.svcr; - fp_state.fpmr = &vcpu->arch.fpmr; + fp_state.fpmr = &__vcpu_sys_reg(vcpu, FPMR); fp_state.fp_type = &vcpu->arch.fp_type; if (vcpu_has_sve(vcpu)) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index a9a11893c191..3d78ab164bab 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -376,10 +376,15 @@ static bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code) isb(); /* Write out the host state if it's in the registers */ - if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) + if (vcpu->arch.fp_state == FP_STATE_HOST_OWNED) { __fpsimd_save_state(&(vcpu->arch.host_uw->fpsimd_state)); + if (cpus_have_final_cap(ARM64_HAS_FPMR)) + vcpu->arch.host_uw->fpmr = read_sysreg_s(SYS_FPMR); + } /* Restore the guest state */ + if (kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR2_EL1, FPMR, IMP)) + write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR); if (sve_guest) __hyp_sve_restore_guest(vcpu); else diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index a3c20d1a36aa..941ad700d0ab 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2068,6 +2068,15 @@ static unsigned int hidden_user_visibility(const struct kvm_vcpu *vcpu, .visibility = hidden_user_visibility, \ } +static unsigned int fpmr_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (kvm_has_feat(vcpu->kvm, ID_AA64PFR2_EL1, FPMR, IMP)) + return 0; + + return REG_HIDDEN; +} + /* * Since reset() callback and field val are not used for idregs, they will be * used for specific purposes for idregs. @@ -2469,6 +2478,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, { SYS_DESC(SYS_CTR_EL0), access_ctr }, { SYS_DESC(SYS_SVCR), undef_access }, + { SYS_DESC(SYS_FPMR), access_rw, reset_unknown, FPMR, + .visibility = fpmr_visibility }, { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr, .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr }, @@ -4054,6 +4065,8 @@ void kvm_init_sysreg(struct kvm_vcpu *vcpu) if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); + if (kvm_has_feat(kvm, ID_AA64PFR2_EL1, FPMR, IMP)) + vcpu->arch.hcrx_el2 |= (HCRX_EL2_EnFPM); } if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) From patchwork Fri Mar 29 00:13:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 13609772 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E78312E48; Fri, 29 Mar 2024 00:14:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711671248; cv=none; b=C5a7t1UyQnOT/GvdTgqJypTH0kko4EvPz/JBZjkvE1c/43Kbh/dSxoMsr4doimg8/6WnqEB3QmdDyj5lr7ijgFs6exPEIIbkBJ387OmcmQEqxSMg+8UDNLbfnMHi2TrZvkG2Z5AEqnhw8k/T17WCZGs5vx2pQ9ymUNHk556lE3I= ARC-Message-Signature: i=1; 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b=nlOV+jLa6Tkf/v8jg9AogiwUdi2BMVz3niqtQI1MnmskhyuxKkCiof+7CGwRQ0Wdt WO5ZEw8ld14UN8EtpMOVUP9JLcKPWcmaxvWaF4vte/81/B1mUoAhsZxl0bLBGhgTem 2c/lC95hnnsng24I3fkrxOf7y4jA/ZaFRRWiBM4Wt8F5OiAhZlsvPPzOJhkshynT8K nVYv3CmJf9EeAtahbN7IBMZ19CS/ApSlMFT0YrMAoWXBdJMwjHobSQDbc9kWRoiaBL RaC/iC9OqRjZc2L2JS//SBfh8m4xQaavaj3uo5BGcJDUk3tamiZBjO810D6NkarvRD FWBsqwMRuNZ8Q== From: Mark Brown Date: Fri, 29 Mar 2024 00:13:45 +0000 Subject: [PATCH v6 4/5] KVM: arm64: selftests: Document feature registers added in 2023 extensions Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-arm64-2023-dpisa-v6-4-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> In-Reply-To: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1469; i=broonie@kernel.org; h=from:subject:message-id; bh=RtrbRWeplo/J+dSChm3CUN1rkk7mxJJmNnU3ySYX5lo=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmBge+s+lkBil5O5ULHYTCu6HqHEpkyLZR2s7CdXxc zwWvNxyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZgYHvgAKCRAk1otyXVSH0IHBB/ 48Gom+Co43qHyYjyopetCX/UN7yiLE0+B13Es7XY35I2YHvjzhk4LSB5/q87XV6DpP02W3A4k4U5TZ 7SsNqis78qg0D/oc3ovJ9RtGdNqMCz4xgBORtywy0MFl5qZTOETxyVnjpoT9VF/JCbRTXd9epR+m7B jHFp6KNS69NdP1oNhN3CEYhW7LBC85c16WufdH9FlFXym/rAZ8IuLx8AuHjgH4TILI7Pj4RwrQd5WZ ArbmVPzlRv94qdw4kRii6Q2FYcUTdMpjwlU/KqvUOUba0+30T/RBLmg1gQw1ccu8UeEf3T1diaYu8U za5MB6Wv+0vF2tdyDX9BixiFsEbm79 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The 2023 architecture extensions allocated some previously usused feature registers, add comments mapping the names in get-reg-list as we do for the other allocated registers. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 709d7d721760..71ea6ecec7ce 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -428,7 +428,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 4, 4), /* ID_AA64ZFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 5), /* ID_AA64SMFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 4, 6), - ARM64_SYS_REG(3, 0, 0, 4, 7), + ARM64_SYS_REG(3, 0, 0, 4, 7), /* ID_AA64FPFR_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 0), /* ID_AA64DFR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 1), /* ID_AA64DFR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 5, 2), @@ -440,7 +440,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 0, 0, 6, 0), /* ID_AA64ISAR0_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 1), /* ID_AA64ISAR1_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 2), /* ID_AA64ISAR2_EL1 */ - ARM64_SYS_REG(3, 0, 0, 6, 3), + ARM64_SYS_REG(3, 0, 0, 6, 3), /* ID_AA64ISAR3_EL1 */ ARM64_SYS_REG(3, 0, 0, 6, 4), ARM64_SYS_REG(3, 0, 0, 6, 5), ARM64_SYS_REG(3, 0, 0, 6, 6), From patchwork Fri Mar 29 00:13:46 2024 Content-Type: text/plain; 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b=cLQxU21nQ++e7XLPoiyXVkxQyFaXloi2Y4Akn+7Hs0tRQ8AIIwqdPwto4bf/HjXKwdi/YBVzKAUQIcuNt6API1rJLQNO84JLM6B7PGNBAc4vi+7IVdz4cCyTz4wQO6uR5wW3Ddfre30GpVsuMYpUgRp/hbyqTS5LWid8aF77+HQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cDpGxoRY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cDpGxoRY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00DAEC433C7; Fri, 29 Mar 2024 00:14:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711671250; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=cDpGxoRYxLjokSzdjyr/XpeJME93UBt6tnftJZ4T9xOVKuDufBc1JIllQnvVnYmCq rx/lZqfrEU0z1yyRPMbiLf3iggfMot6kYdtd1sW6H4c/9Rvvc0R8JsV6hKHSo0H5uR ybcPFdq+49uL7I7a5fSGuun4iOvzrI+Xf7f0Y3+Kj4EAEayQAD6NjQ4fMdW1r4/Bbr jDpLucIYlLtlp0NSYXnDT+vRy3+eyJypFk7diu1AkXTOSAQWvuPNh7dKwMVFYaudJ+ GDtKv9kJUrKjhJDjzg7vBbr4HJK9wBUHffXc3W0Xfu8/S84LBrzhQE2EwJqfwjRk6S VCmPu+AkdbDyA== From: Mark Brown Date: Fri, 29 Mar 2024 00:13:46 +0000 Subject: [PATCH v6 5/5] KVM: arm64: selftests: Teach get-reg-list about FPMR Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-arm64-2023-dpisa-v6-5-ba42db6c27f3@kernel.org> References: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> In-Reply-To: <20240329-arm64-2023-dpisa-v6-0-ba42db6c27f3@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Jonathan Corbet , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Dave Martin , kvmarm@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.14-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1321; i=broonie@kernel.org; h=from:subject:message-id; bh=uwufjRPZpufB4WAKz4BvxO1YI+sO9dPrjMMi385iZbk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBmBge+eqk74AMtUMIBPiwGI+pi1wDTEcHLlC4p4q7p myPQfbeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZgYHvgAKCRAk1otyXVSH0NW5B/ 0TcU6VavkFfCBJ8vGg2RX9vZ4t77ShVUFmfqiEzDq+KrtNcMcCRhCD6mQXTT/JcxC1Fa6P/PPFjApS fFaHMzOG+YHH0ngniUKKS/oLfDAK0z++QRPzBKHLZPzeb3t0Amcim7X703CJdZLdN+bivsNFzkgcqD zVgJPTVIrRdEE68SOE/l2KZgFuNqa8YT4v2wEHHG942seRV3ovb6Nt3UmWz1P6w1YRgpxWq+xflPVb 1m4RMvSuUwHBEIOLmV4qA0QWlRPEE0gUF+hJIduSa8qLmxJEdxHN/0JRRR86TDzL82F3AJvX308o8V /lE+aiJZcM3rN2ebnTtAOrIAl8XjMQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB FEAT_FPMR defines a new register FMPR which is available at all ELs and is discovered via ID_AA64PFR2_EL1.FPMR, add this to the set of registers that get-reg-list knows to check for with the required identification register depdendency. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/aarch64/get-reg-list.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/testing/selftests/kvm/aarch64/get-reg-list.c b/tools/testing/selftests/kvm/aarch64/get-reg-list.c index 71ea6ecec7ce..1e43511d1440 100644 --- a/tools/testing/selftests/kvm/aarch64/get-reg-list.c +++ b/tools/testing/selftests/kvm/aarch64/get-reg-list.c @@ -40,6 +40,12 @@ static struct feature_id_reg feat_id_regs[] = { ARM64_SYS_REG(3, 0, 0, 7, 3), /* ID_AA64MMFR3_EL1 */ 4, 1 + }, + { + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ + ARM64_SYS_REG(3, 0, 0, 4, 2), /* ID_AA64PFR2_EL1 */ + 32, + 1 } }; @@ -481,6 +487,7 @@ static __u64 base_regs[] = { ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ ARM64_SYS_REG(3, 4, 3, 0, 0), /* DACR32_EL2 */ + ARM64_SYS_REG(3, 3, 4, 4, 2), /* FPMR */ ARM64_SYS_REG(3, 4, 5, 0, 1), /* IFSR32_EL2 */ ARM64_SYS_REG(3, 4, 5, 3, 0), /* FPEXC32_EL2 */ };