From patchwork Fri Mar 29 05:33:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ho-Ren (Jack) Chuang" X-Patchwork-Id: 13610125 Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA7603BBE0 for ; Fri, 29 Mar 2024 05:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711690445; cv=none; b=TTQnJ3NczrwyqpjdcXFql12GHOhyF5g1vzLB2gVMMaP/7jl2Calzp0kWno+y2abV37iZplfSf7Qy4HgM1hnZESApoR2blsCM0/g+7Vb9+cZjIWm22PpkxwOyvqUvC1Pjh/4V57TdiRAnB32vr4eJpZiNKAXpD1byJiXZdGashKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711690445; c=relaxed/simple; bh=vXOLrurzWw91h7eYCw90ZLDHh+I4uNd31lHySo7hGYw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NO8MuP9+fKzTSe2gCFsgFPjrqgGbn6xnaZGN3fsTSsR+cKKrKV4xFMxZnvG4KRG9E9MGqqdqkF3lb4PYvyxYTAPbJ1eAWykT0SXiewx6yVHM3miqpmujKgtPRfzli8xBZiyH15O6t0k6yAlBuq6z0dX6PMXU48ccvHpsh2iFI1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=bXflVEPL; arc=none smtp.client-ip=209.85.222.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="bXflVEPL" Received: by mail-qk1-f180.google.com with SMTP id af79cd13be357-789f00aba19so121549785a.0 for ; Thu, 28 Mar 2024 22:34:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1711690442; x=1712295242; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nM2K0D/X61aNkdsdtPeKZ1y9TeOUsh6nA3RvZQfcaBY=; b=bXflVEPLQ+A1BJRus3mNTT6dGPpE1nMMZBKku5KksFRp4Rtd6GEQqzDR4QITylAKLc S4as70RdVtid3zclSQFicLDsjs4ENQ2/0BmPT8+igfUVmGnhVuhiE3Sx7LY3hPNF4MUu YSKztKqmCQzOttN2K9jKsQhDZIVUh55OzmsCy7ud5LBcLeGgXg4LkRQsRFH556QnHUck OVStMKDn5zXCi/H5XOeMmANfldG5m+Z5fHs4UhFdmwmKeeBLLreGypTjmkVb93nGQwsp eGb5rnLeRtDHguXOtWz6cudz9R6stKUjkKRSxWwhsPS125J5Ml0iB7O7rxSq6YOy0NMz fuvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711690442; x=1712295242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nM2K0D/X61aNkdsdtPeKZ1y9TeOUsh6nA3RvZQfcaBY=; b=gc0xwzJTqserARNbvbjT2gaEFZEmHlEdLp2DFi/+wdQ6XEg+x7Z8ms6l8cBhgFWI+W 7xbWM1lTIX2nPME5m4QBHdoZHLx4lFh43SRa3r29/5qiHwBeUteBCxgXTxZNo4Y1hroG 0BKxvO/2L77kckGrzMTNuuJmi5p985+V/VHKct3qiN+sKmd5lWZxks3gwzcS0FYRVg5E SUsJEofg24QSPm5AKnjwBrEHAvjwjNPrYUYkRWNs80S2IclXpWCiia+vFca8rD4cGUEw n+GppqihDlw95roOFt6CxbOMc+eeWbV8kGVcLcDcJ567lmJhp7fn3UYXMRkmuGwdc6fU GVLg== X-Forwarded-Encrypted: i=1; AJvYcCXqlxx4UEuFpmIC9iSUk0aG4QFvkYKO8/orez1hE8qKuO12vVrmgBBvglMp4/ZlsoQHbW+ofIR5ZDcUER91xGTQPw2/YHYtG6bF X-Gm-Message-State: AOJu0YwqYctgK5IzKaXxNPwaOCjWtRCpAi5TBnfcDH/rD2T8TMCsio+s EXaUSJjE1TYL7MKLkh/Jj+2GblDS+aYcyeV7HjmJX19ZOJC/9SXrhIvKbGrjvTg= X-Google-Smtp-Source: AGHT+IFNoqNydjaxWSpQbLOw9NSrhWxbMGVfkX5oUHJM8lI3o7LuokzE9FNy1hUFSqYBfeSHSyDMdw== X-Received: by 2002:a05:622a:10:b0:431:756b:c48f with SMTP id x16-20020a05622a001000b00431756bc48fmr1092286qtw.27.1711690441708; Thu, 28 Mar 2024 22:34:01 -0700 (PDT) Received: from n231-228-171.byted.org ([147.160.184.85]) by smtp.gmail.com with ESMTPSA id jd25-20020a05622a719900b00430bf59ebccsm1293700qtb.11.2024.03.28.22.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 22:34:01 -0700 (PDT) From: "Ho-Ren (Jack) Chuang" To: "Huang, Ying" , "Gregory Price" , aneesh.kumar@linux.ibm.com, mhocko@suse.com, tj@kernel.org, john@jagalactic.com, "Eishan Mirakhur" , "Vinicius Tavares Petrucci" , "Ravis OpenSrc" , "Alistair Popple" , "Srinivasulu Thanneeru" , Dan Williams , Vishal Verma , Dave Jiang , Andrew Morton , nvdimm@lists.linux.dev, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , qemu-devel@nongnu.org Subject: [PATCH v9 1/2] memory tier: dax/kmem: introduce an abstract layer for finding, allocating, and putting memory types Date: Fri, 29 Mar 2024 05:33:52 +0000 Message-Id: <20240329053353.309557-2-horenchuang@bytedance.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240329053353.309557-1-horenchuang@bytedance.com> References: <20240329053353.309557-1-horenchuang@bytedance.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Since different memory devices require finding, allocating, and putting memory types, these common steps are abstracted in this patch, enhancing the scalability and conciseness of the code. Signed-off-by: Ho-Ren (Jack) Chuang Reviewed-by: "Huang, Ying" --- drivers/dax/kmem.c | 20 ++------------------ include/linux/memory-tiers.h | 13 +++++++++++++ mm/memory-tiers.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/dax/kmem.c b/drivers/dax/kmem.c index 42ee360cf4e3..01399e5b53b2 100644 --- a/drivers/dax/kmem.c +++ b/drivers/dax/kmem.c @@ -55,21 +55,10 @@ static LIST_HEAD(kmem_memory_types); static struct memory_dev_type *kmem_find_alloc_memory_type(int adist) { - bool found = false; struct memory_dev_type *mtype; mutex_lock(&kmem_memory_type_lock); - list_for_each_entry(mtype, &kmem_memory_types, list) { - if (mtype->adistance == adist) { - found = true; - break; - } - } - if (!found) { - mtype = alloc_memory_type(adist); - if (!IS_ERR(mtype)) - list_add(&mtype->list, &kmem_memory_types); - } + mtype = mt_find_alloc_memory_type(adist, &kmem_memory_types); mutex_unlock(&kmem_memory_type_lock); return mtype; @@ -77,13 +66,8 @@ static struct memory_dev_type *kmem_find_alloc_memory_type(int adist) static void kmem_put_memory_types(void) { - struct memory_dev_type *mtype, *mtn; - mutex_lock(&kmem_memory_type_lock); - list_for_each_entry_safe(mtype, mtn, &kmem_memory_types, list) { - list_del(&mtype->list); - put_memory_type(mtype); - } + mt_put_memory_types(&kmem_memory_types); mutex_unlock(&kmem_memory_type_lock); } diff --git a/include/linux/memory-tiers.h b/include/linux/memory-tiers.h index 69e781900082..a44c03c2ba3a 100644 --- a/include/linux/memory-tiers.h +++ b/include/linux/memory-tiers.h @@ -48,6 +48,9 @@ int mt_calc_adistance(int node, int *adist); int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, const char *source); int mt_perf_to_adistance(struct access_coordinate *perf, int *adist); +struct memory_dev_type *mt_find_alloc_memory_type(int adist, + struct list_head *memory_types); +void mt_put_memory_types(struct list_head *memory_types); #ifdef CONFIG_MIGRATION int next_demotion_node(int node); void node_get_allowed_targets(pg_data_t *pgdat, nodemask_t *targets); @@ -136,5 +139,15 @@ static inline int mt_perf_to_adistance(struct access_coordinate *perf, int *adis { return -EIO; } + +struct memory_dev_type *mt_find_alloc_memory_type(int adist, struct list_head *memory_types) +{ + return NULL; +} + +void mt_put_memory_types(struct list_head *memory_types) +{ + +} #endif /* CONFIG_NUMA */ #endif /* _LINUX_MEMORY_TIERS_H */ diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 0537664620e5..974af10cfdd8 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -623,6 +623,38 @@ void clear_node_memory_type(int node, struct memory_dev_type *memtype) } EXPORT_SYMBOL_GPL(clear_node_memory_type); +struct memory_dev_type *mt_find_alloc_memory_type(int adist, struct list_head *memory_types) +{ + bool found = false; + struct memory_dev_type *mtype; + + list_for_each_entry(mtype, memory_types, list) { + if (mtype->adistance == adist) { + found = true; + break; + } + } + if (!found) { + mtype = alloc_memory_type(adist); + if (!IS_ERR(mtype)) + list_add(&mtype->list, memory_types); + } + + return mtype; +} +EXPORT_SYMBOL_GPL(mt_find_alloc_memory_type); + +void mt_put_memory_types(struct list_head *memory_types) +{ + struct memory_dev_type *mtype, *mtn; + + list_for_each_entry_safe(mtype, mtn, memory_types, list) { + list_del(&mtype->list); + put_memory_type(mtype); + } +} +EXPORT_SYMBOL_GPL(mt_put_memory_types); + static void dump_hmem_attrs(struct access_coordinate *coord, const char *prefix) { pr_info( From patchwork Fri Mar 29 05:33:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ho-Ren (Jack) Chuang" X-Patchwork-Id: 13610126 Received: from mail-qt1-f182.google.com (mail-qt1-f182.google.com [209.85.160.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 022B33C6AB for ; Fri, 29 Mar 2024 05:34:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711690445; cv=none; b=pBHzGg4E3BiTTSn256JTLeMfxt0ImZSn01884fO2jrk5rKPR1czr9uPb2ETrIeOIzJEc/TEOgI7FqdXnkZ/3qAc17v16104oiGzIw8hd5yy+zDEWYGzgF90aWC0PK016iK/3nrF35A9z7FsthhxBUxlANDGa0T+61rz6S3OKzng= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711690445; c=relaxed/simple; bh=PaZ2AF3JeHPXJZBphflXd5DZx1k2kc8EgFP2kYGmJq0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oIYF772M7WllKeHRe+ghgR7MBFCipkTeDvUBPUz0OCJ7iNGGnBMRFqrHVu3LzTtCmuk6nDAau70HrmdLZZo+FKflT+aLnyTG23oJIMqAebW9WEycvOD+Q1dZ7yf1XbUAL4N+6exvkaedHWG/PsvrnljhRinOLT9jk+DIeBdAebU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=Quuohvzn; arc=none smtp.client-ip=209.85.160.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="Quuohvzn" Received: by mail-qt1-f182.google.com with SMTP id d75a77b69052e-430a25ed4e7so11429421cf.0 for ; Thu, 28 Mar 2024 22:34:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1711690443; x=1712295243; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7gywZcWj8Uy1UfLQdLtf6937dGqAomoCBcBBPX1Jltg=; b=QuuohvznFwRoWdk62/GkZ6/WdN7+IQfhXFmEc71VzxK39sr60qHAAG6d+b/95S/Jgq YnmRUUOfm/qZvywwCbDGixgB3f+00iEceCJYDGvkHH/UwuhxgV5MXDDb1PznHVvaFqP1 6HzrymG12F6LhM/g6TWMNciK+6k9s21NlSr3dK8tVA6AZABlE55NW/ydZAqgekne2lxh T1DTxpJARwmyObnJgKM4LSyiQh/O3E2ZF3fDK7Y9cReZxXyqc9lnbcfIYUFm3y/A9/6f XNUfUefwu7faMUZ1LICWZNgXT5+lfHSWoQVaVBXAqc6eG0oe7NenqwWw4R7Po3sjRFZi 5juw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711690443; x=1712295243; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7gywZcWj8Uy1UfLQdLtf6937dGqAomoCBcBBPX1Jltg=; b=doBe8bdue4kIDPOpNouk3XNQMV1mAPugktJwP84Pmpo34oPbAdhuhkBzvhdNLK9JM5 AXw7UUScAOjPmOu9E8OMt9G/9solB/D8DCQgPdfJAkGULxLOrnOyw7EhlXa/VcLnhVzv SHYzEaXRaMdqLiNHC+ZnPeXPgNtmCMAEEWFQBebOE3xlAU3oHwJpeUkrNizMWjbZQoqr tR6LQ1oizg/3VKGn1Ns/VxPxCKhKnJvOLeOdgVfIikKQlmjHQ6FKsGLyw06lQffFYa+w S9IfUGLQ2dYtk5PENVYZPSSDGhalwR99PNpGfR2KmWBNDABkCJuvI35GR9VVWxfeGBMz Pp+Q== X-Forwarded-Encrypted: i=1; AJvYcCX6cl3dlLQ2jbo45ifgA2lt+zaOtaMykglWuXoUgZ+BZeV/KCekWfEyUkA585e6m1xUoYr/vm3/MA2souZPVXzSNDODom8GI5W0 X-Gm-Message-State: AOJu0YzehdQyyEyWpRLFc6qdjK31eSDYQN5IYhA2q+hVnxaSlgoTLpkU QlQ/5z5Q92EwST4e+v6I8BhoKFSR/A0t4gBOBGtzGz1nbXY1Gel0lPMeWIJJB+o= X-Google-Smtp-Source: AGHT+IHMKi8jQpAaT6v24K2SIK8/4KC+bbaOA6pAb143bozl04FLNTZDjzodC6fB+ReD22deVOL3iA== X-Received: by 2002:a05:622a:5e89:b0:432:c1b3:7985 with SMTP id er9-20020a05622a5e8900b00432c1b37985mr849659qtb.55.1711690442938; Thu, 28 Mar 2024 22:34:02 -0700 (PDT) Received: from n231-228-171.byted.org ([147.160.184.85]) by smtp.gmail.com with ESMTPSA id jd25-20020a05622a719900b00430bf59ebccsm1293700qtb.11.2024.03.28.22.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 22:34:02 -0700 (PDT) From: "Ho-Ren (Jack) Chuang" To: "Huang, Ying" , "Gregory Price" , aneesh.kumar@linux.ibm.com, mhocko@suse.com, tj@kernel.org, john@jagalactic.com, "Eishan Mirakhur" , "Vinicius Tavares Petrucci" , "Ravis OpenSrc" , "Alistair Popple" , "Srinivasulu Thanneeru" , Dan Williams , Vishal Verma , Dave Jiang , Andrew Morton , nvdimm@lists.linux.dev, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org Cc: "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , "Ho-Ren (Jack) Chuang" , qemu-devel@nongnu.org, Hao Xiang Subject: [PATCH v9 2/2] memory tier: create CPUless memory tiers after obtaining HMAT info Date: Fri, 29 Mar 2024 05:33:53 +0000 Message-Id: <20240329053353.309557-3-horenchuang@bytedance.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20240329053353.309557-1-horenchuang@bytedance.com> References: <20240329053353.309557-1-horenchuang@bytedance.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The current implementation treats emulated memory devices, such as CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory (E820_TYPE_RAM). However, these emulated devices have different characteristics than traditional DRAM, making it important to distinguish them. Thus, we modify the tiered memory initialization process to introduce a delay specifically for CPUless NUMA nodes. This delay ensures that the memory tier initialization for these nodes is deferred until HMAT information is obtained during the boot process. Finally, demotion tables are recalculated at the end. * late_initcall(memory_tier_late_init); Some device drivers may have initialized memory tiers between `memory_tier_init()` and `memory_tier_late_init()`, potentially bringing online memory nodes and configuring memory tiers. They should be excluded in the late init. * Handle cases where there is no HMAT when creating memory tiers There is a scenario where a CPUless node does not provide HMAT information. If no HMAT is specified, it falls back to using the default DRAM tier. * Introduce another new lock `default_dram_perf_lock` for adist calculation In the current implementation, iterating through CPUlist nodes requires holding the `memory_tier_lock`. However, `mt_calc_adistance()` will end up trying to acquire the same lock, leading to a potential deadlock. Therefore, we propose introducing a standalone `default_dram_perf_lock` to protect `default_dram_perf_*`. This approach not only avoids deadlock but also prevents holding a large lock simultaneously. * Upgrade `set_node_memory_tier` to support additional cases, including default DRAM, late CPUless, and hot-plugged initializations. To cover hot-plugged memory nodes, `mt_calc_adistance()` and `mt_find_alloc_memory_type()` are moved into `set_node_memory_tier()` to handle cases where memtype is not initialized and where HMAT information is available. * Introduce `default_memory_types` for those memory types that are not initialized by device drivers. Because late initialized memory and default DRAM memory need to be managed, a default memory type is created for storing all memory types that are not initialized by device drivers and as a fallback. Signed-off-by: Ho-Ren (Jack) Chuang Signed-off-by: Hao Xiang Reviewed-by: "Huang, Ying" --- mm/memory-tiers.c | 93 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 77 insertions(+), 16 deletions(-) diff --git a/mm/memory-tiers.c b/mm/memory-tiers.c index 974af10cfdd8..9f8ae99e8e6e 100644 --- a/mm/memory-tiers.c +++ b/mm/memory-tiers.c @@ -36,6 +36,11 @@ struct node_memory_type_map { static DEFINE_MUTEX(memory_tier_lock); static LIST_HEAD(memory_tiers); +/* + * The list is used to store all memory types that are not created + * by a device driver. + */ +static LIST_HEAD(default_memory_types); static struct node_memory_type_map node_memory_types[MAX_NUMNODES]; struct memory_dev_type *default_dram_type; @@ -108,6 +113,8 @@ static struct demotion_nodes *node_demotion __read_mostly; static BLOCKING_NOTIFIER_HEAD(mt_adistance_algorithms); +/* The lock is used to protect `default_dram_perf*` info and nid. */ +static DEFINE_MUTEX(default_dram_perf_lock); static bool default_dram_perf_error; static struct access_coordinate default_dram_perf; static int default_dram_perf_ref_nid = NUMA_NO_NODE; @@ -505,7 +512,8 @@ static inline void __init_node_memory_type(int node, struct memory_dev_type *mem static struct memory_tier *set_node_memory_tier(int node) { struct memory_tier *memtier; - struct memory_dev_type *memtype; + struct memory_dev_type *mtype = default_dram_type; + int adist = MEMTIER_ADISTANCE_DRAM; pg_data_t *pgdat = NODE_DATA(node); @@ -514,11 +522,20 @@ static struct memory_tier *set_node_memory_tier(int node) if (!node_state(node, N_MEMORY)) return ERR_PTR(-EINVAL); - __init_node_memory_type(node, default_dram_type); + mt_calc_adistance(node, &adist); + if (node_memory_types[node].memtype == NULL) { + mtype = mt_find_alloc_memory_type(adist, &default_memory_types); + if (IS_ERR(mtype)) { + mtype = default_dram_type; + pr_info("Failed to allocate a memory type. Fall back.\n"); + } + } + + __init_node_memory_type(node, mtype); - memtype = node_memory_types[node].memtype; - node_set(node, memtype->nodes); - memtier = find_create_memory_tier(memtype); + mtype = node_memory_types[node].memtype; + node_set(node, mtype->nodes); + memtier = find_create_memory_tier(mtype); if (!IS_ERR(memtier)) rcu_assign_pointer(pgdat->memtier, memtier); return memtier; @@ -655,6 +672,33 @@ void mt_put_memory_types(struct list_head *memory_types) } EXPORT_SYMBOL_GPL(mt_put_memory_types); +/* + * This is invoked via `late_initcall()` to initialize memory tiers for + * CPU-less memory nodes after driver initialization, which is + * expected to provide `adistance` algorithms. + */ +static int __init memory_tier_late_init(void) +{ + int nid; + + mutex_lock(&memory_tier_lock); + for_each_node_state(nid, N_MEMORY) + if (node_memory_types[nid].memtype == NULL) + /* + * Some device drivers may have initialized memory tiers + * between `memory_tier_init()` and `memory_tier_late_init()`, + * potentially bringing online memory nodes and + * configuring memory tiers. Exclude them here. + */ + set_node_memory_tier(nid); + + establish_demotion_targets(); + mutex_unlock(&memory_tier_lock); + + return 0; +} +late_initcall(memory_tier_late_init); + static void dump_hmem_attrs(struct access_coordinate *coord, const char *prefix) { pr_info( @@ -668,7 +712,7 @@ int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, { int rc = 0; - mutex_lock(&memory_tier_lock); + mutex_lock(&default_dram_perf_lock); if (default_dram_perf_error) { rc = -EIO; goto out; @@ -716,23 +760,30 @@ int mt_set_default_dram_perf(int nid, struct access_coordinate *perf, } out: - mutex_unlock(&memory_tier_lock); + mutex_unlock(&default_dram_perf_lock); return rc; } int mt_perf_to_adistance(struct access_coordinate *perf, int *adist) { - if (default_dram_perf_error) - return -EIO; + int rc = 0; - if (default_dram_perf_ref_nid == NUMA_NO_NODE) - return -ENOENT; + mutex_lock(&default_dram_perf_lock); + if (default_dram_perf_error) { + rc = -EIO; + goto out; + } if (perf->read_latency + perf->write_latency == 0 || - perf->read_bandwidth + perf->write_bandwidth == 0) - return -EINVAL; + perf->read_bandwidth + perf->write_bandwidth == 0) { + rc = -EINVAL; + goto out; + } - mutex_lock(&memory_tier_lock); + if (default_dram_perf_ref_nid == NUMA_NO_NODE) { + rc = -ENOENT; + goto out; + } /* * The abstract distance of a memory node is in direct proportion to * its memory latency (read + write) and inversely proportional to its @@ -745,8 +796,9 @@ int mt_perf_to_adistance(struct access_coordinate *perf, int *adist) (default_dram_perf.read_latency + default_dram_perf.write_latency) * (default_dram_perf.read_bandwidth + default_dram_perf.write_bandwidth) / (perf->read_bandwidth + perf->write_bandwidth); - mutex_unlock(&memory_tier_lock); +out: + mutex_unlock(&default_dram_perf_lock); return 0; } EXPORT_SYMBOL_GPL(mt_perf_to_adistance); @@ -858,7 +910,8 @@ static int __init memory_tier_init(void) * For now we can have 4 faster memory tiers with smaller adistance * than default DRAM tier. */ - default_dram_type = alloc_memory_type(MEMTIER_ADISTANCE_DRAM); + default_dram_type = mt_find_alloc_memory_type(MEMTIER_ADISTANCE_DRAM, + &default_memory_types); if (IS_ERR(default_dram_type)) panic("%s() failed to allocate default DRAM tier\n", __func__); @@ -868,6 +921,14 @@ static int __init memory_tier_init(void) * types assigned. */ for_each_node_state(node, N_MEMORY) { + if (!node_state(node, N_CPU)) + /* + * Defer memory tier initialization on CPUless numa nodes. + * These will be initialized after firmware and devices are + * initialized. + */ + continue; + memtier = set_node_memory_tier(node); if (IS_ERR(memtier)) /*