From patchwork Fri Mar 29 09:09:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7F2DACD128D for ; Fri, 29 Mar 2024 09:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Z1VlhGP0TMfyMLYVB2pv49h8qU6xdMOqA9jNc1HVnQA=; b=D9kXZ0ZOrorixG jMqE65d49DLvVeXDCMybr/3U4uEd2Sifx+vyRNnykpyasSYq2fMsY3dYQddHG0ZmjUL7YV+SFOGzs NqYGORLqUeu+zNCG0fRs/OFNm07zt7zXLfxlQ+4zb6lMRipaSf+mxh3NsQYoO/mWK+4rD0wo0aXkH A707SQaVWkknxrxkOsF9wYWpfVM9XVjsLS5gisufuPRtFgJMLzDq16nGLRpq78AjNtfclA44T/oEW czMJNzos9VIyu+xQPjradZTrGLFJWbFFYn9o7/7NGc84bWL+DHmYC1DxaR6wZdOEoHXJWEVVPDEx0 wjQjXBl89MN63X6I1fVA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FF-0000000HQ2v-1hbk; Fri, 29 Mar 2024 09:09:53 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FC-0000000HQ0Z-3mzv for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:09:52 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id E1B9F618EF; Fri, 29 Mar 2024 09:09:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8A3CAC43390; Fri, 29 Mar 2024 09:09:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703389; bh=YJFivpKCi3PodyQK+czq2eSUstzDiwXAIfoJ+H7Xdxk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Y6iBPl1iH4gV5Dy9NQL6CY8mSuTlK+OwobIzeUjUTtwprvqNKRD8jLoZP0tg57fk8 vrUjNtWvx4YLoSmSH/Mk8PwQHhQOe3uAbVbAjvq8hdc5zC8WngXwuyBWiJbWa7tLNV rjCx/jcAYGm4eEAIMjKychDCztjhDSqTY4busletVzSdTPug6XIhncbqpCXIMWBpVp Abb18gCmxkOKyahbo0jjPAtWZRNeQBOxMkKjMqOM+ST08nzHcwFhYGTM7D8ibbbyIs Y3NOCnUzBgDb1sYU9ZYrx+qtBuy1zQwdaLwaHcFk1zgRS3Iw6frZ/KM4IyZH4M+S8i Qi36bdRoAmnXA== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 01/19] PCI: endpoint: Introduce pci_epc_check_func() Date: Fri, 29 Mar 2024 18:09:27 +0900 Message-ID: <20240329090945.1097609-2-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020951_136072_3585678C X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Introduce the small epc core helper function pci_epc_check_func() to check that an epc pointer, a physical function number and a virtual function number are all valid. This avoids repeating the code pattern: if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) return err; if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) return err; in many functions of the endpoint controller core code. Signed-off-by: Damien Le Moal --- drivers/pci/endpoint/pci-epc-core.c | 78 +++++++++++------------------ 1 file changed, 30 insertions(+), 48 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index da3fc0795b0b..26fe2c255fc9 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -126,6 +126,17 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features } EXPORT_SYMBOL_GPL(pci_epc_get_next_free_bar); +static bool pci_epc_check_func(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) + return false; + + if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + return false; + + return true; +} + /** * pci_epc_get_features() - get the features supported by EPC * @epc: the features supported by *this* EPC device will be returned @@ -143,10 +154,7 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc, { const struct pci_epc_features *epc_features; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return NULL; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return NULL; if (!epc->ops->get_features) @@ -216,10 +224,7 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, { int ret; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return -EINVAL; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; if (!epc->ops->raise_irq) @@ -260,10 +265,7 @@ int pci_epc_map_msi_irq(struct pci_epc *epc, u8 func_no, u8 vfunc_no, { int ret; - if (IS_ERR_OR_NULL(epc)) - return -EINVAL; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; if (!epc->ops->map_msi_irq) @@ -291,10 +293,7 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { int interrupt; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return 0; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return 0; if (!epc->ops->get_msi) @@ -327,11 +326,10 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 vfunc_no, u8 interrupts) int ret; u8 encode_int; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || - interrupts < 1 || interrupts > 32) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (interrupts < 1 || interrupts > 32) return -EINVAL; if (!epc->ops->set_msi) @@ -359,10 +357,7 @@ int pci_epc_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) { int interrupt; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return 0; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return 0; if (!epc->ops->get_msix) @@ -395,11 +390,10 @@ int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no, { int ret; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || - interrupts < 1 || interrupts > 2048) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (interrupts < 1 || interrupts > 2048) return -EINVAL; if (!epc->ops->set_msix) @@ -426,10 +420,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_msix); void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, phys_addr_t phys_addr) { - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return; if (!epc->ops->unmap_addr) @@ -457,10 +448,7 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, { int ret; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return -EINVAL; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; if (!epc->ops->map_addr) @@ -487,12 +475,11 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr); void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar) { - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || - (epf_bar->barno == BAR_5 && - epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return; - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (epf_bar->barno == BAR_5 && + epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) return; if (!epc->ops->clear_bar) @@ -519,18 +506,16 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, int ret; int flags = epf_bar->flags; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions || - (epf_bar->barno == BAR_5 && - flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || + if (!pci_epc_check_func(epc, func_no, vfunc_no)) + return -EINVAL; + + if ((epf_bar->barno == BAR_5 && flags & PCI_BASE_ADDRESS_MEM_TYPE_64) || (flags & PCI_BASE_ADDRESS_SPACE_IO && flags & PCI_BASE_ADDRESS_IO_MASK) || (upper_32_bits(epf_bar->size) && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))) return -EINVAL; - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) - return -EINVAL; - if (!epc->ops->set_bar) return 0; @@ -559,10 +544,7 @@ int pci_epc_write_header(struct pci_epc *epc, u8 func_no, u8 vfunc_no, { int ret; - if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions) - return -EINVAL; - - if (vfunc_no > 0 && (!epc->max_vfs || vfunc_no > epc->max_vfs[func_no])) + if (!pci_epc_check_func(epc, func_no, vfunc_no)) return -EINVAL; /* Only Virtual Function #1 has deviceID */ From patchwork Fri Mar 29 09:09:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10373CD1288 for ; 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Fri, 29 Mar 2024 09:09:56 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FE-0000000HQ1O-03EA for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:09:53 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 7178961710; Fri, 29 Mar 2024 09:09:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 12B86C433F1; Fri, 29 Mar 2024 09:09:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703391; bh=qCEbulFduSNumMtAvNmv8e5o53wv9ou11qaVvfYDl1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cUcoX29lxqP3o/uu5GkmylQ2N850ka0wERjw1dqVGb49wl7di7Chx0LGV2MOCRhbf YqKB3lJs/srqXgJ5ESNp6dZ3FaLEnHfd+pvParjPRNtUsxYI28M4he6fNjxH8gGHLU H7df1HYmk4+ztyZJNKs1EjUUKhQczPTNjirJVWAMAuMHc9MeH93nnv3IyBo0uDnm+s 7EqxmefJG217c4x1jln5dUCW03VRDdAiYRD3BQ7Z75YOdfz5LvQ0dKDfKTyiedV1+N 4wQszNQW/LElYGRNMZr9hT4j6WO/z4uUWXtfYFpRQxIxUnLDx4ZraHS11pnJymWiy3 9ywVSWSZXFotQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 02/19] PCI: endpoint: Improve pci_epc_mem_alloc_addr() Date: Fri, 29 Mar 2024 18:09:28 +0900 Message-ID: <20240329090945.1097609-3-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020952_153860_B270FAE5 X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org There is no point in attempting to allocate memory from an endpoint controller memory window if the requested size is larger than the window size. Add a check to skip bitmap_find_free_region() calls for such case. Also change the final return to return NULL to simplify the code. Signed-off-by: Damien Le Moal --- drivers/pci/endpoint/pci-epc-mem.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c index a9c028f58da1..218a60e945db 100644 --- a/drivers/pci/endpoint/pci-epc-mem.c +++ b/drivers/pci/endpoint/pci-epc-mem.c @@ -178,7 +178,7 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_exit); void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, phys_addr_t *phys_addr, size_t size) { - void __iomem *virt_addr = NULL; + void __iomem *virt_addr; struct pci_epc_mem *mem; unsigned int page_shift; size_t align_size; @@ -188,10 +188,13 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, for (i = 0; i < epc->num_windows; i++) { mem = epc->windows[i]; - mutex_lock(&mem->lock); + if (size > mem->window.size) + continue; + align_size = ALIGN(size, mem->window.page_size); order = pci_epc_mem_get_order(mem, align_size); + mutex_lock(&mem->lock); pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order); if (pageno >= 0) { @@ -211,7 +214,7 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, mutex_unlock(&mem->lock); } - return virt_addr; + return NULL; } EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr); From patchwork Fri Mar 29 09:09:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610374 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2D9AAC6FD1F for ; Fri, 29 Mar 2024 09:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 29 Mar 2024 09:09:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703392; bh=BFWNyOZga4bcF5IwhtlimJOyalVsQSzj1z8KDBtoQk8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g5t9DWKLosSQH9ud7qXS14biEt5tBCjkCB1xpa1Q/V7JbeU3xrJngQsDyJzVZDWza T5PsiosTNPn1XVjxyHzcvBmLHOTJU3G1WUfUDiMU426UVc8ayFPMhFzNLfaKSpQAsH FqLwleY67q8sDA2BJ3Rl6PZc3F6YMnGj7X96lsnvmk5aL8SKSg6eWEuSxN703TdyCl catY8WMKBqtIMXjelf52O9PAbVcBTlbJC2rl1eblEepseRw+NRXi3VHg9ug1F4BQ/0 i43xlrRju4pTpZPPYFuXk3rYG63SBS8DjAaBm9SwHqtcsS/TpvyXuXYJQo0Y/wxeqv cx/qnDiindB+g== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 03/19] PCI: endpoint: Introduce pci_epc_map_align() Date: Fri, 29 Mar 2024 18:09:29 +0900 Message-ID: <20240329090945.1097609-4-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020953_648384_B4700DE2 X-CRM114-Status: GOOD ( 27.48 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Some endpoint controllers have requirements on the alignment of the controller physical memory address that must be used to map a RC PCI address region. For instance, the rockchip endpoint controller uses at most the lower 20 bits of a physical memory address region as the lower bits of an RC PCI address. For mapping a PCI address region of size bytes starting from pci_addr, the exact number of address bits used is the number of address bits changing in the address range [pci_addr..pci_addr + size - 1]. For this example, this creates the following constraints: 1) The offset into the controller physical memory allocated for a mapping depends on the mapping size *and* the starting PCI address for the mapping. 2) A mapping size cannot exceed the controller windows size (1MB) minus the offset needed into the allocated physical memory, which can end up being a smaller size than the desired mapping size. Handling these constraints independently of the controller being used in a PCI EP function driver is not possible with the current EPC API as it only provides the ->align field in struct pci_epc_features. Furthermore, this alignment is static and does not depend on a mapping pci address and size. Solve this by introducing the function pci_epc_map_align() and the endpoint controller operation ->map_align to allow endpoint function drivers to obtain the size and the offset into a controller address region that must be used to map an RC PCI address region. The size of the physical address region provided by pci_epc_map_align() can then be used as the size argument for the function pci_epc_mem_alloc_addr(). The offset into the allocated controller memory can be used to correctly handle data transfers. Of note is that pci_epc_map_align() may indicate upon return a mapping size that is smaller (but not 0) than the requested PCI address region size. For such case, an endpoint function driver must handle data transfers in fragments. The controller operation ->map_align is optional: controllers that do not have any address alignment constraints for mapping a RC PCI address region do not need to implement this operation. For such controllers, pci_epc_map_align() always returns the mapping size as equal to the requested size and an offset equal to 0. The structure pci_epc_map is introduced to represent a mapping start PCI address, size and the size and offset into the controller memory needed for mapping the PCI address region. Signed-off-by: Damien Le Moal --- drivers/pci/endpoint/pci-epc-core.c | 66 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 33 +++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index 26fe2c255fc9..f558b333f842 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -432,6 +432,72 @@ void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_unmap_addr); +/** + * pci_epc_map_align() - Get the offset into and the size of a controller memory + * address region needed to map a RC PCI address region + * @epc: the EPC device on which address is allocated + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @pci_addr: PCI address to which the physical address should be mapped + * @size: the size of the mapping starting from @pci_addr + * @map: populate here the actual size and offset into the controller memory + * that must be allocated for the mapping + * + * Invoke the controller map_align operation to obtain the size and the offset + * into a controller address region that must be allocated to map @size + * bytes of the RC PCI address space starting from @pci_addr. + * + * The size of the mapping that can be handled by the controller is indicated + * using the pci_size field of @map. This size may be smaller than the requested + * @size. In such case, the function driver must handle the mapping using + * several fragments. The offset into the controller memory for the effective + * mapping of the @pci_addr..@pci_addr+@map->pci_size address range is indicated + * using the map_ofst field of @map. + */ +int pci_epc_map_align(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + u64 pci_addr, size_t size, struct pci_epc_map *map) +{ + const struct pci_epc_features *features; + size_t mask; + int ret; + + if (!pci_epc_check_func(epc, func_no, vfunc_no)) + return -EINVAL; + + if (!size || !map) + return -EINVAL; + + memset(map, 0, sizeof(*map)); + map->pci_addr = pci_addr; + map->pci_size = size; + + if (epc->ops->map_align) { + mutex_lock(&epc->lock); + ret = epc->ops->map_align(epc, func_no, vfunc_no, map); + mutex_unlock(&epc->lock); + return ret; + } + + /* + * Assume a fixed alignment constraint as specified by the controller + * features. + */ + features = pci_epc_get_features(epc, func_no, vfunc_no); + if (!features || !features->align) { + map->map_pci_addr = pci_addr; + map->map_size = size; + map->map_ofst = 0; + } + + mask = features->align - 1; + map->map_pci_addr = map->pci_addr & ~mask; + map->map_ofst = map->pci_addr & mask; + map->map_size = ALIGN(map->map_ofst + map->pci_size, features->align); + + return 0; +} +EXPORT_SYMBOL_GPL(pci_epc_map_align); + /** * pci_epc_map_addr() - map CPU address to PCI address * @epc: the EPC device on which address is allocated diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index cc2f70d061c8..8cfb4aaf2628 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -32,11 +32,40 @@ pci_epc_interface_string(enum pci_epc_interface_type type) } } +/** + * struct pci_epc_map - information about EPC memory for mapping a RC PCI + * address range + * @pci_addr: start address of the RC PCI address range to map + * @pci_size: size of the RC PCI address range to map + * @map_pci_addr: RC PCI address used as the first address mapped + * @map_size: size of the controller memory needed for the mapping + * @map_ofst: offset into the controller memory needed for the mapping + * @phys_base: base physical address of the allocated EPC memory + * @phys_addr: physical address at which @pci_addr is mapped + * @virt_base: base virtual address of the allocated EPC memory + * @virt_addr: virtual address at which @pci_addr is mapped + */ +struct pci_epc_map { + phys_addr_t pci_addr; + size_t pci_size; + + phys_addr_t map_pci_addr; + size_t map_size; + phys_addr_t map_ofst; + + phys_addr_t phys_base; + phys_addr_t phys_addr; + void __iomem *virt_base; + void __iomem *virt_addr; +}; + /** * struct pci_epc_ops - set of function pointers for performing EPC operations * @write_header: ops to populate configuration space header * @set_bar: ops to configure the BAR * @clear_bar: ops to reset the BAR + * @map_align: operation to get the size and offset into a controller memory + * window needed to map an RC PCI address region * @map_addr: ops to map CPU address to PCI address * @unmap_addr: ops to unmap CPU address and PCI address * @set_msi: ops to set the requested number of MSI interrupts in the MSI @@ -61,6 +90,8 @@ struct pci_epc_ops { struct pci_epf_bar *epf_bar); void (*clear_bar)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar); + int (*map_align)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epc_map *map); int (*map_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, phys_addr_t addr, u64 pci_addr, size_t size); void (*unmap_addr)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, @@ -234,6 +265,8 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar); void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epf_bar *epf_bar); +int pci_epc_map_align(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + u64 pci_addr, size_t size, struct pci_epc_map *map); int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, phys_addr_t phys_addr, u64 pci_addr, size_t size); From patchwork Fri Mar 29 09:09:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A7AB4C6FD1F for ; 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Fri, 29 Mar 2024 09:09:59 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FG-0000000HQ1O-2QZX for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:09:55 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 68D1B618EF; Fri, 29 Mar 2024 09:09:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1918CC43390; Fri, 29 Mar 2024 09:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703394; bh=HKiMTB0O7fIx/S5BlFDhoWZQHCueYyMiVzbKw6x++gs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ji+oGXyrtlvfIQ3j1ohmds6ftLT/Z9FNG1wS8AlN9LIoTSjxCcffjR8K7SaDTY9So ymfeHkrbkg9sCxAifM+bmJHWBcEDp4LO7zxTAZGuuB7/WpJWlaiwo9hIGf401C2zWj lqYeoNE4+HYAh8v+s7prkujTr4pvXkizlZvDOp7V2FIoAahBhnSw8nQrxnkvNyPD6Z JBnKQkdqG2kJlVxjSjX/SDp8/CBNMIZaMjx6Yygn6JxBZu0lXI3bgyTRrskzUMHUUS 7gcj6bH4veBPGTMN0yxWsm2xVYWRXmKGyHqaFGXB5PvK1hT7kzPf60PGBm549yn8Vv crLeTc+DymbjQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 04/19] PCI: endpoint: Introduce pci_epc_mem_map()/unmap() Date: Fri, 29 Mar 2024 18:09:30 +0900 Message-ID: <20240329090945.1097609-5-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020954_759336_49E5D444 X-CRM114-Status: GOOD ( 17.99 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Introduce the function pci_epc_mem_map() to facilitate controller memory address allocation and mapping to a RC PCI address region in endpoint function drivers. This function first uses pci_epc_map_align() to determine the controller memory address alignment (offset and size) constraints. The result of this function is used to allocate a controller physical memory region using pci_epc_mem_alloc_addr() and map it to the RC PCI address space with pci_epc_map_addr(). Since pci_epc_map_align() may indicate that a mapping can be smaller than the requested size, pci_epc_mem_map() may only partially map the RC PCI address region specified and return a smaller size for the effective mapping. The counterpart of pci_epc_mem_map() to unmap and free the controller memory address region is pci_epc_mem_unmap(). Both functions operate using struct pci_epc_map data structure which is extended to contain the physical and virtual addresses of the allocated controller memory. Endpoint function drivers can use struct pci_epc_map to implement read/write accesses within the mapped RC PCI address region using the ->virt_addr and ->size fields. Co-developed-by: Rick Wertenbroek Signed-off-by: Damien Le Moal --- drivers/pci/endpoint/pci-epc-core.c | 68 +++++++++++++++++++++++++++++ include/linux/pci-epc.h | 6 +++ 2 files changed, 74 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index f558b333f842..539196c602cb 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -529,6 +529,74 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_map_addr); +/** + * pci_epc_mem_map() - allocate and map CPU address to PCI address + * @epc: the EPC device on which the CPU address is to be allocated and mapped + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @pci_addr: PCI address to which the CPU address should be mapped + * @size: the number of bytes to map starting from @pci_addr + * @map: where to return the mapping information + * + * Allocate a controller physical address region and map it to a RC PCI address + * region, taking into account the controller physical address mapping + * constraints (if any). Returns the effective size of the mapping, which may + * be less than @size, or a negative error code in case of error. + */ +ssize_t pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + u64 pci_addr, size_t size, struct pci_epc_map *map) +{ + int ret; + + ret = pci_epc_map_align(epc, func_no, vfunc_no, pci_addr, size, map); + if (ret) + return ret; + + map->virt_base = pci_epc_mem_alloc_addr(epc, &map->phys_base, + map->map_size); + if (!map->virt_base) + return -ENOMEM; + + map->phys_addr = map->phys_base + map->map_ofst; + map->virt_addr = map->virt_base + map->map_ofst; + + ret = pci_epc_map_addr(epc, func_no, vfunc_no, map->phys_base, + map->map_pci_addr, map->map_size); + if (ret) { + pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base, + map->map_size); + return ret; + } + + return map->pci_size; +} +EXPORT_SYMBOL_GPL(pci_epc_mem_map); + +/** + * pci_epc_mem_unmap() - unmap from PCI address and free a CPU address region + * @epc: the EPC device on which the CPU address is allocated and mapped + * @func_no: the physical endpoint function number in the EPC device + * @vfunc_no: the virtual endpoint function number in the physical function + * @map: the mapping information + * + * Allocate and map local CPU address to a PCI address, accounting for the + * controller local CPU address alignement constraints. + */ +void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epc_map *map) +{ + if (!pci_epc_check_func(epc, func_no, vfunc_no)) + return; + + if (!map || !map->pci_size) + return; + + pci_epc_unmap_addr(epc, func_no, vfunc_no, map->phys_base); + pci_epc_mem_free_addr(epc, map->phys_base, map->virt_base, + map->map_size); +} +EXPORT_SYMBOL_GPL(pci_epc_mem_unmap); + /** * pci_epc_clear_bar() - reset the BAR * @epc: the EPC device for which the BAR has to be cleared diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 8cfb4aaf2628..86397a500b54 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -304,4 +304,10 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc, phys_addr_t *phys_addr, size_t size); void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr, void __iomem *virt_addr, size_t size); + +ssize_t pci_epc_mem_map(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + u64 pci_addr, size_t size, struct pci_epc_map *map); +void pci_epc_mem_unmap(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epc_map *map); + #endif /* __LINUX_PCI_EPC_H */ From patchwork Fri Mar 29 09:09:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610521 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7E45DCD11DD for ; Fri, 29 Mar 2024 10:19:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FlXj87lwpFgc6l+ASDetaGJ2FkMxIrzF1gm+ef/10uw=; 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Fri, 29 Mar 2024 09:09:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703395; bh=HDumR+C0lGN+JmG5mxEWg0Dd7ELkE1gQie7RsRRWKzI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PeUc/VWvO2BQY1C6JHf5nQACYVjsO9egRZ29oduBQ3wreQDnCm5unUqkUompH6/SD WLXamtYw8bzsFRQN2cR1jz9O48+kaq1qME1j7DMtA1QisA+8EZO9DdQQdFKEIQKNiU UwfeLf9QFQq8lV5Z1kfSnfe0OFeD7jVIrsjI3VrsJGzoeII+GrDdSR5XspyVBI6uYY kcOlmZql5G8CUUIEXWa6t0tU3yviSvQoIn8u5S7xvS9FJTuwAURuItmUwRRJQGihyh pCljMy2MURZlgGHQxVdl87jocKeKYime/cN03fEPcoUvSSkhhJgl8KJ+t1uzbsrXO4 +k2W7Q45t8PDQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 05/19] PCI: endpoint: test: Use pci_epc_mem_map/unmap() Date: Fri, 29 Mar 2024 18:09:31 +0900 Message-ID: <20240329090945.1097609-6-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020957_037372_8E0B2399 X-CRM114-Status: GOOD ( 16.58 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Modify the endpoint test driver to use the functions pci_epc_mem_map() and pci_epc_mem_unmap() for the read, write and copy tests. For each test case, the transfer (dma or mmio) are executed in a loop to ensure that potentially partial mappings returned by pci_epc_mem_map() are correctly handled. Signed-off-by: Damien Le Moal --- drivers/pci/endpoint/functions/pci-epf-test.c | 378 +++++++++--------- 1 file changed, 197 insertions(+), 181 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index cd4ffb39dcdc..0e285e539538 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -317,91 +317,94 @@ static void pci_epf_test_print_rate(struct pci_epf_test *epf_test, static void pci_epf_test_copy(struct pci_epf_test *epf_test, struct pci_epf_test_reg *reg) { - int ret; - void __iomem *src_addr; - void __iomem *dst_addr; - phys_addr_t src_phys_addr; - phys_addr_t dst_phys_addr; + int ret = 0; struct timespec64 start, end; struct pci_epf *epf = epf_test->epf; - struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; + struct pci_epc_map src_map, dst_map; + u64 src_addr = reg->src_addr; + u64 dst_addr = reg->dst_addr; + size_t copy_size = reg->size; + ssize_t map_size = 0; + void *copy_buf = NULL, *buf; - src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size); - if (!src_addr) { - dev_err(dev, "Failed to allocate source address\n"); - reg->status = STATUS_SRC_ADDR_INVALID; - ret = -ENOMEM; - goto err; - } - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr, - reg->src_addr, reg->size); - if (ret) { - dev_err(dev, "Failed to map source address\n"); - reg->status = STATUS_SRC_ADDR_INVALID; - goto err_src_addr; - } - - dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size); - if (!dst_addr) { - dev_err(dev, "Failed to allocate destination address\n"); - reg->status = STATUS_DST_ADDR_INVALID; - ret = -ENOMEM; - goto err_src_map_addr; - } - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr, - reg->dst_addr, reg->size); - if (ret) { - dev_err(dev, "Failed to map destination address\n"); - reg->status = STATUS_DST_ADDR_INVALID; - goto err_dst_addr; - } - - ktime_get_ts64(&start); if (reg->flags & FLAG_USE_DMA) { if (epf_test->dma_private) { dev_err(dev, "Cannot transfer data using DMA\n"); ret = -EINVAL; - goto err_map_addr; + goto set_status; } - - ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr, - src_phys_addr, reg->size, 0, - DMA_MEM_TO_MEM); - if (ret) - dev_err(dev, "Data transfer failed\n"); } else { - void *buf; - - buf = kzalloc(reg->size, GFP_KERNEL); - if (!buf) { + copy_buf = kzalloc(copy_size, GFP_KERNEL); + if (!copy_buf) { ret = -ENOMEM; - goto err_map_addr; + goto set_status; } - - memcpy_fromio(buf, src_addr, reg->size); - memcpy_toio(dst_addr, buf, reg->size); - kfree(buf); + buf = copy_buf; } - ktime_get_ts64(&end); - pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start, &end, - reg->flags & FLAG_USE_DMA); -err_map_addr: - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, dst_phys_addr); + while (copy_size) { + map_size = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no, + src_addr, copy_size, &src_map); + if (map_size < 0) { + dev_err(dev, "Failed to map source address\n"); + reg->status = STATUS_SRC_ADDR_INVALID; + ret = map_size; + goto free_buf; + } + + map_size = pci_epc_mem_map(epf->epc, epf->func_no, epf->vfunc_no, + dst_addr, copy_size, &dst_map); + if (map_size < 0) { + dev_err(dev, "Failed to map destination address\n"); + reg->status = STATUS_DST_ADDR_INVALID; + ret = map_size; + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, + &src_map); + goto free_buf; + } + + map_size = min_t(size_t, map_size, src_map.pci_size); + + ktime_get_ts64(&start); + if (reg->flags & FLAG_USE_DMA) { + ret = pci_epf_test_data_transfer(epf_test, + dst_map.phys_addr, src_map.phys_addr, + map_size, 0, DMA_MEM_TO_MEM); + if (ret) { + dev_err(dev, "Data transfer failed\n"); + goto unmap; + } + } else { + memcpy_fromio(buf, src_map.virt_addr, map_size); + memcpy_toio(dst_map.virt_addr, buf, map_size); + buf += map_size; + } + ktime_get_ts64(&end); + + copy_size -= map_size; + src_addr += map_size; + dst_addr += map_size; -err_dst_addr: - pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size); + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &dst_map); + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &src_map); + map_size = 0; + } -err_src_map_addr: - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, src_phys_addr); + pci_epf_test_print_rate(epf_test, "COPY", reg->size, &start, + &end, reg->flags & FLAG_USE_DMA); + +unmap: + if (map_size) { + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &dst_map); + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &src_map); + } -err_src_addr: - pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size); +free_buf: + kfree(copy_buf); -err: +set_status: if (!ret) reg->status |= STATUS_COPY_SUCCESS; else @@ -411,82 +414,89 @@ static void pci_epf_test_copy(struct pci_epf_test *epf_test, static void pci_epf_test_read(struct pci_epf_test *epf_test, struct pci_epf_test_reg *reg) { - int ret; - void __iomem *src_addr; - void *buf; + int ret = 0; + void *src_buf, *buf; u32 crc32; - phys_addr_t phys_addr; + struct pci_epc_map map; phys_addr_t dst_phys_addr; struct timespec64 start, end; struct pci_epf *epf = epf_test->epf; - struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; struct device *dma_dev = epf->epc->dev.parent; + u64 src_addr = reg->src_addr; + size_t src_size = reg->size; + ssize_t map_size = 0; - src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); - if (!src_addr) { - dev_err(dev, "Failed to allocate address\n"); - reg->status = STATUS_SRC_ADDR_INVALID; + src_buf = kzalloc(src_size, GFP_KERNEL); + if (!src_buf) { ret = -ENOMEM; - goto err; - } - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr, - reg->src_addr, reg->size); - if (ret) { - dev_err(dev, "Failed to map address\n"); - reg->status = STATUS_SRC_ADDR_INVALID; - goto err_addr; - } - - buf = kzalloc(reg->size, GFP_KERNEL); - if (!buf) { - ret = -ENOMEM; - goto err_map_addr; + goto set_status; } + buf = src_buf; + + while (src_size) { + map_size = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no, + src_addr, src_size, &map); + if (map_size < 0) { + dev_err(dev, "Failed to map address\n"); + reg->status = STATUS_SRC_ADDR_INVALID; + ret = map_size; + goto free_buf; + } - if (reg->flags & FLAG_USE_DMA) { - dst_phys_addr = dma_map_single(dma_dev, buf, reg->size, - DMA_FROM_DEVICE); - if (dma_mapping_error(dma_dev, dst_phys_addr)) { - dev_err(dev, "Failed to map destination buffer addr\n"); - ret = -ENOMEM; - goto err_dma_map; + if (reg->flags & FLAG_USE_DMA) { + dst_phys_addr = dma_map_single(dma_dev, buf, map_size, + DMA_FROM_DEVICE); + if (dma_mapping_error(dma_dev, dst_phys_addr)) { + dev_err(dev, + "Failed to map destination buffer addr\n"); + ret = -ENOMEM; + goto unmap; + } + + ktime_get_ts64(&start); + ret = pci_epf_test_data_transfer(epf_test, + dst_phys_addr, map.phys_addr, + map_size, src_addr, DMA_DEV_TO_MEM); + if (ret) + dev_err(dev, "Data transfer failed\n"); + ktime_get_ts64(&end); + + dma_unmap_single(dma_dev, dst_phys_addr, map_size, + DMA_FROM_DEVICE); + + if (ret) + goto unmap; + } else { + ktime_get_ts64(&start); + memcpy_fromio(buf, map.virt_addr, map_size); + ktime_get_ts64(&end); } - ktime_get_ts64(&start); - ret = pci_epf_test_data_transfer(epf_test, dst_phys_addr, - phys_addr, reg->size, - reg->src_addr, DMA_DEV_TO_MEM); - if (ret) - dev_err(dev, "Data transfer failed\n"); - ktime_get_ts64(&end); + src_size -= map_size; + src_addr += map_size; + buf += map_size; - dma_unmap_single(dma_dev, dst_phys_addr, reg->size, - DMA_FROM_DEVICE); - } else { - ktime_get_ts64(&start); - memcpy_fromio(buf, src_addr, reg->size); - ktime_get_ts64(&end); + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map); + map_size = 0; } - pci_epf_test_print_rate(epf_test, "READ", reg->size, &start, &end, - reg->flags & FLAG_USE_DMA); + pci_epf_test_print_rate(epf_test, "READ", reg->size, &start, + &end, reg->flags & FLAG_USE_DMA); - crc32 = crc32_le(~0, buf, reg->size); + crc32 = crc32_le(~0, src_buf, reg->size); if (crc32 != reg->checksum) ret = -EIO; -err_dma_map: - kfree(buf); +unmap: + if (map_size) + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map); -err_map_addr: - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr); +free_buf: + kfree(src_buf); -err_addr: - pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size); - -err: +set_status: if (!ret) reg->status |= STATUS_READ_SUCCESS; else @@ -496,71 +506,79 @@ static void pci_epf_test_read(struct pci_epf_test *epf_test, static void pci_epf_test_write(struct pci_epf_test *epf_test, struct pci_epf_test_reg *reg) { - int ret; - void __iomem *dst_addr; - void *buf; - phys_addr_t phys_addr; + int ret = 0; + void *dst_buf, *buf; + struct pci_epc_map map; phys_addr_t src_phys_addr; struct timespec64 start, end; struct pci_epf *epf = epf_test->epf; - struct device *dev = &epf->dev; struct pci_epc *epc = epf->epc; + struct device *dev = &epf->dev; struct device *dma_dev = epf->epc->dev.parent; + u64 dst_addr = reg->dst_addr; + size_t dst_size = reg->size; + ssize_t map_size = 0; - dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size); - if (!dst_addr) { - dev_err(dev, "Failed to allocate address\n"); - reg->status = STATUS_DST_ADDR_INVALID; + dst_buf = kzalloc(dst_size, GFP_KERNEL); + if (!dst_buf) { ret = -ENOMEM; - goto err; + goto set_status; } - - ret = pci_epc_map_addr(epc, epf->func_no, epf->vfunc_no, phys_addr, - reg->dst_addr, reg->size); - if (ret) { - dev_err(dev, "Failed to map address\n"); - reg->status = STATUS_DST_ADDR_INVALID; - goto err_addr; - } - - buf = kzalloc(reg->size, GFP_KERNEL); - if (!buf) { - ret = -ENOMEM; - goto err_map_addr; - } - - get_random_bytes(buf, reg->size); - reg->checksum = crc32_le(~0, buf, reg->size); - - if (reg->flags & FLAG_USE_DMA) { - src_phys_addr = dma_map_single(dma_dev, buf, reg->size, - DMA_TO_DEVICE); - if (dma_mapping_error(dma_dev, src_phys_addr)) { - dev_err(dev, "Failed to map source buffer addr\n"); - ret = -ENOMEM; - goto err_dma_map; + get_random_bytes(dst_buf, dst_size); + reg->checksum = crc32_le(~0, dst_buf, dst_size); + buf = dst_buf; + + while (dst_size) { + map_size = pci_epc_mem_map(epc, epf->func_no, epf->vfunc_no, + dst_addr, dst_size, &map); + if (map_size < 0) { + dev_err(dev, "Failed to map address\n"); + reg->status = STATUS_DST_ADDR_INVALID; + ret = map_size; + goto free_buf; } - ktime_get_ts64(&start); + if (reg->flags & FLAG_USE_DMA) { + src_phys_addr = dma_map_single(dma_dev, buf, map_size, + DMA_TO_DEVICE); + if (dma_mapping_error(dma_dev, src_phys_addr)) { + dev_err(dev, + "Failed to map source buffer addr\n"); + ret = -ENOMEM; + goto unmap; + } + + ktime_get_ts64(&start); + + ret = pci_epf_test_data_transfer(epf_test, + map.phys_addr, src_phys_addr, + map_size, dst_addr, + DMA_MEM_TO_DEV); + if (ret) + dev_err(dev, "Data transfer failed\n"); + ktime_get_ts64(&end); + + dma_unmap_single(dma_dev, src_phys_addr, map_size, + DMA_TO_DEVICE); + + if (ret) + goto unmap; + } else { + ktime_get_ts64(&start); + memcpy_toio(map.virt_addr, buf, map_size); + ktime_get_ts64(&end); + } - ret = pci_epf_test_data_transfer(epf_test, phys_addr, - src_phys_addr, reg->size, - reg->dst_addr, - DMA_MEM_TO_DEV); - if (ret) - dev_err(dev, "Data transfer failed\n"); - ktime_get_ts64(&end); + dst_size -= map_size; + dst_addr += map_size; + buf += map_size; - dma_unmap_single(dma_dev, src_phys_addr, reg->size, - DMA_TO_DEVICE); - } else { - ktime_get_ts64(&start); - memcpy_toio(dst_addr, buf, reg->size); - ktime_get_ts64(&end); + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map); + map_size = 0; } - pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start, &end, - reg->flags & FLAG_USE_DMA); + pci_epf_test_print_rate(epf_test, "WRITE", reg->size, &start, + &end, reg->flags & FLAG_USE_DMA); /* * wait 1ms inorder for the write to complete. Without this delay L3 @@ -568,16 +586,14 @@ static void pci_epf_test_write(struct pci_epf_test *epf_test, */ usleep_range(1000, 2000); -err_dma_map: - kfree(buf); - -err_map_addr: - pci_epc_unmap_addr(epc, epf->func_no, epf->vfunc_no, phys_addr); +unmap: + if (map_size) + pci_epc_mem_unmap(epc, epf->func_no, epf->vfunc_no, &map); -err_addr: - pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size); +free_buf: + kfree(dst_buf); -err: +set_status: if (!ret) reg->status |= STATUS_WRITE_SUCCESS; else From patchwork Fri Mar 29 09:09:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610522 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B6D2C6FD1F for ; Fri, 29 Mar 2024 10:19:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=L8CukzwKN6SbECaSr11FkkTxgYP60LckIDRRIsyQGl8=; b=v2IlVMzH+7Ow7Y jXUkJID12qfoFkG7/dxgVx1pZUX9rnQU/ccFeNLCUAY5+iNm2tvRePMZRfq3rO3xF3qQ8XKOwzwE2 qSV4wM5zin1ogqsDdEj/awZ4BzulgpTHyXci2hLBD1jC2SYiw0OJ8bYIqCQ8v3PK2wHvSKm33iP8k D5N+6AkeCf4voXWwqnIriz8nIbk6givkgqqIdNUJuMSb9tNqG0Ayq1s7mVFaJw1eeWKSDzPTJXEhR 7kPWciDltt3c9/4otDGPmYKg4hh+HuYnENTIYHqLY5WBLeLG9KJHV7IdzKzxbo5s+NZ210OexRpCL trpsnxpVL79OSzM7d0KA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq9KE-000000000yS-1ZYs; Fri, 29 Mar 2024 10:19:06 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FK-0000000HQ6y-05dj for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:09:59 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6AFB8618E2; Fri, 29 Mar 2024 09:09:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A986C433C7; Fri, 29 Mar 2024 09:09:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703397; bh=RPsgju8wctxiYCFYLF54C9sP1jD4+/+es21hzNjkdTU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B1cTxtUbTPUd9ck6/DygX4OqkrkhveqVmBXUCh15b/AsCDmL0Ph7xsaN/xn+Vd446 rrRc0xLppVRCebX/nhzF+UY5qrN099j/SibNwlLHkEKRnS0QRs3AeOQDocRgptxx2q WwvoyEHITgVCHCNAWmV1ewRH25xbM8dU5uS1+5GBfvJXOsC/hCCLhJsotY/KO5mrjj q+hbJgHNhr8Dm3CN6k7nwb0e3DhriLLyDNFvMZ8T+2QbV79kqV77YhFP7TDd5USZQQ WRVOyeLWtTLKQSGjyVn1i1v4AHwA60+D56x5Fao52QaCYd9SyBXMcFa/+UXmpqJBbD NyvXEUAn5b8Ng== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 06/19] PCI: endpoint: test: Synchronously cancel command handler work Date: Fri, 29 Mar 2024 18:09:32 +0900 Message-ID: <20240329090945.1097609-7-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020958_192256_58E3550B X-CRM114-Status: GOOD ( 10.74 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org In pci_epf_test_unbind(), replace the call to cancel_delayed_work() to cancel the command handler delayed work with the synchronous version cancel_delayed_work_sync(). This ensure that the command handler is really stopped when proceeding with dma and bar cleanup. Signed-off-by: Damien Le Moal Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 0e285e539538..ab40c3182677 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -709,7 +709,7 @@ static void pci_epf_test_unbind(struct pci_epf *epf) struct pci_epf_bar *epf_bar; int bar; - cancel_delayed_work(&epf_test->cmd_handler); + cancel_delayed_work_sync(&epf_test->cmd_handler); pci_epf_test_clean_dma_chan(epf_test); for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { epf_bar = &epf->bar[bar]; From patchwork Fri Mar 29 09:09:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B199CD128D for ; Fri, 29 Mar 2024 09:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Kndu5qj828DEXLxXRwyfQ6h1HRAPHEU0wKj1PDOG9wQ=; b=cxBtKv8zc69BJY dWjIXcn4KnWQYTXDa36FAmnv1VdqKo8VPBZuMAZIJUvdtt0muw/08bAx3P7457QhDYAM6VtB6Ha+5 3wH9ibKwD/RS5igzp7Ihdqrz2WIeutaI7ahEXhVCZPRXJI0SFEWWU4CLkPPYa2zqRqRVejD9ECy7N lANbNq3OLJVEh5OZf+y3YjwYFz3USIDwXyjJwr8gDr1yfymMalFzWHa7jXXBE/KsVKOFJ2FF27x5o CGcnQPD9qeUgg9OGR2w1Y5l1zR/OVGLyjyaZb0idTc1aaCvTYmNF5s4JKWoXz9MhAUQBqg/UmxLNH hKYC6RYpbqSs/engnQOw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Fa-0000000HQMc-0MvJ; Fri, 29 Mar 2024 09:10:14 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FL-0000000HQ82-2C8o for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:02 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id E23C061710; Fri, 29 Mar 2024 09:09:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91675C433F1; Fri, 29 Mar 2024 09:09:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703398; bh=eTw3lNRbr8KXVdzPW1SwocJ9mAakSZelSr8uef0y60M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qsMFTM1Ew65BHQoYV3KHaPWQd6rEco0sqVcsiPqHgl9DuPL0JH9weqtPKbIDX3Ieo wzpiUYmcVXdXHroGXMTtXo3MgTx6tKeEiQKFH316spSegRQBD4weQlRmq7/4tYAkNN +GTtDZHSriUsE+kh8Nv60xN1xhG7M2VwgD1PUTbh5Kd7xnezySUUNTGjUKlMhC4Axg 69TT4SK1g9frPqSK8EheIM6mIATAc48hKoYwddc6fNE3ypBKisBzKJdE+8mqljeYeV tsHJte5xWdnYfiGO4+7MZVhJSUricm+zXOi6A5IpoS1kBS033ZRUdN2NalqqWdI97S 7yowI7FWpbZUg== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 07/19] PCI: endpoint: test: Implement link_down event operation Date: Fri, 29 Mar 2024 18:09:33 +0900 Message-ID: <20240329090945.1097609-8-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_020959_750733_B094A0DA X-CRM114-Status: UNSURE ( 9.11 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Implement the link_down event operation to stop the command execution delayed work when the endpoint controller notifies a link down event. Signed-off-by: Damien Le Moal Reviewed-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-test.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index ab40c3182677..e6d4e1747c9f 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -824,9 +824,19 @@ static int pci_epf_test_link_up(struct pci_epf *epf) return 0; } +static int pci_epf_test_link_down(struct pci_epf *epf) +{ + struct pci_epf_test *epf_test = epf_get_drvdata(epf); + + cancel_delayed_work_sync(&epf_test->cmd_handler); + + return 0; +} + static const struct pci_epc_event_ops pci_epf_test_event_ops = { .core_init = pci_epf_test_core_init, .link_up = pci_epf_test_link_up, + .link_down = pci_epf_test_link_down, }; static int pci_epf_test_alloc_space(struct pci_epf *epf) From patchwork Fri Mar 29 09:09:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB863CD1288 for ; Fri, 29 Mar 2024 09:10:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BtpvISgwxz0k22TDVrov8jJen32v7TeRpQqp5bKEboo=; b=SFnNhtg7pegKse LenyZiTJdQ2xruJmQav8n1ciw7hWFRFNTtgfRkFk+ViJAv+P+eXd9MGxEvuikv2G1dULTe6yAtZSY dUfCedv1WcwiJpYsjXjU04SP6EIRD+4vcmfT/KO3KF/vfYmlynUzoNbpGF/6Fwys0STo06bYSlHYx P+C+sMJtUK3vLcRYYrDtkTjKDjKnc/bkGZRbMd3sN8uRak4EBPL367PbshgvkezVv0MYTF0T/kow+ M1bzFiVyTVJ2m/O29qwYn+3ZORAyw6F28w47YM7goSvsB2Yohb+uYal08mk+efRNqB8OW/MMQ/KPN WiByd+UH7Co7/Q24fI6w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Fa-0000000HQNP-46ZX; Fri, 29 Mar 2024 09:10:14 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FN-0000000HQ9p-0qHv for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:04 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 69BB5618CC; Fri, 29 Mar 2024 09:10:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 132F1C433F1; Fri, 29 Mar 2024 09:09:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703400; bh=IVFEcbwtCPMVBa8uS2gEdsaKW6gPvOwDrAV6RcR7FCM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JkSsPVdv3AY2jAzqMzwzDMqXtA//ygbgzaL0EAbnQJ7F53gMaBwdtlwVbuD2hpKkW SIa6WSlg4pk1QIRxU506Vwh7PCUQXsip1nygsq6rTss0UFqnGadTXVSRr3cSB4UMmt MPF5IfwXOYGqCJhLbWxPMP/3mAMgh5JzUISqnrY+u1T/RHoW+BouWHRlis80BqYTiG dN3QsanOExFiHviPfH/l9cXrNma/8+tdOVUAYVDi5X8FWu2f+2ZDzQaYnUBAbrIA1Y aapZEdLM5WEgEBYeE3d24uKoUmOJNiUSvIRnk+eplslUkIZkW8c/B+vtR7UwVtmmiO ORJIZWD3610/g== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 08/19] PCI: rockchip-ep: Fix address translation unit programming Date: Fri, 29 Mar 2024 18:09:34 +0900 Message-ID: <20240329090945.1097609-9-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021001_923692_C907C0A5 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The rockchip PCIe endpoint controller handles PCIe transfers addresses by masking the lower bits of the programmed PCI address and using the same number of lower bits masked from the CPU address space used for the mapping. For a PCI mapping of bytes starting from , the number of bits masked is the number of address bits changing in the address range [pci_addr..pci_addr + size - 1]. However, rockchip_pcie_prog_ep_ob_atu() calculates num_pass_bits only using the size of the mapping, resulting in an incorrect number of mask bits depending on the value of the PCI address to map. Fix this by introducing the helper function rockchip_pcie_ep_ob_atu_num_bits() to correctly calculate the number of mask bits to use to program the address translation unit. The number of mask bits iscalculated depending on both the PCI address and size of the mapping, and clamped between 8 and 20 using the macros ROCKCHIP_PCIE_AT_MIN_NUM_BITS and ROCKCHIP_PCIE_AT_MAX_NUM_BITS. Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 15 +++++++++++---- drivers/pci/controller/pcie-rockchip.h | 4 ++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c9046e97a1d2..786efd918b3f 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -63,16 +63,23 @@ static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region)); } +static int rockchip_pcie_ep_ob_atu_num_bits(struct rockchip_pcie *rockchip, + u64 pci_addr, size_t size) +{ + int num_pass_bits = fls64(pci_addr ^ (pci_addr + size - 1)); + + return clamp(num_pass_bits, ROCKCHIP_PCIE_AT_MIN_NUM_BITS, + ROCKCHIP_PCIE_AT_MAX_NUM_BITS); +} + static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, u32 r, u64 cpu_addr, u64 pci_addr, size_t size) { - int num_pass_bits = fls64(size - 1); + int num_pass_bits = + rockchip_pcie_ep_ob_atu_num_bits(rockchip, pci_addr, size); u32 addr0, addr1, desc0; - if (num_pass_bits < 8) - num_pass_bits = 8; - addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) | (lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR); addr1 = upper_32_bits(pci_addr); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 6111de35f84c..15ee949f2485 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -245,6 +245,10 @@ (PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12))) #define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \ (PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12))) + +#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8 +#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20 + #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ (PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ From patchwork Fri Mar 29 09:09:35 2024 Content-Type: text/plain; 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Fri, 29 Mar 2024 09:10:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703401; bh=TtEADjsIY+AJrW5BwZotEsQEf9GAL1QtAJ4zDREYbqs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BIE7fTuKedWyvQK2FwnsTcjVJ1MMjL3vsvbjnj30S6RgBPJqoqCK6r4R0C6KEJuMw h9a954yfAWJni+TB7SzNy6WhjrPYuZu9Wptix8U+DbcfzJXMl7vUc1r0c1zL+FdpGS a1uGmz6jlo77nl4TQGYWYgzlZVzqM7d9bP0eO3qhhvuMPjKdR4z30a76nxsApXZlj8 SueYjW+MSqO9P0UiFrLVUYDTuxm89/o1pw192wlyTKsALDmUWDmpMgyuRVsUsLMTbD PGnTCs27vm31xhrYhXhCqKZYI8axAY9/2gXivKLxJfFR2yvASrqjZF69HUdZEYUcwq hijHSs1t63AHw== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 09/19] PCI: rockchip-ep: use macro to define EP controller .align feature Date: Fri, 29 Mar 2024 18:09:35 +0900 Message-ID: <20240329090945.1097609-10-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021003_204765_2A7B24A6 X-CRM114-Status: GOOD ( 11.07 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Introduce the macro ROCKCHIP_PCIE_AT_SIZE_ALIGN using ROCKCHIP_PCIE_AT_MIN_NUM_BITS to define the .align field of the controller epc_features structure, avoiding using the "magic" value 8 directly. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 2 +- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 786efd918b3f..f8c26606df58 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -448,7 +448,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = false, - .align = 256, + .align = ROCKCHIP_PCIE_AT_SIZE_ALIGN, }; static const struct pci_epc_features* diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 15ee949f2485..02368ce9bd54 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -248,6 +248,7 @@ #define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8 #define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20 +#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ (PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008) From patchwork Fri Mar 29 09:09:36 2024 Content-Type: text/plain; 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Fri, 29 Mar 2024 09:10:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703403; bh=aUn36xuvuaMnSLvVIxSZrVLaOID09mKh7f0aChbzrms=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UcUYOsPlM8nRJw00dIoGmQlUfCRnj4GqVbFuC9uHNT6bzcPOinci/SY5TJgKJw77G P+YB1KCbf/Ul1Y5xh0hc+P9u5YINvKy/sDaJKrqGQS8lBrju0LGr2jd14q6nt1hABV uwz81Td74Ca+gZBjF9x+RYDUpTuuN+5tw2TOYFUi21Hwd3uVKcjk4s0kfAd71heayM 5wLq4+++YvKzY9klIjRSbVNb5N41f4xl8O70CW/M8AI/3d9DTPKGzMbS/qbo9Q0JNG IrFlF714JmcG9NICvgwdVPDeOe7sQB99FEbJXJ/qTfnWySOfy60fvYG++ue8ty3qbM 13iFHn2Ooe1zA== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 10/19] PCI: rockchip-ep: Improve rockchip_pcie_ep_unmap_addr() Date: Fri, 29 Mar 2024 18:09:36 +0900 Message-ID: <20240329090945.1097609-11-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021004_313863_8C89D05A X-CRM114-Status: GOOD ( 11.33 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Damien Le Moal There is no need to loop over all regions to find the memory window used to map an address. We can use rockchip_ob_region() to determine the region index, together with a check that the address passed as argument is the address used to create the mapping. Furthermore, the ob_region_map bitmap should also be checked to ensure that we are not attempting to unmap an address that is not mapped. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index f8c26606df58..296916d4a6e4 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -258,14 +258,10 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u32 r; - - for (r = 0; r < ep->max_regions; r++) - if (ep->ob_addr[r] == addr) - break; + u32 r = rockchip_ob_region(addr); - if (r == ep->max_regions) - return; + if (addr != ep->ob_addr[r] || !test_bit(r, &ep->ob_region_map)) + return; rockchip_pcie_clear_ep_ob_atu(rockchip, r); From patchwork Fri Mar 29 09:09:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610523 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3141CCD128E for ; Fri, 29 Mar 2024 10:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4b5/VFdCth6b83k6h5PPaG80eaAUphz8NLJM1m6rDoI=; b=Jw7tYKZj9+BZZr is6Wwki1I+9qQfJDfI9R2TNWuKd577ZWrRdUQuysbMvtcECDXTmtZBK6a+Fe2PCwvm0QvlVc4Xu4P QOrJSJvAEfwDE8eakHyBYcBOPN/VVMpKNA1iDKMBQd0l0yYb96cqMHozZptJZYGmwaVZWOBoKyK0P QTiOBGNkv1EyHi/bH/Ce2Rm05SLQg99ohdow8Pis7Zb27lUgvpURwWp/8YzdYYUH5ak3X/t+qsD1y OuhbCW1BQcJrd5GlKjuVeBEeSm4J0gpzjVMpe5VvRN85y5cD6X6ZtiXhrIaUEu6VBPTRyGHxd+aQv 7x/mQEtfMOWsjRVfpgxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq9KF-000000000yc-0KAc; Fri, 29 Mar 2024 10:19:07 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FR-0000000HQ9p-0SRb for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:09 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id E7ED1618CC; Fri, 29 Mar 2024 09:10:04 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90708C43390; Fri, 29 Mar 2024 09:10:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703404; bh=xJl20dD/sfAgaEM4rbGBuGwJ0fENngDOuq2Kb9XiBoI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=YAh3YGV40g4BCrUXtyYt20wRiTXN1/OQGNo3ZwZVUpR4ybt/IDow9+EDtMWYdGM7G MMeEu+3i+Ipaa+otSjP2rRf42ea2nOeYP7fhSOcn+OBSnRtveN6dqGta2NXmBfDX1s ABoVFQdzc6RZ2NDF9JRrTu2UMBQBWhRoU8nS/XO9uNUryvslBt7TLsBrX6zHIqYG2i UTpvdBMkzmJlNrfQyAoP54xs0/ByeRXF8Il66eaAmFB0QjYwNF4OoZOa7Gk868GKQC ypVmQjC+tJ4OCeMtvVOnQiJ1B78xy4xwbBIhOEoBgxfZrSOkFRa3lgFtJUP2cYmy+/ 21OFctA6yIICQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 11/19] PCI: rockchip-ep: Improve rockchip_pcie_ep_map_addr() Date: Fri, 29 Mar 2024 18:09:37 +0900 Message-ID: <20240329090945.1097609-12-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021005_453118_581FF084 X-CRM114-Status: UNSURE ( 8.86 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Add a check to verify that the outbound region to be used for mapping an address is not already in use. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 296916d4a6e4..c2ca7878cee3 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -245,6 +245,9 @@ static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, struct rockchip_pcie *pcie = &ep->rockchip; u32 r = rockchip_ob_region(addr); + if (test_bit(r, &ep->ob_region_map)) + return -EBUSY; + rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size); set_bit(r, &ep->ob_region_map); From patchwork Fri Mar 29 09:09:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610525 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 224A1CD1288 for ; Fri, 29 Mar 2024 10:19:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=JNVCAigrLNtOsSehupnIUdzCnQGFGC7dx7uWevDj2ME=; b=U5u82z2jQE20i+ pg56wxLy+VRzrJha7JjgRefPQ2eZzVwogSxEuVETB39JGDrJMwHpkE6WGvDB1QP1S/Pt3mzNihInv o/xvEuLw/wmIAEKSHJvqJEUqCepT5iRb+6lbSzrDFxtipVUVrWRSNwWlS4wwtVO6py0cgN8NyZQbf +ZDjJIjo1tzDrdoXJfyvEURhmnvMNC6+fsI2GAsL0FrsFfulQgEZMu9tS08EpJziH5hpsHrKvAvbF 8qHU5PIaAivIAZ1V6TdBoqWdPYbx4jwNo5LhcYsXKw6m0CBQ0AtXHqCDDobuaACfD5tLBy1kXmmKl ClMoWsWtAsjFz/Nei3vQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq9KF-000000000yi-1o46; Fri, 29 Mar 2024 10:19:07 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FS-0000000HQBr-2gLI for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:10 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 6FF88618E2; Fri, 29 Mar 2024 09:10:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1A04FC433C7; Fri, 29 Mar 2024 09:10:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703406; bh=V/9fC8s68KTcgM87C93vvKDSr1AEhX43ztr6Cblt1Bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AJM32OjRFBqas7mhpEPychf3nDO84Ubo2u42bDESbXQuOlxLwUp6RLdI357rKZRNq 62iP2luSYr1ipoaMrzC3lk+0lxEMoBiJz2/6X6wUoasK5gJb14ekLOsifRA6QpsW4b OtnSgtbjPSEzcgi8jG9Wi1ZOnS5YTOvMT+ifVnNTLITanqMHw68oOmZSHeVSWNHSw8 xzulxAfvh1J/z1xZFM0eOPEBUkwFkUh1lNyPiPPWj12mGsAJzAELj/3T64lLVedAgq fMijtuHto5Ph0Zmn99L5gtBnJECH/W72OB/U0eDotAXddwiLvJrsZ0oPBXKSGcz/1u LaoCHSo/1+WAQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 12/19] PCI: rockchip-ep: Implement the map_info endpoint controller operation Date: Fri, 29 Mar 2024 18:09:38 +0900 Message-ID: <20240329090945.1097609-13-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021007_026026_FBFFF6ED X-CRM114-Status: GOOD ( 14.32 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The rockchip PCIe endpoint controller handles PCIe transfers addresses by masking the lower bits of the programmed PCI address and using the same number of lower bits from the CPU address space used for the mapping. For a PCI mapping of size bytes starting from pci_addr, the number of bits masked is the number of address bits changing in the address range [pci_addr..pci_addr + size - 1], up to 20 bits, that is, up to 1MB mappings. This means that when preparing a PCI address mapping, an endpoint function driver must use an offset into the allocated controller memory region that is equal to the mask of the starting PCI address over rockchip_pcie_ep_ob_atu_num_bits() bits. This offset also determines the maximum size of the mapping given the starting PCI address and the fixed 1MB controller memory window size. Implement the ->map_info() endpoint controller operation to allow this mapping information to be transparently used by endpoint function drivers through the function pci_epc_map_info(). Co-developed-by: Rick Wertenbroek Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 22 ++++++++++++++++++++++ drivers/pci/controller/pcie-rockchip.h | 5 +++++ 2 files changed, 27 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c2ca7878cee3..223132acc787 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -237,6 +237,27 @@ static inline u32 rockchip_ob_region(phys_addr_t addr) return (addr >> ilog2(SZ_1M)) & 0x1f; } +static int rockchip_pcie_ep_map_align(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epc_map *map) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + int num_bits; + + num_bits = rockchip_pcie_ep_ob_atu_num_bits(&ep->rockchip, + map->pci_addr, map->pci_size); + + map->map_pci_addr = map->pci_addr & ~((1ULL << num_bits) - 1); + map->map_ofst = map->pci_addr - map->map_pci_addr; + + if (map->map_ofst + map->pci_size > SZ_1M) + map->pci_size = SZ_1M - map->map_ofst; + + map->map_size = ALIGN(map->map_ofst + map->pci_size, + ROCKCHIP_PCIE_AT_SIZE_ALIGN); + + return 0; +} + static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, phys_addr_t addr, u64 pci_addr, size_t size) @@ -460,6 +481,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = { .write_header = rockchip_pcie_ep_write_header, .set_bar = rockchip_pcie_ep_set_bar, .clear_bar = rockchip_pcie_ep_clear_bar, + .map_align = rockchip_pcie_ep_map_align, .map_addr = rockchip_pcie_ep_map_addr, .unmap_addr = rockchip_pcie_ep_unmap_addr, .set_msi = rockchip_pcie_ep_set_msi, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 02368ce9bd54..30398156095f 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -241,6 +241,11 @@ #define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8) #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 #define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 + +#define ROCKCHIP_PCIE_AT_MIN_NUM_BITS 8 +#define ROCKCHIP_PCIE_AT_MAX_NUM_BITS 20 +#define ROCKCHIP_PCIE_AT_SIZE_ALIGN (1UL << ROCKCHIP_PCIE_AT_MIN_NUM_BITS) + #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \ (PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12))) #define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \ From patchwork Fri Mar 29 09:09:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3149DCD128E for ; Fri, 29 Mar 2024 09:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CXJPIIl9CRYhQ2Hs4u59WLf7JOLsJUQeta7OHrbjgKY=; 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Fri, 29 Mar 2024 09:10:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703407; bh=KGfRIg4cyD9K+XEZfIeN75bZ9A1MHBRzIMLdsYfvYAs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZniPOvFSN9t6MvBrMlAKYz+qeTGOdeRk/9fgQAZ3T9KyxHIMpUNM7G4YjDbTg/p8r T5I/rM4mcxJ6SLG1D6+zGxjprrFtyJZrrasU/Aaa5wy8OYjeUoyJiHz0zCLuMa6HIy NsHGwe6kawv7/9WY6RRpsxOz/soQWqhz/W1VJOQMY+tasuzgl0DzpxUqZ0/LG/Dptg phFMt2wUiCwCzFRsTMnmyJOT1nuVvzDh90SRbIP+5vDa8cq1klmsuXjTV61ZfNu+XB 7MmrPfxIfSA7CrW8nUk/m0asdbmGw9Gu0WYloA0VaOmLhfQ0fX9bXqwlpIE0H6CwBy tckIT9INqNV8A== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 13/19] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() memory allocations Date: Fri, 29 Mar 2024 18:09:39 +0900 Message-ID: <20240329090945.1097609-14-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021008_733635_64D70B17 X-CRM114-Status: GOOD ( 19.54 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Introduce the function rockchip_pcie_ep_get_resources() to parse the DT node of a rockchip PCIe endpoint controller and allocate the outbound memory region and memory needed for IRQ handling. This function tidies up rockchip_pcie_ep_probe(). No functional change. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 109 ++++++++++++---------- 1 file changed, 62 insertions(+), 47 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 223132acc787..c3c132733bd7 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -526,15 +526,70 @@ static const struct of_device_id rockchip_pcie_ep_of_match[] = { {}, }; +static int rockchip_pcie_ep_get_resources(struct rockchip_pcie_ep *ep) +{ + struct rockchip_pcie *rockchip = &ep->rockchip; + struct device *dev = rockchip->dev; + struct pci_epc_mem_window *windows = NULL; + int err, i; + + err = rockchip_pcie_parse_ep_dt(rockchip, ep); + if (err) + return err; + + ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr), + GFP_KERNEL); + + if (!ep->ob_addr) + return -ENOMEM; + + windows = devm_kcalloc(dev, ep->max_regions, + sizeof(struct pci_epc_mem_window), GFP_KERNEL); + if (!windows) + return -ENOMEM; + + for (i = 0; i < ep->max_regions; i++) { + windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); + windows[i].size = SZ_1M; + windows[i].page_size = SZ_1M; + } + err = pci_epc_multi_mem_init(ep->epc, windows, ep->max_regions); + devm_kfree(dev, windows); + + if (err < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + return err; + } + + ep->irq_cpu_addr = pci_epc_mem_alloc_addr(ep->epc, &ep->irq_phys_addr, + SZ_1M); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + goto err_epc_mem_exit; + } + + ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + + return 0; + +err_epc_mem_exit: + pci_epc_mem_exit(ep->epc); + + return err; +} + +static void rockchip_pcie_ep_release_resources(struct rockchip_pcie_ep *ep) +{ + pci_epc_mem_exit(ep->epc); +} + static int rockchip_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct rockchip_pcie_ep *ep; struct rockchip_pcie *rockchip; struct pci_epc *epc; - size_t max_regions; - struct pci_epc_mem_window *windows = NULL; - int err, i; + int err; u32 cfg_msi, cfg_msix_cp; ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); @@ -554,13 +609,13 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) ep->epc = epc; epc_set_drvdata(epc, ep); - err = rockchip_pcie_parse_ep_dt(rockchip, ep); + err = rockchip_pcie_ep_get_resources(ep); if (err) return err; err = rockchip_pcie_enable_clocks(rockchip); if (err) - return err; + goto err_release_resources; err = rockchip_pcie_init_port(rockchip); if (err) @@ -570,47 +625,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); - max_regions = ep->max_regions; - ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr), - GFP_KERNEL); - - if (!ep->ob_addr) { - err = -ENOMEM; - goto err_uninit_port; - } - /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - windows = devm_kcalloc(dev, ep->max_regions, - sizeof(struct pci_epc_mem_window), GFP_KERNEL); - if (!windows) { - err = -ENOMEM; - goto err_uninit_port; - } - for (i = 0; i < ep->max_regions; i++) { - windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i); - windows[i].size = SZ_1M; - windows[i].page_size = SZ_1M; - } - err = pci_epc_multi_mem_init(epc, windows, ep->max_regions); - devm_kfree(dev, windows); - - if (err < 0) { - dev_err(dev, "failed to initialize the memory space\n"); - goto err_uninit_port; - } - - ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, - SZ_1M); - if (!ep->irq_cpu_addr) { - dev_err(dev, "failed to reserve memory space for MSI\n"); - err = -ENOMEM; - goto err_epc_mem_exit; - } - - ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; - /* * MSI-X is not supported but the controller still advertises the MSI-X * capability by default, which can lead to the Root Complex side @@ -638,10 +655,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) PCIE_CLIENT_CONFIG); return 0; -err_epc_mem_exit: - pci_epc_mem_exit(epc); -err_uninit_port: - rockchip_pcie_deinit_phys(rockchip); +err_release_resources: + rockchip_pcie_ep_release_resources(ep); err_disable_clocks: rockchip_pcie_disable_clocks(rockchip); return err; From patchwork Fri Mar 29 09:09:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610383 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94402CD128D for ; Fri, 29 Mar 2024 09:10:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 29 Mar 2024 09:10:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703409; bh=XW2cLWM2iuC1h9KK5feAHrV3z6vk0VuKhTTY+E5G9i4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=umyPUM3ZxPVL9FDpG+OD+aLU+CRF8Dqmx9rqtaX4mR1qesghTuxiNjx/gWUgHtpCp cq3XxVgUrBQipZgAIHivZrQndtP1GgGj4yufGil/EvWxfCptIR9xFjbfbd0eT2DtO/ RY6mwdzAdIKjkcBCtAFQIf1qe/zVKGZeLOQGw7p1DNLRZ0b7FlV+Iv41BLpsOCaAPE pjgQWS4fMn17udwFPa9uve5u75pzucclOtxPJJVcBb/OyQkLszy+b6rCWnbhyr+C5l Pr4hsXvKoAX1clR7obPTSdli70efivMmmfYnpsp6E5BYAdtTh2vNhKJIgTEx0o+17g UdzUs37j0a8lw== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 14/19] PCI: rockchip-ep: Refactor rockchip_pcie_ep_probe() MSIX hiding Date: Fri, 29 Mar 2024 18:09:40 +0900 Message-ID: <20240329090945.1097609-15-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021010_039896_36DD5EF1 X-CRM114-Status: GOOD ( 15.02 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Move the code in rockchip_pcie_ep_probe() to hide the MSIX capability to its own function, rockchip_pcie_ep_hide_msix_cap(). No functional changes. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 54 +++++++++++++---------- 1 file changed, 30 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c3c132733bd7..b6b9161932c9 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -583,6 +583,34 @@ static void rockchip_pcie_ep_release_resources(struct rockchip_pcie_ep *ep) pci_epc_mem_exit(ep->epc); } +static void rockchip_pcie_ep_hide_msix_cap(struct rockchip_pcie *rockchip) +{ + u32 cfg_msi, cfg_msix_cp; + + /* + * MSI-X is not supported but the controller still advertises the MSI-X + * capability by default, which can lead to the Root Complex side + * allocating MSI-X vectors which cannot be used. Avoid this by skipping + * the MSI-X capability entry in the PCIe capabilities linked-list: get + * the next pointer from the MSI-X entry and set that in the MSI + * capability entry (which is the previous entry). This way the MSI-X + * entry is skipped (left out of the linked-list) and not advertised. + */ + cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); + + cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK; + + cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + + ROCKCHIP_PCIE_EP_MSIX_CAP_REG) & + ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK; + + cfg_msi |= cfg_msix_cp; + + rockchip_pcie_write(rockchip, cfg_msi, + PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); +} + static int rockchip_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -590,7 +618,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) struct rockchip_pcie *rockchip; struct pci_epc *epc; int err; - u32 cfg_msi, cfg_msix_cp; ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); if (!ep) @@ -621,6 +648,8 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) if (err) goto err_disable_clocks; + rockchip_pcie_ep_hide_msix_cap(rockchip); + /* Establish the link automatically */ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, PCIE_CLIENT_CONFIG); @@ -628,29 +657,6 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - /* - * MSI-X is not supported but the controller still advertises the MSI-X - * capability by default, which can lead to the Root Complex side - * allocating MSI-X vectors which cannot be used. Avoid this by skipping - * the MSI-X capability entry in the PCIe capabilities linked-list: get - * the next pointer from the MSI-X entry and set that in the MSI - * capability entry (which is the previous entry). This way the MSI-X - * entry is skipped (left out of the linked-list) and not advertised. - */ - cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + - ROCKCHIP_PCIE_EP_MSI_CTRL_REG); - - cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK; - - cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE + - ROCKCHIP_PCIE_EP_MSIX_CAP_REG) & - ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK; - - cfg_msi |= cfg_msix_cp; - - rockchip_pcie_write(rockchip, cfg_msi, - PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); - rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); From patchwork Fri Mar 29 09:09:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72D0FC6FD1F for ; Fri, 29 Mar 2024 09:10:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4WD/mnabA/EUeSX6yusZqPo7yJ+eTD38YdwMVSAz6mQ=; b=QNqwsSEWQveRFb T0pk0FHVKAk3AybaxU5K8ugNSjsn9jcGIczCkwqNhPWKsI0VaiXvgPzAn1/Xp9JxeDMte8QIQcJRN BJEIHfMA9lRAK/4aumMb4Lm5h8cXpol0qjNHERltbJEktOJh8lPZC82XiFAf60q3hkvzsx7zSyFNE DMQxse13QBkZYVcJLDtm5uwLabWBt1yUYJwNmla6yXDL1V2zLy9W7OzeYNoXP8jT0+Msgoi7yDBuu ai1H3OIryJY2PfkgG3NDh3Blz0fp3AAPgU9eN8Mdn3ZXhguKtZwn7iTtepeLhRoM+Oh9ck3/h+ez7 VAGsjSXqpaVQIyuW0/kA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Fo-0000000HQY4-1y8N; Fri, 29 Mar 2024 09:10:28 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8FX-0000000HQBr-1Y1S for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:14 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 309CF618E2; Fri, 29 Mar 2024 09:10:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9ED51C433F1; Fri, 29 Mar 2024 09:10:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703410; bh=h8X8PrPgY8Hng7qpmyQmQNd4ZBulxmwQHIfO5ggjjo4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nG9gQ7xQmyJ2v7u6XspNZLnVQNnX3iWwigV9fQyL/NpnIq+kDuIRhn0EcKlX0v+IY WS/I16TOqOHY3Oe8uHG0E5d7u+OjKAQISXIXRqcnx/RZSz5CrSKIFwMfRv4w9IKUNR zC4t9SpoyRZOP9BQAT3SDWjYB637IfxQ7Bqqjhgi5Xo24qUbKxBJR0dw4sEBPMEYAv 4fyER67K3NZn4Cnpz3Ln+CNTabOg8PVcbqavrROoSvKxDI8Yb6zP1cddZ6OF4qwrOf 3LdDacAErm3+lOLAtgM36/+4td8EAObcRM/LqvNP/6eYkVz2m61NLHO6b5YhnM1nFm jSe8I0MaWCKsA== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 15/19] PCI: rockchip-ep: Refactor endpoint link training enable Date: Fri, 29 Mar 2024 18:09:41 +0900 Message-ID: <20240329090945.1097609-16-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021011_755759_EF4C6EE0 X-CRM114-Status: GOOD ( 13.22 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The function rockchip_pcie_init_port() enables link training for a controller configured in EP mode. Enabling link training is again done in rockchip_pcie_ep_probe() after that function executed rockchip_pcie_init_port(). Enabling link training only needs to be done once, and doing so at the probe stage before the controller is actually started by the user serves no purpose. Refactor this by removing the link training enablement from both rockchip_pcie_init_port() and rockchip_pcie_ep_probe() and moving it to the endpoint start operation defined with rockchip_pcie_ep_start(). Enabling the controller configuration using the PCIE_CLIENT_CONF_ENABLE bit in the same PCIE_CLIENT_CONFIG register is also move to rockchip_pcie_ep_start() and both the controller configuration and link training enable bits are set with a single call to rockchip_pcie_write(). Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.c | 5 +++-- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index b6b9161932c9..7df036098ecd 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -461,6 +461,12 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); + /* Enable configuration and start link training */ + rockchip_pcie_write(rockchip, + PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE, + PCIE_CLIENT_CONFIG); + return 0; } @@ -539,7 +545,6 @@ static int rockchip_pcie_ep_get_resources(struct rockchip_pcie_ep *ep) ep->ob_addr = devm_kcalloc(dev, ep->max_regions, sizeof(*ep->ob_addr), GFP_KERNEL); - if (!ep->ob_addr) return -ENOMEM; @@ -650,16 +655,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip_pcie_ep_hide_msix_cap(rockchip); - /* Establish the link automatically */ - rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, - PCIE_CLIENT_CONFIG); - /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); - rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, - PCIE_CLIENT_CONFIG); - return 0; err_release_resources: rockchip_pcie_ep_release_resources(ep); diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index 0ef2e622d36e..dbec700ba9f9 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -244,11 +244,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, PCIE_CLIENT_CONFIG); - regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | + regs = PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); if (rockchip->is_rc) - regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; + regs |= PCIE_CLIENT_LINK_TRAIN_ENABLE | + PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC; else regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP; From patchwork Fri Mar 29 09:09:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8D7D3CD1288 for ; Fri, 29 Mar 2024 09:10:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Fri, 29 Mar 2024 09:10:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703412; bh=RXLldZKLpPMu+MutiLKOGWj1dxASTXunfudattYEHEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lKI6quCuJe1QmenF8fJF1NLI7QagbAaAlQPF1h3JDyt2nFUJByBEdlZa+/AhsnzFL b1Tk9TZzWeO5D9jAHDJT9wlo9YD5vtGGCsrTUUjz0wSZV09oCQLO7VyWvrepubRvcK mqk14eWHVHDiN6JrUQPI7n5wbFFCX2b/fkuWisgh/9yvATffAD78sHcj3pBjTZuOnU YlcIB3XRPKGcAbhaVY40YcYQwlioOAyb985mf74Oz4gDL+LY1k1AxxQOsGktm0DfN4 gaa+mQguBnU/jyoM3s2QCr8GMyq/dESFUw9GdH84ob9QWWfSdktvDNutG1y5WVsq7o y8vgMF8uJi7dA== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 16/19] PCI: rockship-ep: Introduce rockchip_pcie_ep_stop() Date: Fri, 29 Mar 2024 18:09:42 +0900 Message-ID: <20240329090945.1097609-17-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021013_586191_8E661D1F X-CRM114-Status: GOOD ( 11.67 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Define the EPC operation ->stop for the rockchip endpoint driver with the function rockchip_pcie_ep_stop(). This function disables link training and the controller configuration, as the reverse to what the start operation defined with rockchip_pcie_ep_start() does. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 13 +++++++++++++ drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 7df036098ecd..c126da07bf0c 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -470,6 +470,18 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) return 0; } +static void rockchip_pcie_ep_stop(struct pci_epc *epc) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; + + /* Stop link training and disable configuration */ + rockchip_pcie_write(rockchip, + PCIE_CLIENT_CONF_DISABLE | + PCIE_CLIENT_LINK_TRAIN_DISABLE, + PCIE_CLIENT_CONFIG); +} + static const struct pci_epc_features rockchip_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, @@ -494,6 +506,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = { .get_msi = rockchip_pcie_ep_get_msi, .raise_irq = rockchip_pcie_ep_raise_irq, .start = rockchip_pcie_ep_start, + .stop = rockchip_pcie_ep_stop, .get_features = rockchip_pcie_ep_get_features, }; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 30398156095f..0263f158ee8d 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -32,6 +32,7 @@ #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001) #define PCIE_CLIENT_CONF_DISABLE HIWORD_UPDATE(0x0001, 0) #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_LINK_TRAIN_DISABLE HIWORD_UPDATE(0x0002, 0) #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008) #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x)) #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) From patchwork Fri Mar 29 09:09:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B84C1CD128D for ; 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Fri, 29 Mar 2024 09:10:30 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8Fa-0000000HQ9p-12gl for linux-rockchip@lists.infradead.org; Fri, 29 Mar 2024 09:10:17 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 054E261764; Fri, 29 Mar 2024 09:10:14 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A56C3C433F1; Fri, 29 Mar 2024 09:10:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703413; bh=+TmInabN37SfEhMgyX/p7nVgLz3hbajUkBFvvCUgxJ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=env7fnJMur239VcR6gPVXw7rC1BdzlLCS6Hjm+pdshs7w7u45zeiwvIgjhi/ZZF7F /DdgykUQRq1i+X+Pf9A+bn3+8Kqr3U0h8KOBBqB7k/Ebym/1/10uOX6JsIJg+xl95h 9bURXPPnxl1pRtORkL63Pw5S5e/OGE01PhQdDJMKmAU+CdYY69dhdKiHcF9sUHIR5T 3lSY2SYSB5ZJ5i4juakmw07PExxaTVms6OGuEu4jtetq3PfMwWK4+zLQod4nmOb4WM nfubqpPKqv10sdDvHreOhp/OZcjC01fPAZCC8PCxGUfa2BM576m+smnIOrOkkwySXl SEgUvvXLcg/RQ== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 17/19] PCI: rockchip-ep: Improve link training Date: Fri, 29 Mar 2024 18:09:43 +0900 Message-ID: <20240329090945.1097609-18-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021014_564190_33E35953 X-CRM114-Status: GOOD ( 22.33 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org The Rockchip rk339 technical reference manual describe the endpoint mode link training process clearly and states that: Insure link training completion and success by observing link_st field in PCIe Client BASIC_STATUS1 register change to 2'b11. If both side support PCIe Gen2 speed, re-train can be Initiated by asserting the Retrain Link field in Link Control and Status Register. The software should insure the BASIC_STATUS0[negotiated_speed] changes to "1", that indicates re-train to Gen2 successfully. This procedure is very similar to what is done for the root-port mode in rockchip_pcie_host_init_port(). Implement this link training procedure for the endpoint mode as well. Given that the rk3399 SoC does not have an interrupt signaling link status changes, training is implemented as a delayed work which is rescheduled until the link training completes or the endpoint controller is stopped. The link training work is first scheduled in rockchip_pcie_ep_start() when the endpoint function is started. Link training completion is signaled to the function using pci_epc_linkup(). Accordingly, the linkup_notifier field of the rockchip pci_epc_features structure is changed to true. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 79 ++++++++++++++++++++++- drivers/pci/controller/pcie-rockchip.h | 11 ++++ 2 files changed, 89 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index c126da07bf0c..d8e56b4a5578 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "pcie-rockchip.h" @@ -48,6 +50,7 @@ struct rockchip_pcie_ep { u64 irq_pci_addr; u8 irq_pci_fn; u8 irq_pending; + struct delayed_work link_training; }; static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip, @@ -467,6 +470,8 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); + schedule_delayed_work(&ep->link_training, 0); + return 0; } @@ -475,6 +480,8 @@ static void rockchip_pcie_ep_stop(struct pci_epc *epc) struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; + cancel_delayed_work_sync(&ep->link_training); + /* Stop link training and disable configuration */ rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_DISABLE | @@ -482,8 +489,77 @@ static void rockchip_pcie_ep_stop(struct pci_epc *epc) PCIE_CLIENT_CONFIG); } +static void rockchip_pcie_ep_retrain_link(struct rockchip_pcie *rockchip) +{ + u32 status; + + status = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_LCS); + status |= PCI_EXP_LNKCTL_RL; + rockchip_pcie_write(rockchip, status, PCIE_EP_CONFIG_LCS); +} + +static bool rockchip_pcie_ep_link_up(struct rockchip_pcie *rockchip) +{ + u32 val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS1); + + return PCIE_LINK_UP(val); +} + +static void rockchip_pcie_ep_link_training(struct work_struct *work) +{ + struct rockchip_pcie_ep *ep = + container_of(work, struct rockchip_pcie_ep, link_training.work); + struct rockchip_pcie *rockchip = &ep->rockchip; + struct device *dev = rockchip->dev; + u32 val; + int ret; + + /* Enable Gen1 training and wait for its completion */ + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, + val, PCIE_LINK_TRAINING_DONE(val), 50, + LINK_TRAIN_TIMEOUT); + if (ret) + goto again; + + /* Make sure that the link is up */ + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1, + val, PCIE_LINK_UP(val), 50, + LINK_TRAIN_TIMEOUT); + if (ret) + goto again; + + /* Check the current speed */ + val = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL); + if (!PCIE_LINK_IS_GEN2(val) && rockchip->link_gen == 2) { + /* Enable retrain for gen2 */ + rockchip_pcie_ep_retrain_link(rockchip); + readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, + val, PCIE_LINK_IS_GEN2(val), 50, + LINK_TRAIN_TIMEOUT); + } + + /* Check again that the link is up */ + if (!rockchip_pcie_ep_link_up(rockchip)) + goto again; + + val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS0); + dev_info(dev, + "Link UP (Negociated speed: %sGT/s, width: x%lu)\n", + (val & PCIE_CLIENT_NEG_LINK_SPEED) ? "5" : "2.5", + ((val & PCIE_CLIENT_NEG_LINK_WIDTH_MASK) >> + PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT) << 1); + + /* Notify the function */ + pci_epc_linkup(ep->epc); + + return; + +again: + schedule_delayed_work(&ep->link_training, msecs_to_jiffies(5)); +} + static const struct pci_epc_features rockchip_pcie_epc_features = { - .linkup_notifier = false, + .linkup_notifier = true, .msi_capable = true, .msix_capable = false, .align = ROCKCHIP_PCIE_AT_SIZE_ALIGN, @@ -644,6 +720,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip = &ep->rockchip; rockchip->is_rc = false; rockchip->dev = dev; + INIT_DELAYED_WORK(&ep->link_training, rockchip_pcie_ep_link_training); epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); if (IS_ERR(epc)) { diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 0263f158ee8d..3963b7097a91 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -26,6 +26,7 @@ #define MAX_LANE_NUM 4 #define MAX_REGION_LIMIT 32 #define MIN_EP_APERTURE 28 +#define LINK_TRAIN_TIMEOUT (5000 * USEC_PER_MSEC) #define PCIE_CLIENT_BASE 0x0 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00) @@ -50,6 +51,10 @@ #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 #define PCIE_CLIENT_DEBUG_LTSSM_L2 0x19 +#define PCIE_CLIENT_BASIC_STATUS0 (PCIE_CLIENT_BASE + 0x44) +#define PCIE_CLIENT_NEG_LINK_WIDTH_MASK GENMASK(7, 6) +#define PCIE_CLIENT_NEG_LINK_WIDTH_SHIFT 6 +#define PCIE_CLIENT_NEG_LINK_SPEED BIT(5) #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48) #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000 @@ -87,6 +92,8 @@ #define PCIE_CORE_CTRL_MGMT_BASE 0x900000 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000) +#define PCIE_CORE_PL_CONF_LS_MASK 0x00000001 +#define PCIE_CORE_PL_CONF_LS_READY 0x00000001 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006 @@ -144,6 +151,7 @@ #define PCIE_RC_CONFIG_BASE 0xa00000 #define PCIE_EP_CONFIG_BASE 0xa00000 #define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) +#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 @@ -155,6 +163,7 @@ #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) +#define PCIE_EP_CONFIG_LCS (PCIE_EP_CONFIG_BASE + 0xd0) #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) @@ -192,6 +201,8 @@ #define ROCKCHIP_VENDOR_ID 0x1d87 #define PCIE_LINK_IS_L2(x) \ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) +#define PCIE_LINK_TRAINING_DONE(x) \ + (((x) & PCIE_CORE_PL_CONF_LS_MASK) == PCIE_CORE_PL_CONF_LS_READY) #define PCIE_LINK_UP(x) \ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) #define PCIE_LINK_IS_GEN2(x) \ From patchwork Fri Mar 29 09:09:44 2024 Content-Type: text/plain; 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Fri, 29 Mar 2024 09:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703415; bh=7oDGTy7Lw9gvGIO8M6FvPbAlyOWQQdvFe/jiW9a1h3s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lQabuVT2/wm2HpNgWsT5QsW9+2tTGubZLksdh0wQiVdwMANADoXD8g7JH2x9c01H3 QtSv1UBycphovECJf6nCEygV/GJKrBHzWM4KtGjoAeIANHihSD95UVB2bWxIKMD2QL sE8fCyAsM5DsAgjMsZSBorpaEaz4QhObKb9zGD2hM+lQVzxySXqA2gxxTUDLNsalxd a2nG8pUQwU9KEQFcpEdG3IN83mxYL37gSvyVIzXkWPHbF2JHCTlUhHIqMPSzWYFr1l 4pG21Kwvd2X4cooLl7GC8gDGR65e4qVG3v5yFmR8vd9wMwwEiT+mJYw+GeyQs6nI2F aWzERCjqanxOA== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 18/19] dt-bindings: pci: rockchip,rk3399-pcie-ep: Add ep-gpios property Date: Fri, 29 Mar 2024 18:09:44 +0900 Message-ID: <20240329090945.1097609-19-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_021016_110901_619EFA93 X-CRM114-Status: UNSURE ( 7.23 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Wilfred Mallawa Describe the `ep-gpios` property which is used to map the PERST input signal for endpoint mode. Signed-off-by: Wilfred Mallawa Signed-off-by: Damien Le Moal --- .../devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml index 6b62f6f58efe..b8a5b567a9af 100644 --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml @@ -30,6 +30,9 @@ properties: maximum: 32 default: 32 + ep-gpios: + description: Input GPIO configured for the PERST signal. + required: - rockchip,max-outbound-regions From patchwork Fri Mar 29 09:09:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 13610388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0BE0CD1288 for ; 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Fri, 29 Mar 2024 09:10:22 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 05B85618D1; Fri, 29 Mar 2024 09:10:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A04E8C43390; Fri, 29 Mar 2024 09:10:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1711703416; bh=KnL9qhDEe03V7Ld9L+icsq4NJuUTRiw2nztwBh1bzS4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=JLSthcFjb0qAroJnySyOMWj4PiShL6qqJX25qRTTLFRKxhCu13DRSIVROiDHcWbJD JagZ+UNlwpJSQENKO1FCKlMTzrbuopwKaeGLgk5LYkGus00AKrSEtLsYTZThD1kzKD UdxtJdiROd9eVdAvCEt1HjI6vkz656bJiEcdq8k6mCAffqgVv+ZeV+ZpGMkE0CGRA8 bv8JKPW3fjS0O8nEsKLBWW7VbSmvNQXkGeJL5sbXDr9ihlfa/6K9EHmLjj1Z+Fx3Qp nkGq7WNK/NqH84cXDaNAKFzP5xW7u35igdn5JI4sfVT5HqvTbgsDmru66oqpo26Pd+ koNrWZb5vlIuw== From: Damien Le Moal To: Manivannan Sadhasivam , Kishon Vijay Abraham I , Shawn Lin , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org Cc: linux-rockchip@lists.infradead.org Subject: [PATCH 19/19] PCI: rockchip-ep: Handle PERST signal in endpoint mode Date: Fri, 29 Mar 2024 18:09:45 +0900 Message-ID: <20240329090945.1097609-20-dlemoal@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240329090945.1097609-1-dlemoal@kernel.org> References: <20240329090945.1097609-1-dlemoal@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_091021_240486_A320BBDD X-CRM114-Status: GOOD ( 22.88 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org Currently, the Rockchip PCIe endpoint controller driver does not handle PERST signal, which prevents detecting when link training should actually be started or if the host reset the device. This however can be supported using the controller ep_gpio, set as an input GPIO for endpoint mode. Modify the endpoint rockchip driver to get the ep_gpio and its associated interrupt which is serviced using a threaded IRQ with the function rockchip_pcie_ep_perst_irq_thread() as handler. This handler function notifies a link down event corresponding to the RC side asserting the PERST signal using pci_epc_linkdown() when the gpio is high. Once the gpio value goes down, corresponding to the RC de-asserting the PERST signal, link training is started. The polarity of the gpio interrupt trigger is changed from high to low after the RC asserted PERST, and conversely changed from low to high after the RC de-asserts PERST. Signed-off-by: Damien Le Moal --- drivers/pci/controller/pcie-rockchip-ep.c | 118 +++++++++++++++++++++- drivers/pci/controller/pcie-rockchip.c | 12 +-- 2 files changed, 122 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index d8e56b4a5578..501d25f7284c 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "pcie-rockchip.h" @@ -50,6 +51,9 @@ struct rockchip_pcie_ep { u64 irq_pci_addr; u8 irq_pci_fn; u8 irq_pending; + int perst_irq; + bool perst_asserted; + bool link_up; struct delayed_work link_training; }; @@ -464,13 +468,17 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc) rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG); + if (rockchip->ep_gpio) + enable_irq(ep->perst_irq); + /* Enable configuration and start link training */ rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_CONF_ENABLE, PCIE_CLIENT_CONFIG); - schedule_delayed_work(&ep->link_training, 0); + if (!rockchip->ep_gpio) + schedule_delayed_work(&ep->link_training, 0); return 0; } @@ -480,6 +488,11 @@ static void rockchip_pcie_ep_stop(struct pci_epc *epc) struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; + if (rockchip->ep_gpio) { + ep->perst_asserted = true; + disable_irq(ep->perst_irq); + } + cancel_delayed_work_sync(&ep->link_training); /* Stop link training and disable configuration */ @@ -542,6 +555,13 @@ static void rockchip_pcie_ep_link_training(struct work_struct *work) if (!rockchip_pcie_ep_link_up(rockchip)) goto again; + /* + * If PERST was asserted while polling the link, do not notify + * the function. + */ + if (ep->perst_asserted) + return; + val = rockchip_pcie_read(rockchip, PCIE_CLIENT_BASIC_STATUS0); dev_info(dev, "Link UP (Negociated speed: %sGT/s, width: x%lu)\n", @@ -551,6 +571,7 @@ static void rockchip_pcie_ep_link_training(struct work_struct *work) /* Notify the function */ pci_epc_linkup(ep->epc); + ep->link_up = true; return; @@ -558,6 +579,94 @@ static void rockchip_pcie_ep_link_training(struct work_struct *work) schedule_delayed_work(&ep->link_training, msecs_to_jiffies(5)); } +static void rockchip_pcie_ep_perst_assert(struct rockchip_pcie_ep *ep) +{ + struct rockchip_pcie *rockchip = &ep->rockchip; + struct device *dev = rockchip->dev; + + dev_dbg(dev, "PERST asserted, link down\n"); + + if (ep->perst_asserted) + return; + + ep->perst_asserted = true; + + cancel_delayed_work_sync(&ep->link_training); + + if (ep->link_up) { + pci_epc_linkdown(ep->epc); + ep->link_up = false; + } +} + +static void rockchip_pcie_ep_perst_deassert(struct rockchip_pcie_ep *ep) +{ + struct rockchip_pcie *rockchip = &ep->rockchip; + struct device *dev = rockchip->dev; + + dev_dbg(dev, "PERST de-asserted, starting link training\n"); + + if (!ep->perst_asserted) + return; + + ep->perst_asserted = false; + + /* Enable link re-training */ + rockchip_pcie_ep_retrain_link(rockchip); + + /* Start link training */ + schedule_delayed_work(&ep->link_training, 0); +} + +static irqreturn_t rockchip_pcie_ep_perst_irq_thread(int irq, void *data) +{ + struct pci_epc *epc = data; + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; + u32 perst = gpiod_get_value(rockchip->ep_gpio); + + if (perst) + rockchip_pcie_ep_perst_assert(ep); + else + rockchip_pcie_ep_perst_deassert(ep); + + irq_set_irq_type(ep->perst_irq, + (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); + + return IRQ_HANDLED; +} + +static int rockchip_pcie_ep_setup_irq(struct pci_epc *epc) +{ + struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); + struct rockchip_pcie *rockchip = &ep->rockchip; + struct device *dev = rockchip->dev; + int ret; + + if (!rockchip->ep_gpio) + return 0; + + /* PCIe reset interrupt */ + ep->perst_irq = gpiod_to_irq(rockchip->ep_gpio); + if (ep->perst_irq < 0) { + dev_err(dev, "No corresponding IRQ for PERST GPIO\n"); + return ep->perst_irq; + } + + ep->perst_asserted = true; + irq_set_status_flags(ep->perst_irq, IRQ_NOAUTOEN); + ret = devm_request_threaded_irq(dev, ep->perst_irq, NULL, + rockchip_pcie_ep_perst_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + "pcie-ep-perst", epc); + if (ret) { + dev_err(dev, "Request PERST GPIO IRQ failed %d\n", ret); + return ret; + } + + return 0; +} + static const struct pci_epc_features rockchip_pcie_epc_features = { .linkup_notifier = true, .msi_capable = true, @@ -721,6 +830,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) rockchip->is_rc = false; rockchip->dev = dev; INIT_DELAYED_WORK(&ep->link_training, rockchip_pcie_ep_link_training); + ep->link_up = false; epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops); if (IS_ERR(epc)) { @@ -748,7 +858,13 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) /* Only enable function 0 by default */ rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG); + err = rockchip_pcie_ep_setup_irq(epc); + if (err < 0) + goto err_uninit_port; + return 0; +err_uninit_port: + rockchip_pcie_deinit_phys(rockchip); err_release_resources: rockchip_pcie_ep_release_resources(ep); err_disable_clocks: diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index dbec700ba9f9..3938c0b6b5a9 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -119,13 +119,11 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) return PTR_ERR(rockchip->aclk_rst); } - if (rockchip->is_rc) { - rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", - GPIOD_OUT_HIGH); - if (IS_ERR(rockchip->ep_gpio)) - return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio), - "failed to get ep GPIO\n"); - } + rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", + rockchip->is_rc ? GPIOD_OUT_HIGH : GPIOD_IN); + if (IS_ERR(rockchip->ep_gpio)) + return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio), + "failed to get ep GPIO\n"); rockchip->aclk_pcie = devm_clk_get(dev, "aclk"); if (IS_ERR(rockchip->aclk_pcie)) {