From patchwork Fri Mar 29 09:26:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610458 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC2294AEFE for ; Fri, 29 Mar 2024 09:27:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704466; cv=none; b=QaP5byHba3vZ2PaXRbw7ksfo0uXfn/Q7+K+VbQ8gNi+kpzqYfLF5YgSqRJZ0eEopH9hgrlaZySk6t/qP/jIVOXyjCCvz3iAzQxaiWzR49mtd43wMTnpB06YW0bqECVWr5adtQzYQnNxjr4PwFblYxOuvRQ2E4FUfiMyHo2qQtOw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704466; c=relaxed/simple; bh=LSg/rLuOsrxnsspgQ4r75KW0fisxGsUYFmGBfMYsNR4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k6GI8vsqM0+/tNYcb8Is/0Gk/MfA79Jgb/RWZHw7/vRiSEjK5XEvXuLGg5XTZqrnmBoe6cJsKMAq/Zs2IJQeGKk72rVnIgjBsMxwmVkVYi45EWWobj8SGlxaaSS1pIbKwJnqlBplruk5ScwpqmugaQQxb32QGBzdSV+iqsepmHA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=jfZsineP; arc=none smtp.client-ip=209.85.216.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="jfZsineP" Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-29f1686ff12so1380837a91.1 for ; Fri, 29 Mar 2024 02:27:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704464; x=1712309264; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=36s8w1btdvP+IRdBHf7/8nd9U/EcEkIO6Yh0YtSkXJI=; b=jfZsinePGh8GvughMdULBUqVVMU1/IJRkTvq/SnnFQDY0Q+6enwRM+p1Y4Db8388LN Ld0i1RVKMNpoau3cAcSqb5TrIJqhYrW7P+fQz3J9IQJwOkKcKowBRgEsvr2lUU4DYjbA /0snbQzpo2MYpphrbq8vQGY5i4KqzuiwtPry/z1RnbZD0+6Z7gFRBshffAJ23D5v+uzW cxFsXRI/7R2j1NvNuFIxlcuapbcsxuuPFr3lv8UNbBysKwDbWFlx9IMC+SQBuCFDf3vA mAtSjLmfnj5tnMuaHSHq+O4ceHaGTfHdGvxbTVd48Jv+s4Ly7qh3TAv1BDpU6+Sp9wHq 4anQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704464; x=1712309264; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=36s8w1btdvP+IRdBHf7/8nd9U/EcEkIO6Yh0YtSkXJI=; b=PP9I2llV+L/+0gkzlbMvNVNBAdIaRk9WlIAsZ27uluTuqBQJOXV9nsQY+trCHwPost rXCHcA1NFpGfPzrQ0YODLdtmO/+7wwItJ4IAksynC5CaEznFN0tin+8nq9G5tfoXzjgS Z7gkdkn9jVoZt7iPWDtTRf1gogfb0w9+gToQ9XgHSfVgS2qlhsAuobZVxHkIEnwi9zMH hLCOrgTI+KMCWTZ00zJnUlhoSnIyW0jYBxg58kVINGemVAoeo1JJPsQ0465qsTe6weUv DgdMbgJr/FpJz8Pv+VashCPYcgrZr34TbJpbQukhzlWM4DhhVA9Wf3rATXQ8cMjq1/bM 836g== X-Forwarded-Encrypted: i=1; AJvYcCUvL5hpb9nBrRpXMbF14UJIm8HCgSP4pdV/6t3SOOUZjDJogjMYDTpFCrBtAVxSFDo6MkOIVK5nVGDGh1eNxFIjdmoU X-Gm-Message-State: AOJu0YxRjET43eqYCI8iiuL3BC/0qvaU2yW7AHSlGTM6nT+pwSZJmWdk XqPwkayMbrqIgfg4/XkMyyGhZJrXF2E/oP8XBpvjHZH1i1l7MP+MPl7Wpuout2Y= X-Google-Smtp-Source: AGHT+IFlwBZNBeq8Vspi+hcWxSywtk3eGAD9nkXigHO0/VIsXQXySmGGcQSPVllJIcGqIgMzGVu2Kw== X-Received: by 2002:a17:90a:6986:b0:2a2:1012:fbbf with SMTP id s6-20020a17090a698600b002a21012fbbfmr1808164pjj.14.1711704464008; Fri, 29 Mar 2024 02:27:44 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:43 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:17 +0800 Subject: [PATCH RFC 01/11] dt-bindings: riscv: Add Sdtrig ISA extension Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-1-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 As riscv-debug-spec [1] Chapter 5 introduce Sdtrig extension. Add an entry for the Sdtrig extension to the riscv,isa-extensions property. Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..47d82cd35ca7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -121,6 +121,13 @@ properties: version of the privileged ISA specification. # multi-letter extensions, sorted alphanumerically + - const: sdtrig + description: | + The standard Sdtrig extension for introduce trigger CSRs for + cause a breakpoint exception, entry into Debug Mode, + or trace action as frozen at commit 359bedc ("Freeze Candidate") + of riscv-debug-spec + - const: smaia description: | The standard Smaia supervisor-level extension for the advanced From patchwork Fri Mar 29 09:26:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610459 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C00950A97 for ; Fri, 29 Mar 2024 09:27:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704469; cv=none; b=sZoEdsTF6dfjWxG1kuZRJWq9lrgm2FsCTi37gntFuFat+vlkv+kOyulk7n2sDzQ3l+KT3CMNcL0kxCGQaGgD6y2HIkg+S5UlqsLfQtfZdlB5IQVuH4Y5WpnsLm9CDM1VYSDnVlV2Na75q7MzeHNABH/7htNiF5uGCvlGhRFdCCQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704469; c=relaxed/simple; bh=fkcsbGMX7J/mGQ3kvbZ+/zIV5Yfm+uf2j5rr/bXjhvk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RBMdLxu9Pd5B8R6CCZOUG3QB/pBo1uqAsGvt6h+EbjElU1N/u1KDt0nw8flbcOIj4otyYDP+Y1B/rwLalgmdhZRPvfXUHnGGI0d7Jnv6C5TV1Q25NSLuRN7xokNE3TweKSdfWnwG8ebhAfDbm+iSg2plvKApe0pZm0NjZ6vxIws= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=FDKiLbhW; arc=none smtp.client-ip=209.85.216.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="FDKiLbhW" Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-2a21af18037so40212a91.3 for ; Fri, 29 Mar 2024 02:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704467; x=1712309267; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Z0W2e62vRjypPXRsKNjsPCEnDXDpWajUvlAFErcdHOc=; b=FDKiLbhW62r5AuDSXRUZj5O5V3KeL56RpH3jWggpLKpbu7GKnA7nl+0w1rNFqWqCrL bCNU+xqLaMoPdGIm2fXL9sQJOcQSGSb1rDXaSg4xusFdoHHhGShDjOvxqbt3tveJy3AX SlQDBcxdKfr7wO7SmIXrDTOusRs5IT++cTkN6QRFi4nS+968tg36N+p2RA10SHrKeJuy FYxkGlnzCi7Kq5S1W4EuUVGpZmfpYHnldAftYCFD/rmgTmJCyLdJPNF6Y2Hn4ypjNpnz SPhzruXMbp/eSgUgWD3TTj84ZlzS+4vrKUHnDAm46+xl7zEtd6+4kg7wfA6qLP43GDcB 0Y7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704467; x=1712309267; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z0W2e62vRjypPXRsKNjsPCEnDXDpWajUvlAFErcdHOc=; b=RNAdh3sNfKBCaLXoVIRd649IVhWOGyQ1Y5PMtOgnHbisTq5BSteKMKYEYQ9N1fkYyQ nlK4awTv/KOBGcSM7JOs8jbm+Bw7gypEfrggEunQZMPGHA47D+9lslwKp3EDedzf2Uj8 z7JNM1ELhbRt4G8voLhXijeFrmug+MGSgAl/PFCFDReR+1re02A/WbbrGLWEHahos0KN gwtZiTUSndZLkqIYTZf/EHOS1TMND4LBC2mLdBvfM4kmFHarbUVSkTTbmr1uI3RAsgnP WNlqAVjgtB1noKGFZkIc1DL2eSi2YhDhsdwdmx0T+IYAGlwT1fM1YJEFgT/n0mUataEH drhA== X-Forwarded-Encrypted: i=1; AJvYcCX343NTIpLmkh5Hnl0WT+ORRGe6+50IfdlbKSnejtOOTotzzsf3p0eZG7mb7eJ0pM2FI6Rrty3yO/WgdnGlu63geurd X-Gm-Message-State: AOJu0YzbeT5LmZ2npVs+oE8LAyD5oc/YDLuseyNsr40duiL7Kt3qG8UZ MWPvwEXK4YqEX2Gs7fUD8ECaWBwuyKJva+iYh1Sti3oyDbqS9RIvdQUUVqBDYkI= X-Google-Smtp-Source: AGHT+IEuJwWsZcF37cdSyR4oAfPxO9tw5zd/KR1va4FW9dJBQvIHdmB9ul/Vbw6Ly8QQV6MyjM+RcQ== X-Received: by 2002:a17:90b:46c6:b0:2a2:176f:fba9 with SMTP id jx6-20020a17090b46c600b002a2176ffba9mr596520pjb.43.1711704467546; Fri, 29 Mar 2024 02:27:47 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:47 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:18 +0800 Subject: [PATCH RFC 02/11] dt-bindings: riscv: Add Sdtrig optional CSRs existence on DT Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-2-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 The mcontext/hcontext/scontext CSRs are optional in the Sdtrig extension, to prevent RW operations to the missing CSRs, which will cause illegal instructions. As a solution, we have proposed the dt format for these CSRs. Signed-off-by: Max Hsu --- Documentation/devicetree/bindings/riscv/cpus.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c713a48c5025 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -137,6 +137,24 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + debug: + type: object + properties: + compatible: + const: riscv,debug-v1.0.0 + trigger-module: + type: object + description: | + An indication set of optional CSR existence from + riscv-debug-spec Sdtrig extension + properties: + mcontext-present: + type: boolean + hcontext-present: + type: boolean + scontext-present: + type: boolean + anyOf: - required: - riscv,isa From patchwork Fri Mar 29 09:26:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610460 Received: from mail-pg1-f177.google.com (mail-pg1-f177.google.com [209.85.215.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE25C537E7 for ; Fri, 29 Mar 2024 09:27:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704474; cv=none; b=UzeoZFZY5mLndbwqpmK5fBlrjPn+nKToZ5S4g6163acvl0SJUbwA7vcri8lBLzFkc8OXLh7OBor2gbWha/Y2TaOS6pArPgUVU2z0Zmzbx5AfYdLSLdgvupbDq9j/tFCK1QJeaoiGW2uyzhvR5+iD6rQ/drNx1K85QgcDfIxuhmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704474; c=relaxed/simple; bh=JA7UBPKQETRrngwLOp+J6IF6ItB1gKtf7ZWFX11pOa4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HROyKkkMrY1uguRDPrulVTLT+c+52NTcNyw58c9CCUix6JI5gUyW/aNpK4DRfqhg3nJ+Tw/fc42vcM1EI4PzM20uF2vVJ31gjLiaQVFuG73kErzAja9Kw91Njj3ahP+K3xo6OlgKMwrcEdTpRu322L35FrJCKSLwkmSIxgNFggc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=Y+kogVx+; arc=none smtp.client-ip=209.85.215.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Y+kogVx+" Received: by mail-pg1-f177.google.com with SMTP id 41be03b00d2f7-5dbcfa0eb5dso1374165a12.3 for ; Fri, 29 Mar 2024 02:27:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704471; x=1712309271; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9zZjndsCXBnAhUzEP7RXDQ1mWPnsHyYv9gf2B2OXJhU=; b=Y+kogVx+aPSJb+/4M886ExbMfFekUnh15FdP7WFiHUXrpSqYmngEX+cR6VQgj3EN4+ 08NFjwmxuWSUZxNAKi78pmDG7fk/HXZVaS05csCUkREqDpXDqgkMH5ueWQoUXeOq0sLt 1LKEexOzlFo15dcbz3nWq6Ei2cn8M4pcVWLD+fZbJcgGiuDoIIfQS9Td3Jf+Z3ZWvTZ0 Z/idaBOYgq8fQDev0TmMJ6+pFwcPmycqdXoBLtXxUrTafFTFkZQQUvrFtbsctsNIWJXX RddcdrLfx2uz5svmgDU+KLFkE6mrDwnvmjiWFsbDNm9d9jAC7W/4p4Ha8WxG9LXdE/GQ 79Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704471; x=1712309271; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9zZjndsCXBnAhUzEP7RXDQ1mWPnsHyYv9gf2B2OXJhU=; b=MfCUh2D8pSxY8CjblzlRusLag6hKDK1tgiRDpmT2pT4oMGa9e1XDUpV0CDXCzGkn3J 8Ha81da1n9ZuZBrjYhiFkTIMsxDwmVq0wcDqolszw31nClTt6DzUKZ/KsPMv18gknwof EwmqyxzhKanyh+fwZNpbL8zmtRL8igOoevqCkqr/zeCvyoNFX0xUC6fxwdryIpZ+NmI7 oq6yohVjJR8MikrC6x3cX5Zvnu2pDh1aPnG650qbEpgOyjq4u/DOJmrkCBGWUqxu4qV9 Np/mENEQpu4e9A4FO8R34Wg3BXYaUljgpuGGEL/MaJ4YOjjlrHDteDPv6pldufq8+Ggb tkFQ== X-Forwarded-Encrypted: i=1; AJvYcCXuuHfCKmRtcfcbgi6k2ZLjNGolcKth4KLpzpk1/t07+POA4FtByKY1pJp05g6CRIuTEeQic8KjzBI+85kJ+dm1om81 X-Gm-Message-State: AOJu0YyL/iIR3GlGlpKqeEi6cMZg4zdkRRHNjpJ73YE3h6OQ9DyNBc0b Xfg4kLfVFua/ro8KIpcGkq/rwAqWKngH7nlNYw5M84OD3RlkFYI8ksPc/mAbvXY= X-Google-Smtp-Source: AGHT+IFa9F+COKZa8ISch08bbNdcv43TGvP8EG5xj5dJ6X521KU5ZdxA9e79JCDBwefI9u7FZNld2Q== X-Received: by 2002:a17:90a:ba88:b0:2a1:f3a0:181a with SMTP id t8-20020a17090aba8800b002a1f3a0181amr1796435pjr.31.1711704471054; Fri, 29 Mar 2024 02:27:51 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:50 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:19 +0800 Subject: [PATCH RFC 03/11] riscv: Add ISA extension parsing for Sdtrig Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-3-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 Add ISA extension parsing for Sdtrig as introduced in riscv-debug-spec [1] Chapter 5 Link: https://github.com/riscv/riscv-debug-spec/releases/download/ar20231208/riscv-debug-stable.pdf [1] Signed-off-by: Max Hsu --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index e17d0078a651..9f8d780fce35 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -81,6 +81,7 @@ #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 +#define RISCV_ISA_EXT_SDTRIG 75 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ed2359eae35..080c06b76f53 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -296,6 +296,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA(sdtrig, RISCV_ISA_EXT_SDTRIG), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), From patchwork Fri Mar 29 09:26:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610461 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8449154BD4 for ; Fri, 29 Mar 2024 09:27:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704476; cv=none; b=N9NiKaSuyk5sIy3X74SEolfssLIKOURjZ1g/lPC78lH8CykCB8yPLHf7ItQWJlOPdp/CC1nWQCtmlTpfM00ClbdDvrVwWSVeJIaLeL8pBGjptvaNNx0Vqqe+9byLYOlPhgHEJ7Yo2Un+dMraxvu/eQqQGPWz9EmNotk3XUsbOIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704476; c=relaxed/simple; bh=kFYDos5oOuWgkjmYMwk9XxLgUS9cjG+wC5rkcBK9y+M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MRgUedw2qnpMsYoBNgF+A59BXDzNmuqfqWvI7cKlCEsAMtacEg09lAMYlpy7+D/+xarpNDUw89WHKj+FJnNQgTyGHCRREKNy6nMOflVNTIyMeMpsu2FXGISqcYirZU7riZA0EMpr4G5QkUkSVgSqZfvbydSgg4P31xzFiRwSgZ8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=LJEHAOEX; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="LJEHAOEX" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6e88e4c8500so1500828b3a.2 for ; Fri, 29 Mar 2024 02:27:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704475; x=1712309275; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AWJBCH09eu6e6/Y/jgxKzI6AZAa7BXYvEZEuKCZc7nk=; b=LJEHAOEXbmpdLGymnH1Slp9iJZNh7Z2+VK2iLh5CS7SjuzLoCvou6ZsWxFxyQfwoEv Cb8iE9m+wW9K5lTcfCgqGFlss3W+w1DqBd8wdunA2QTsV3NL9JVdqYjFuF8G8kFzIKmB aJWlsNrNBWGiLm6SMFJPD9UHCHWNGM0xZIrYqJVOESB9yQQjvnlJFiMbba7piMh37vTH MHFKZR4UOhRK1tXQvBAarb84ZLnBasrIlwrAIGhMFJBvTM+ECsqFQSH7jC3esPx9jJZz mGa4ENT3h0GuJ1CK2Yqy3nvn46H1GE+6Gvj5PsVzbIK06rqRaFLxpAajWd/617EvtfVx l6wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704475; x=1712309275; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AWJBCH09eu6e6/Y/jgxKzI6AZAa7BXYvEZEuKCZc7nk=; b=Scy1DwpUwytSmB8bCJM1B7A7vb1jxP1U01A0ZurGjLeMV8H8SHZp9rX5OHmvrNM7Ae FLs+h6ePfxZl89k6/NCvvK8nAFS374RTmXvXGz8s7tX4AW/N3P+NsnkGrabMbXWF5LMS 10Gp/jsnw8neDuwUXCdmlq2pqB62cuW+SRkxmqgmmvZeWlwjNxU62TOd45zG9rWwmNuw BF6MdH2sbzKwHtRxo2z3N3KSAg1DYm7a7mUY6tBYfRhaOQV0CktD8Jja1UJUVpm7+s6u emtuYVIxpfLED8p5lXXbk/o8HUBnx+LJbt11i4Iyyo8KgOAskSB1kKnx2QrF7Ji271md uhxw== X-Forwarded-Encrypted: i=1; AJvYcCU868qAeTyWNL8Kdz6rVrX4bNnxnS90Pr1CEsaqHpnPcqwG3zW3fu4kfuSlxxOh5QWCTmjnniUFXFgipzhJ40ZP1YT9 X-Gm-Message-State: AOJu0YwhTobfBFeSj3pTJ07Dtt1si9QsPw9Ato0XCFvq11uppfeVrha9 bTKMF0y82a0uMb322rdbursIsds8sgC+1oJIQC6n7Oka+dMaL9mXgNNhsRMgnHk= X-Google-Smtp-Source: AGHT+IHveAaHJ+i93XoWQQhAxL1npi1lTK697/I+K/Ux4G4x9neoQ8w5TBypEt7P1DanmINkW4zEcQ== X-Received: by 2002:a05:6a21:3986:b0:1a3:af50:18bd with SMTP id ad6-20020a056a21398600b001a3af5018bdmr1630725pzc.28.1711704474638; Fri, 29 Mar 2024 02:27:54 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:54 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:20 +0800 Subject: [PATCH RFC 04/11] riscv: Add Sdtrig CSRs definition, Smstateen bit to access Sdtrig CSRs Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-4-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 Add hcontext/scontext CSRs definition to csr.h As riscv-state-enable [1] Smstateen extension spec: Sdtrig CSRs: hcontext/scontext availability are controlled by bit 57 of Smstateen CSRs. Link: https://github.com/riscvarchive/riscv-state-enable/releases/download/v1.0.0/Smstateen.pdf [1] Signed-off-by: Max Hsu --- arch/riscv/include/asm/csr.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 2468c55933cd..308ae795dc82 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -204,6 +204,8 @@ #define ENVCFG_FIOM _AC(0x1, UL) /* Smstateen bits */ +#define SMSTATEEN0_HSCONTEXT_SHIFT 57 +#define SMSTATEEN0_HSCONTEXT (_ULL(1) << SMSTATEEN0_HSCONTEXT_SHIFT) #define SMSTATEEN0_AIA_IMSIC_SHIFT 58 #define SMSTATEEN0_AIA_IMSIC (_ULL(1) << SMSTATEEN0_AIA_IMSIC_SHIFT) #define SMSTATEEN0_AIA_SHIFT 59 @@ -480,6 +482,10 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) +/* riscv-debug-spec: Sdtrig extension */ +#define CSR_SCONTEXT 0x5a8 +#define CSR_HCONTEXT 0x6a8 + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ From patchwork Fri Mar 29 09:26:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610462 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB95A5D8FD for ; Fri, 29 Mar 2024 09:27:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704481; cv=none; b=H9Z0RQSfSlorWiBXuXu9/ZqY0E5Z0qh/NPQlrLTjvvoHlTl6Jna9lf6kI+k7qJ+wK77ZD4DmgFsmOyzShj0iXX/UuzWZuN72o1ECxoVVpzQxHtAqDq5++tgf0SL51OE+cTyb1jmi0Uu+Lt+WOqFv1BBBbFXWSRJ6DrRafWL27fs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704481; c=relaxed/simple; bh=byQyJ+mUVDPrSJinRBDLAgeflaiBNndaObFYJicDYXw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JKvmVRWJaBJDAg7nZE0LW2qihyd96NSpNvwWAi4tSEupDof7YoIjVigc0aS3mXkQmKR45LvL4LyK8iclg9p5jxG60EVHOBgFhIqd80/Fn19ww6e6LTMnJzn8kMFr3BfVjUkYIE1EIQLShfouKXSZz00SFkY7ke6KGORjjA/0cWg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=bxepa0GE; arc=none smtp.client-ip=209.85.216.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="bxepa0GE" Received: by mail-pj1-f47.google.com with SMTP id 98e67ed59e1d1-2a02c4dffd2so1531261a91.0 for ; Fri, 29 Mar 2024 02:27:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704478; x=1712309278; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YfructPGSDbFIY5KANyP0OUZ/rAlg6UVQSMNURcUx/Q=; b=bxepa0GEVFLUDtuop8ELhwkgu/KuNGfRsK2zCJU2wDPijHaYc1lkgyt/Ao78GDKEqy dtsgMQe/rOnp00h9D8Zy19p0OExENv4jjRaRBIJ0QEujxXlkhBe+hW5skSYXVyg2chnl RpX9pN9MdMT5XV3Ek5L/iHVY/oIT55kPx3+ef0d2suATgm0ivZRpGXm+Sb5MsHM9XFuQ O440QmxmXNWNCjucNWCkNZypl3RgEreezbGv02KQO0WMrOLWXu4oiOtTM3LlOdmvL8Im SCTTK/sRoCkHHKVqymFY48ubOH1AI6xjYGuJMMZBuuw+hOVeDjx72G+m0z/DzC/zL3b0 J8yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704478; x=1712309278; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YfructPGSDbFIY5KANyP0OUZ/rAlg6UVQSMNURcUx/Q=; b=KHS1oWE3SCP+Vc1bAngJsna1uuJYV4Mr7Xt30cnKjOHvTdnX/MR/YCaW4FQJYN16z+ 5MnXKickAAqoReRMzgoFLpEmGph0dGJFr0U++PriLNqgNPYP18TQMVZzy2QbZJ7Hab64 4h8V54yMsXUFCX+jk5naFgk5Mdz0e2qXPpx823Q7UHWMUOV+sbRMx63pfL4Toq2ENgq8 hswj7jjtnuYQ9YuUou8NWcIKGxENiSspFFy7oDngxSp0LjYXxP/5FaT1bL4mphgRcFYo 4LIPBDtKIST7T1xyntQXbsM30R9FSDfsvRSjsqO4iP5HIYE4+Uktvm0gI3w4kWdeSDXQ tiKw== X-Forwarded-Encrypted: i=1; AJvYcCUIxq2qTmutwXtYMC4/Fwzto7bNj/DsHAZ2bJTQp4GsuYhGh2vppEpyut1RYUIb2bs2MWWu4oV39jzqNd9TFED3M7g5 X-Gm-Message-State: AOJu0Yy/qgnDyCbIgJgHIXYmqnk80JA8fC3StDOv+pwu02T+hWHZOygs pfiX0/f9EPf/f2binEsha14tkVFriplHRgI5WvIrQffQcRPIctP2p1dZ1C1zkKI= X-Google-Smtp-Source: AGHT+IEgRCohje6FoItkAA90Oov//fQs26jLa2d7M0gq96y2GMdC43oOYqp9fbQEYyu5BFzz1OlNNA== X-Received: by 2002:a17:90a:7d02:b0:2a0:4495:1f3d with SMTP id g2-20020a17090a7d0200b002a044951f3dmr2125693pjl.0.1711704478186; Fri, 29 Mar 2024 02:27:58 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:57 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:21 +0800 Subject: [PATCH RFC 05/11] riscv: cpufeature: Add Sdtrig optional CSRs checks Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-5-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 Sdtrig extension introduce two optional CSRs [hcontext/scontext], that will be storing PID/Guest OS ID for the debug feature. The availability of these two CSRs will be determined by DTS and Smstateen extension [h/s]stateen0 CSR bit 57. If all CPUs hcontext/scontext checks are satisfied, it will enable the use_hcontext/use_scontext static branch. Signed-off-by: Max Hsu --- arch/riscv/include/asm/switch_to.h | 6 ++ arch/riscv/kernel/cpufeature.c | 161 +++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..07432550ed54 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -69,6 +69,12 @@ static __always_inline bool has_fpu(void) { return false; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif +DECLARE_STATIC_KEY_FALSE(use_scontext); +static __always_inline bool has_scontext(void) +{ + return static_branch_likely(&use_scontext); +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 080c06b76f53..44ff84b920af 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -35,6 +35,19 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; +atomic_t hcontext_disable; +atomic_t scontext_disable; + +DEFINE_STATIC_KEY_FALSE_RO(use_hcontext); +EXPORT_SYMBOL(use_hcontext); + +DEFINE_STATIC_KEY_FALSE_RO(use_scontext); +EXPORT_SYMBOL(use_scontext); + +/* Record the maximum number that the hcontext CSR allowed to hold */ +atomic_long_t hcontext_id_share; +EXPORT_SYMBOL(hcontext_id_share); + /** * riscv_isa_extension_base() - Get base extension word * @@ -719,6 +732,154 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } +static void __init sdtrig_percpu_csrs_check(void *data) +{ + struct device_node *node; + struct device_node *debug_node; + struct device_node *trigger_module; + + unsigned int cpu = smp_processor_id(); + + /* + * Expect every cpu node has the [h/s]context-present property + * otherwise, jump to sdtrig_csrs_disable_all to disable all access to + * [h/s]context CSRs + */ + node = of_cpu_device_node_get(cpu); + if (!node) + goto sdtrig_csrs_disable_all; + + debug_node = of_get_compatible_child(node, "riscv,debug-v1.0.0"); + of_node_put(node); + + if (!debug_node) + goto sdtrig_csrs_disable_all; + + trigger_module = of_get_child_by_name(debug_node, "trigger-module"); + of_node_put(debug_node); + + if (!trigger_module) + goto sdtrig_csrs_disable_all; + + if (!(IS_ENABLED(CONFIG_KVM) && + of_property_read_bool(trigger_module, "hcontext-present"))) + atomic_inc(&hcontext_disable); + + if (!of_property_read_bool(trigger_module, "scontext-present")) + atomic_inc(&scontext_disable); + + of_node_put(trigger_module); + + /* + * Before access to hcontext/scontext CSRs, if the smstateen + * extension is present, the accessibility will be controlled + * by the hstateen0[H]/sstateen0 CSRs. + */ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SMSTATEEN)) { + u64 hstateen_bit, sstateen_bit; + + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_h)) { +#if __riscv_xlen > 32 + csr_set(CSR_HSTATEEN0, SMSTATEEN0_HSCONTEXT); + hstateen_bit = csr_read(CSR_HSTATEEN0); +#else + csr_set(CSR_HSTATEEN0H, SMSTATEEN0_HSCONTEXT >> 32); + hstateen_bit = csr_read(CSR_HSTATEEN0H) << 32; +#endif + if (!(hstateen_bit & SMSTATEEN0_HSCONTEXT)) + goto sdtrig_csrs_disable_all; + + } else { + if (IS_ENABLED(CONFIG_KVM)) + atomic_inc(&hcontext_disable); + + /* + * In RV32, the smstateen extension doesn't provide + * high 32 bits of sstateen0 CSR which represent + * accessibility for scontext CSR; + * The decision is left on whether the dts has the + * property to access the scontext CSR. + */ +#if __riscv_xlen > 32 + csr_set(CSR_SSTATEEN0, SMSTATEEN0_HSCONTEXT); + sstateen_bit = csr_read(CSR_SSTATEEN0); + + if (!(sstateen_bit & SMSTATEEN0_HSCONTEXT)) + atomic_inc(&scontext_disable); +#endif + } + } + + /* + * The code can only access hcontext/scontext CSRs if: + * The cpu dts node have [h/s]context-present; + * If Smstateen extension is presented, then the accessibility bit + * toward hcontext/scontext CSRs is enabled; Or the Smstateen extension + * isn't available, thus the access won't be blocked by it. + * + * With writing 1 to the every bit of these CSRs, we retrieve the + * maximum bits that is available on the CSRs. and decide + * whether it's suit for its context recording operation. + */ + if (IS_ENABLED(CONFIG_KVM) && + !atomic_read(&hcontext_disable)) { + unsigned long hcontext_available_bits = 0; + + csr_write(CSR_HCONTEXT, -1UL); + hcontext_available_bits = csr_swap(CSR_HCONTEXT, hcontext_available_bits); + + /* hcontext CSR is required by at least 1 bit */ + if (hcontext_available_bits) + atomic_long_and(hcontext_available_bits, &hcontext_id_share); + else + atomic_inc(&hcontext_disable); + } + + if (!atomic_read(&scontext_disable)) { + unsigned long scontext_available_bits = 0; + + csr_write(CSR_SCONTEXT, -1UL); + scontext_available_bits = csr_swap(CSR_SCONTEXT, scontext_available_bits); + + /* scontext CSR is required by at least the sizeof pid_t */ + if (scontext_available_bits < ((1UL << (sizeof(pid_t) << 3)) - 1)) + atomic_inc(&scontext_disable); + } + + return; + +sdtrig_csrs_disable_all: + if (IS_ENABLED(CONFIG_KVM)) + atomic_inc(&hcontext_disable); + + atomic_inc(&scontext_disable); +} + +static int __init sdtrig_enable_csrs_fill(void) +{ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SDTRIG)) { + atomic_long_set(&hcontext_id_share, -1UL); + + /* check every CPUs sdtrig extension optional CSRs */ + sdtrig_percpu_csrs_check(NULL); + smp_call_function(sdtrig_percpu_csrs_check, NULL, 1); + + if (IS_ENABLED(CONFIG_KVM) && + !atomic_read(&hcontext_disable)) { + pr_info("riscv-sdtrig: Writing 'GuestOS ID' to hcontext CSR is enabled\n"); + static_branch_enable(&use_hcontext); + } + + if (!atomic_read(&scontext_disable)) { + pr_info("riscv-sdtrig: Writing 'PID' to scontext CSR is enabled\n"); + static_branch_enable(&use_scontext); + } + } + return 0; +} + +arch_initcall(sdtrig_enable_csrs_fill); + void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ)) From patchwork Fri Mar 29 09:26:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610463 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C8E569DE4 for ; Fri, 29 Mar 2024 09:28:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704484; cv=none; b=Je4IxilVmXUNuNj0XsWR+x7CSOkIzSimAAQtP55xymi+g6lVlWEJwXhRkhAA8tpThDXvQO9ckUE5mhkvvukO7J5p6QChqDWeeGpcNKZuwswMvn/M0+lgLBPrObvjb7DTGqjB3gYBUlOSbQgisfFiyYdgoMJwHTRijqUKQkzfRGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704484; c=relaxed/simple; bh=CV2JPbXziG2CSHm4cLDaE9gjUQ7JZv4SP9wDAVQhAuk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lS3345jt8pVg81FaEU+5i+sW+psYqdX5qdbW4OWAK85MOF2pZYNtYYo75B5ew86KaCzOEzT/cR0gWl7Tq0Qqpez5tJRbv5dvpQCZrQjWBfuvwaz2d8Ze6q+ER+Y0mN1N6WqedcXtMn+xpqxpC3MIcldmYUuIEXN5jKTbW4MZ7C8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=iL5W1W8H; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="iL5W1W8H" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-6e6fb9a494aso1580564b3a.0 for ; Fri, 29 Mar 2024 02:28:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704482; x=1712309282; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=W2BJOQ9wxa5k0Z60PWQjy0KWSd8OFBHkeE+vEvJtEEk=; b=iL5W1W8HpY43VjvnsAI/T5ubmyHaDFyhfwCn57dVpP3KsB+wrajKxQcvQu57nPaCTl Cuvdx/UTbJOi1AP5K1mly0Euj8cs29yYogB+ZN7zfxAuPH7cA8rp4AFY7PSAlhP/9coK IIzzzCIe09J2K2ttTc1qfBhTgF8QSyc2wo5YodyHv28EEt/IWyx7SE0Fl5TsF1IamAKT D8t20Zr7U0+g4xg7FoVhKO9UCSqI5Ndcj/uLafNogFMaYN+FrO6CVXPBg9pai2tLw76h FbuW1mbHK/7cq5507pkpKAOEUhgu7nofzn6oxg8s9PpErUVhxZJESRwGsQU0vRqlGMVs LU9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704482; x=1712309282; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W2BJOQ9wxa5k0Z60PWQjy0KWSd8OFBHkeE+vEvJtEEk=; b=RezwU71waz1BmxeXN8BQlFEhomYVgzYP/dCEOWH7niEL0nU4YwCxOr13Hf7jCoaukm jH6qSiEmh8JUYuLuMutGExr3phOzRAQCXEaot7i4KJ8NDhnaxl7hDB65/nhldCvANM56 SH4+qBloElamuz0iVfl1o06+wIEAUVWj/HTEeLU1eV5e9R+F+A7Nq+162Kx+8V/7C/EC iBD/Ura0EDK0Dz0ZUVqdzhCjYtBRrFBXpx+blcOuv6f1mRGhYQXcsYqN+pub/9+kV+AY lLNFIBKAfjfAyk0TaFwB651ZL0ox2tmxShmFtAogPh0IhsM1wHk99xroanat8l+sSmw/ DhWg== X-Forwarded-Encrypted: i=1; AJvYcCXmScYt4xO/8Jx+lJBpcy1vuCOlbo+5PVVRC6AJ3WcJk7bcBAg932B83TkVy98387NMpa/G7pps/SfJ2AWzpWarHcxw X-Gm-Message-State: AOJu0YwvTbC3MZMIF4J1vSHTd7+PZTrOpqnHUuKHr+WL92Y7ZHGsU/4M X0EI2CvOUE1OGnflo9O1ObU8HGMFNgNZ3hserBsPFu38OMUO16wfCZ4SSZ8bHKw= X-Google-Smtp-Source: AGHT+IF+IG00xBHcuGEuM8FjBpouIXGd2i1O2spwYlcOfF/yskdrf4gmePYkFHJj5HCFiJOPwSSmXA== X-Received: by 2002:a05:6a20:89a4:b0:1a3:ae18:f1e4 with SMTP id h36-20020a056a2089a400b001a3ae18f1e4mr1227195pzg.34.1711704481705; Fri, 29 Mar 2024 02:28:01 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:01 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:22 +0800 Subject: [PATCH RFC 06/11] riscv: suspend: add Smstateen CSRs save/restore Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-6-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 From Smstateen extension: the values of the [h/s]stateen CSRs will be lost when entering a non-retentive idle state. Therefore, these CSRs values need to be restored to ensure that the corresponding functionality remains enabled. Signed-off-by: Max Hsu --- arch/riscv/include/asm/suspend.h | 6 ++++++ arch/riscv/kernel/suspend.c | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 4718096fa5e3..2ecace073869 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -17,6 +17,12 @@ struct suspend_context { unsigned long envcfg; unsigned long tvec; unsigned long ie; +#if __riscv_xlen < 64 + unsigned long hstateen0h; +#endif + unsigned long hstateen0; + unsigned long sstateen0; + #ifdef CONFIG_MMU unsigned long satp; #endif diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index 8a327b485b90..a086da222872 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -19,6 +19,15 @@ void suspend_save_csrs(struct suspend_context *context) context->envcfg = csr_read(CSR_ENVCFG); context->tvec = csr_read(CSR_TVEC); context->ie = csr_read(CSR_IE); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_h)) { +#if __riscv_xlen < 64 + context->hstateen0h = csr_read(CSR_HSTATEEN0H); +#endif + context->hstateen0 = csr_read(CSR_HSTATEEN0); + } + context->sstateen0 = csr_read(CSR_SSTATEEN0); + } /* * No need to save/restore IP CSR (i.e. MIP or SIP) because: @@ -42,6 +51,15 @@ void suspend_restore_csrs(struct suspend_context *context) csr_write(CSR_ENVCFG, context->envcfg); csr_write(CSR_TVEC, context->tvec); csr_write(CSR_IE, context->ie); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) { + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_h)) { +#if __riscv_xlen < 64 + csr_write(CSR_HSTATEEN0H, context->hstateen0h); +#endif + csr_write(CSR_HSTATEEN0, context->hstateen0); + } + csr_write(CSR_SSTATEEN0, context->sstateen0); + } #ifdef CONFIG_MMU csr_write(CSR_SATP, context->satp); From patchwork Fri Mar 29 09:26:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610464 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2301C6A037 for ; Fri, 29 Mar 2024 09:28:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704487; cv=none; b=M3s/wmpKsO4izZBsBQ8FRsIGYOK76v1VfhI489NEzpLAJf8ISNdxK3vXgO2SN0rTQgKCfhA9BBrgW/vBTUFdnERYfTh36S2/8LC4FnhRSj5LXOUfWwyMqMeurpdnv8kCdZuGSQDVQK1J6NqZRkyj01Hprn9s4fQp1XmTU5+uaSk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704487; c=relaxed/simple; bh=aYxwIoa5oYGQg8jCIXD+qDStt+bScyurvWfoZf9ca1o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f+UyhIeksc0bEEbx3ccAtw5c5M4QeXUxeixm0iacIk2RvUg2xX7XkYsRNn7hJ2niX7z0d3OV3i0DGjNcLwWEMvmhg7BkMGcZcg3sILGwK+J3UOD0UDyWo+KsmZ0L1VUlb0Pn4KJq5lfuwAgxMQLg95EYMcR7Jpt7i61lzKz/G9c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=Wv3Se+ip; arc=none smtp.client-ip=209.85.216.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Wv3Se+ip" Received: by mail-pj1-f52.google.com with SMTP id 98e67ed59e1d1-29f749b6667so1316386a91.0 for ; Fri, 29 Mar 2024 02:28:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704485; x=1712309285; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2me2ctA/QJ+WDbqGcKl2bMmK6E0Eh2HMfIwB//6qG84=; b=Wv3Se+ipLwX7BaXC8mc9OVgZLMWWwl2aQ5g0wKk7JFUVqgpbxaIkAz4jAIQvr5zPR+ wJI6gc1xj5e45Le+xmGkj8FRc5cSMqpYGdPlnF1GXJUqniLGUunR02g7KHc+JzvRv4N6 Xdt1BN9vHfz/gujH+Ls7JrlWKjlHhVGBMx/IlOFioZpORbH3km2aUylELqEVdx4BKFEh OXroAsuI1Ru7h1ry6MKwusQ1K/UlCJ/hjrF6UFr1n+e2XOCjGYid9x7vQ4wRL7bCOll9 ockv9yKI6dWdk3xXwOeIMINnH+vCgzJPiWwtABBZOc32d9CcOWRjL7y6toOgQjsQo/o/ tdHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704485; x=1712309285; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2me2ctA/QJ+WDbqGcKl2bMmK6E0Eh2HMfIwB//6qG84=; b=Egg/j9FiqjfhskH/5f1cBlDFiAsdMQdTWRQ9CJ3Xytv3nM3yWSCJlqFccvkNHpVhh+ pIyGIor+Uonanvqhb0iiULuGftMifEwQPqIxQ9DrxFyIah3XsuTvDLAekFa6ScPsqOT4 oQoKqbgJCAveFuEkQnyMqK1mTK6Q3EW3/qmLyarmRWiBKZrWRq9gmN/pPVJ8liNgRhr8 VWT6/B9GcSP+VLEX+QnN8+1J7iecHeq476ALZqjABYNjOX9kVqlrJto8EmDzJGUBAxd5 M2WPJdMW7qM+tmqYNm+HD9JQzHEHTUAHP+sQMtQFRz5lXe+QxpBLpkJqQgd8IAp8imKi dbKQ== X-Forwarded-Encrypted: i=1; AJvYcCUNSzdDuXXK5Pzib7LsngIG6G3joUqISrY/bGoLW2cVeN+PrqQclRplbGVNZ3u4nebpp7G1armtLQyHhEiy4q+NW3Fi X-Gm-Message-State: AOJu0YxfR/XDxq9qScNyfqkI8sJ8A9ESJ+n6jOxLW0+8yaxM3P6p3+wJ XkwvYanV+AUQSwYEXp2tRIZr1SSyhozbXlaW0yaCVg1lXTJFr8yJtcmFEQwmX74= X-Google-Smtp-Source: AGHT+IGdY03xWXQByMBRxphQC1Vc3BZVaeHeBgA9jftNMkoc3op5kWSNSp3jA7sJf0LUKMcaom5H1Q== X-Received: by 2002:a17:90a:7f84:b0:2a2:d48:9d50 with SMTP id m4-20020a17090a7f8400b002a20d489d50mr1744971pjl.44.1711704485323; Fri, 29 Mar 2024 02:28:05 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:05 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:23 +0800 Subject: [PATCH RFC 07/11] riscv: Add task switch support for scontext CSR Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-7-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu , Nick Hu X-Mailer: b4 0.13.0 Write the next task PID to the scontext CSR if the use_scontext static branch is enabled by the detection of the cpufeature.c The scontext CSR needs to be saved and restored when entering a non-retentive idle state so that when resuming the CPU, the task's PID on the scontext CSR will be correct. Co-developed-by: Nick Hu Signed-off-by: Nick Hu Signed-off-by: Max Hsu --- arch/riscv/include/asm/suspend.h | 1 + arch/riscv/include/asm/switch_to.h | 9 +++++++++ arch/riscv/kernel/suspend.c | 7 +++++++ 3 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/suspend.h b/arch/riscv/include/asm/suspend.h index 2ecace073869..5021cad7e815 100644 --- a/arch/riscv/include/asm/suspend.h +++ b/arch/riscv/include/asm/suspend.h @@ -13,6 +13,7 @@ struct suspend_context { /* Saved and restored by low-level functions */ struct pt_regs regs; /* Saved and restored by high-level functions */ + unsigned long scontext; unsigned long scratch; unsigned long envcfg; unsigned long tvec; diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 07432550ed54..289cd6b60978 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -75,6 +76,12 @@ static __always_inline bool has_scontext(void) return static_branch_likely(&use_scontext); } +static __always_inline void __switch_to_scontext(struct task_struct *__prev, + struct task_struct *__next) +{ + csr_write(CSR_SCONTEXT, task_pid_nr(__next)); +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); @@ -86,6 +93,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (has_scontext()) \ + __switch_to_scontext(__prev, __next); \ ((last) = __switch_to(__prev, __next)); \ } while (0) diff --git a/arch/riscv/kernel/suspend.c b/arch/riscv/kernel/suspend.c index a086da222872..6b403a1f75c3 100644 --- a/arch/riscv/kernel/suspend.c +++ b/arch/riscv/kernel/suspend.c @@ -11,9 +11,13 @@ #include #include #include +#include void suspend_save_csrs(struct suspend_context *context) { + if (has_scontext()) + context->scontext = csr_read(CSR_SCONTEXT); + context->scratch = csr_read(CSR_SCRATCH); if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) context->envcfg = csr_read(CSR_ENVCFG); @@ -46,6 +50,9 @@ void suspend_save_csrs(struct suspend_context *context) void suspend_restore_csrs(struct suspend_context *context) { + if (has_scontext()) + csr_write(CSR_SCONTEXT, context->scontext); + csr_write(CSR_SCRATCH, context->scratch); if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_XLINUXENVCFG)) csr_write(CSR_ENVCFG, context->envcfg); From patchwork Fri Mar 29 09:26:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610465 Received: from mail-pg1-f174.google.com (mail-pg1-f174.google.com [209.85.215.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 922886A8AC for ; Fri, 29 Mar 2024 09:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704492; cv=none; b=lCKOspTlA8EqgmQ+5/0BA8tL2fPlZoCoZHxDjVuA6cubGRQx24+J2YNTvKrg5ghUZ8g/rSyTs7FQH/nhODqxhG82woTJb3OcQNzJaLpLvwukmzV8d8hkyv3BIDKiscbxhXri9CUHElDJOI1+kFYiFKGfZwNPAwCK+niWdMlp3QM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704492; c=relaxed/simple; bh=pKwxjdFDS7fPWD1+VB8s01FYk9Vaq5YiFiXqXB5BVW4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dIWed3R4zonEjoTjjYtjfx6JnEruLIMuJwWxXasC1o38kaOFtxr0U1rAJWwKkJVoEeQZuinV4fMH8BiOMdnTF6o+9ONALO8CAq/mu6mAaR+jIFAUwZNQ7UtR3zhqu9zTnP2I/okShnt3RdhRUH9PhEcoWvKWZryTn0XsP2tbtTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=ngyf2QmO; arc=none smtp.client-ip=209.85.215.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="ngyf2QmO" Received: by mail-pg1-f174.google.com with SMTP id 41be03b00d2f7-5d3912c9a83so1065018a12.3 for ; Fri, 29 Mar 2024 02:28:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704489; x=1712309289; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kNl7zpQXvXrARiVNVkvkffUb5fHwj0L+2J3rA8qc0Og=; b=ngyf2QmO6mG4dNbKrt5LDN5cn6Nar4KHRC4hVBvFjGkXmP6iO9XOnfEp1MkpFrStIR UxuIgFD5ut95EU25UzZDldpka+SQ7WQBmQe31MO8ADOVMrT2Igsxfu1mzs70fHjECbRA N21jfvO4Ar4BisUSsHln1GL6SW8VmrUztkfMmBNP9Ced3F5AFXA7/Ya2Pw9HIqnv/zb/ JD0x8/o8F9V5SmZqyFMaYkW+6ZqXqMF0aT/HlayEJwZRer0ElhieEs1xWV7j2Jasc9rv tiAbuQwnbec5rmLkdNDb49oDLvJ9w0Rc5DlvR7kR0SycalTfH1QMh+6z1Ogslt6xy7D8 DO6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704489; x=1712309289; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kNl7zpQXvXrARiVNVkvkffUb5fHwj0L+2J3rA8qc0Og=; b=dn3Xzw4pIw/ELGN3Yi/oaKMSCI24AYh3FVBZEcTuYuSCpLmjYxUxH4vQDIFdH5eCJb mnNAlsy58RQNkhEYnMrAARl5N0oZFyf/8G3ikIt3nvKU5BYvsMHDZQEkPL5U8BozZNFw S84WR4a8EfFMbu6W8KnE5M12zbQN6njbJ5CjhXAW7r+u7iljCqOic45EjRNKB5ZjI0Jw dMVTotCGluHfAWzWT35xpGgMbtts0PcR48pwxNV6VckDA7kPZ0KJxF/f6jAfV/0j4nSA TWZAaDDJLx8lHmFRssySPhlopHvu/U3/Dgmjzb5FETuV3O8FUFfXpxonyzS7vTS/0wXD Xy3w== X-Forwarded-Encrypted: i=1; AJvYcCXR6cWSi0Rr6HkeTCDrT3mqZcAkqGWqd8YE0yF89PW3eFg/vxb/XATVrv2MrfCPFY9cWR65kH8DlB/DSbO2VO2A4D3y X-Gm-Message-State: AOJu0YwhvveLSkTejp0irvSeibDxAK5jfl6ieeTPKQn8ZqFOdLGrFDKD Us2RYOvuvxMECOJybKif05DGp8tPfZm9TveJQNm5/pDot0PT8hxRAltxsuyfR4w= X-Google-Smtp-Source: AGHT+IGke3TYJDotnJqdt1iP+scqdGmagpwPxA2ur5Kz3bFCD/ukFY00kNWufcTpRyFgA8aurgnlgg== X-Received: by 2002:a17:90a:3ea7:b0:29d:dbaf:bd77 with SMTP id k36-20020a17090a3ea700b0029ddbafbd77mr1594311pjc.43.1711704488865; Fri, 29 Mar 2024 02:28:08 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:08 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:24 +0800 Subject: [PATCH RFC 08/11] riscv: KVM: Add Sdtrig Extension Support for Guest/VM Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-8-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu , Yong-Xuan Wang X-Mailer: b4 0.13.0 From: Yong-Xuan Wang We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Sdtrig extension for Guest/VM. We also save/restore the scontext CSR for guest VCPUs and set the HSCONTEXT bit in hstateen0 CSR if the scontext CSR is available for Guest/VM when the Smstateen extension is present. Signed-off-by: Yong-Xuan Wang Co-developed-by: Max Hsu Signed-off-by: Max Hsu --- arch/riscv/include/asm/kvm_host.h | 11 +++++++++++ arch/riscv/include/asm/kvm_vcpu_debug.h | 17 +++++++++++++++++ arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/vcpu.c | 8 ++++++++ arch/riscv/kvm/vcpu_debug.c | 29 +++++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_onereg.c | 1 + 7 files changed, 68 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index 484d04a92fa6..d495279d99e1 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -21,6 +21,7 @@ #include #include #include +#include #define KVM_MAX_VCPUS 1024 @@ -175,6 +176,10 @@ struct kvm_vcpu_smstateen_csr { unsigned long sstateen0; }; +struct kvm_vcpu_sdtrig_csr { + unsigned long scontext; +}; + struct kvm_vcpu_arch { /* VCPU ran at least once */ bool ran_atleast_once; @@ -197,6 +202,9 @@ struct kvm_vcpu_arch { unsigned long host_senvcfg; unsigned long host_sstateen0; + /* SCONTEXT of Host */ + unsigned long host_scontext; + /* CPU context of Host */ struct kvm_cpu_context host_context; @@ -209,6 +217,9 @@ struct kvm_vcpu_arch { /* CPU Smstateen CSR context of Guest VCPU */ struct kvm_vcpu_smstateen_csr smstateen_csr; + /* CPU Sdtrig CSR context of Guest VCPU */ + struct kvm_vcpu_sdtrig_csr sdtrig_csr; + /* CPU context upon Guest VCPU reset */ struct kvm_cpu_context guest_reset_context; diff --git a/arch/riscv/include/asm/kvm_vcpu_debug.h b/arch/riscv/include/asm/kvm_vcpu_debug.h new file mode 100644 index 000000000000..6e7ce6b408a6 --- /dev/null +++ b/arch/riscv/include/asm/kvm_vcpu_debug.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2024 SiFive + * + * Authors: + * Yong-Xuan Wang + */ + +#ifndef __KVM_VCPU_RISCV_DEBUG_H +#define __KVM_VCPU_RISCV_DEBUG_H + +#include + +void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu); +void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu); + +#endif diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index b1c503c2959c..9f70da85ed51 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZFA, KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, + KVM_RISCV_ISA_EXT_SDTRIG, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/Makefile b/arch/riscv/kvm/Makefile index c9646521f113..387be968d9ea 100644 --- a/arch/riscv/kvm/Makefile +++ b/arch/riscv/kvm/Makefile @@ -15,6 +15,7 @@ kvm-y += vmid.o kvm-y += tlb.o kvm-y += mmu.o kvm-y += vcpu.o +kvm-y += vcpu_debug.o kvm-y += vcpu_exit.o kvm-y += vcpu_fp.o kvm-y += vcpu_vector.o diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b5ca9f2e98ac..1d0e43ab0652 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -20,6 +20,7 @@ #include #include #include +#include const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { KVM_GENERIC_VCPU_STATS(), @@ -504,6 +505,9 @@ static void kvm_riscv_vcpu_setup_config(struct kvm_vcpu *vcpu) SMSTATEEN0_AIA_ISEL; if (riscv_isa_extension_available(isa, SMSTATEEN)) cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0; + + if (has_scontext()) + cfg->hstateen0 |= SMSTATEEN0_HSCONTEXT; } } @@ -643,6 +647,8 @@ static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_vcpu * (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) vcpu->arch.host_sstateen0 = csr_swap(CSR_SSTATEEN0, smcsr->sstateen0); + + kvm_riscv_debug_vcpu_swap_in_guest_context(vcpu); } static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *vcpu) @@ -656,6 +662,8 @@ static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_vcpu *v (cfg->hstateen0 & SMSTATEEN0_SSTATEEN0)) smcsr->sstateen0 = csr_swap(CSR_SSTATEEN0, vcpu->arch.host_sstateen0); + + kvm_riscv_debug_vcpu_swap_in_host_context(vcpu); } /* diff --git a/arch/riscv/kvm/vcpu_debug.c b/arch/riscv/kvm/vcpu_debug.c new file mode 100644 index 000000000000..e7e9263c2e30 --- /dev/null +++ b/arch/riscv/kvm/vcpu_debug.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 SiFive + */ + +#include +#include + +void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr; + unsigned long hcontext = vcpu->kvm->arch.hcontext; + + if (has_hcontext()) + csr_write(CSR_HCONTEXT, hcontext); + if (has_scontext()) + vcpu->arch.host_scontext = csr_swap(CSR_SCONTEXT, csr->scontext); +} + +void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr; + + /* Hypervisor uses the hcontext ID 0 */ + if (has_hcontext()) + csr_write(CSR_HCONTEXT, 0); + if (has_scontext()) + csr->scontext = csr_swap(CSR_SCONTEXT, vcpu->arch.host_scontext); +} diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index f4a6124d25c9..10dda5ddc0a6 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -34,6 +34,7 @@ static const unsigned long kvm_isa_ext_arr[] = { [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, /* Multi letter extensions (alphabetically sorted) */ + KVM_ISA_EXT_ARR(SDTRIG), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), From patchwork Fri Mar 29 09:26:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610466 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 698E36FE21 for ; Fri, 29 Mar 2024 09:28:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704495; cv=none; b=KU8bEwz9ucmjpDmMFmaGIy7MU4+nTDOLl2rA2wc5AOhUdhqqrqf9VYZ4ttM9drGgmqQtPS+nZ+i+sOALIuIsIOjW8QOJdVYyNDPxvrpOP5BOKOh16qi1El3QenzcrGJn0Z4nwMgtahgKPi6G5RVFmtv4Fdp0lnz3uSmPCav8hXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704495; c=relaxed/simple; bh=S2OuTXD/Hjwavyzf8jEj8OwBxUmb/feid5vEZT5nX48=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fWbh2KxRXAax7LG2huPHfuYkB73t4ID6ah+GMAqhJNmqIq8n/lXpsO5A/hFvOLOg5Cm7h2umld3lc3rhkhaaK588p/VncFpyCxy1/wdcokM3yh/NW6+Dk06FFOYclxUmMH9VfJyVSfQLM74+kUaxciQCa+AyF7CdoGjrx4hbOiA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=SUrseKtc; arc=none smtp.client-ip=209.85.214.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="SUrseKtc" Received: by mail-pl1-f173.google.com with SMTP id d9443c01a7336-1def89f0cfdso22422005ad.0 for ; Fri, 29 Mar 2024 02:28:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704492; x=1712309292; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=D8h7cMSHewFGFYlfFfESe4dUXe0bnXjUVrh6WZkusMc=; b=SUrseKtcyxJkwmPkTHXU9ft56oU+M+9AhtAp7zTnmNFWpQE2BCJSRZ+QCXBvgfyDWn XGBWTkddGAxAzQCUq70hQOLNtivzxIYK2Htz9XWaCJuHyrU6uYcQwsolDBqQTuvF5iwY fcWxdyYrQwdNXZ5kn1PDtVvetp8zGZe7tzb2XouA3wOfkMz7E7GIGASx01NFCo9EoUjk c8VmLJ7VSdEvEsrtnh5dTH3RaMf99WQWVpP3IXn1p4jhejc+5eTincMD8dd5T1VMTGeo WnT8+ctptmMCyKVeUCccI94s6t978E7CHsuI/9678lTUpia4RCVs01zN27Aw/k/aoOQc dS1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704492; x=1712309292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D8h7cMSHewFGFYlfFfESe4dUXe0bnXjUVrh6WZkusMc=; b=hUB8kpmLyFUltK0Q/AKei4jrASHz/LcqxeYGsgEoKUMVNTjSI+gfJ/EPygq5U0aDor BT/2piCKmnhJf7lCFEdEndxtohGpbS+yuuELCAt8SrQRRCrOiOIBsnd+7mgscXtpKkLJ s2PDEY1vSkCqGClK3OV7BG77+yfG3/jqHR8No+5sk+lThQfpMXHJIls+k785/uQdZltv LqSe36PvwBS1ugAELHDi3N90rU4CAFpM6sfFc9JYK66hzz/Y4BBVjVpPyUPNvOS9y7b6 1LdGuzkiit4jkVTY5PgFrlfgw/xhkRUor8mAaYiEJlRopFBHVWRBO9x0LkXR1X1QC9sh Tktw== X-Forwarded-Encrypted: i=1; AJvYcCV1j+j6/BGBDAEod7vTX+WFxsaqMuSZFuRplGRUEmXc4kd6hcitOcaQ9lHD/lbMtom1O5QeyoH43/Z3eRXaMeY+VCv9 X-Gm-Message-State: AOJu0YyJrB2BOPq5B44S9nkjv2iGWFYinsx/tc6rVaufjvvAfaGnhiFy PIs2WY+N/Fb67Nooy5mDdvjQBtFGMlYv3SfLBfL2DzxRtEjBudS1TvxOVyJdShY= X-Google-Smtp-Source: AGHT+IHUaxFv/dBvqwWUSlGt4S9YT575kSY8SadSYy/sbeUKbzKaMImn5kh/n16Q0rGOAx3nqMZItA== X-Received: by 2002:a17:90a:e386:b0:29b:46f0:6f8e with SMTP id b6-20020a17090ae38600b0029b46f06f8emr2770618pjz.8.1711704492529; Fri, 29 Mar 2024 02:28:12 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:12 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:25 +0800 Subject: [PATCH RFC 09/11] riscv: KVM: Add scontext to ONE_REG Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-9-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu , Yong-Xuan Wang X-Mailer: b4 0.13.0 From: Yong-Xuan Wang Updte the ONE_REG interface to allow the scontext CSR can be accessed from user space. Signed-off-by: Yong-Xuan Wang Co-developed-by: Max Hsu Signed-off-by: Max Hsu --- arch/riscv/include/uapi/asm/kvm.h | 8 +++++ arch/riscv/kvm/vcpu_onereg.c | 62 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 9f70da85ed51..1886722127d7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -98,6 +98,11 @@ struct kvm_riscv_smstateen_csr { unsigned long sstateen0; }; +/* Sdtrig CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_sdtrig_csr { + unsigned long scontext; +}; + /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_timer { __u64 frequency; @@ -224,12 +229,15 @@ struct kvm_riscv_sbi_sta { #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_CSR_SDTRIG (0x3 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_AIA_REG(name) \ (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_CSR_SDTRIG_REG(name) \ + (offsetof(struct kvm_riscv_sdtrig_csr, name) / sizeof(unsigned long)) /* Timer registers are mapped as type 4 */ #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 10dda5ddc0a6..2796a86ec70b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -471,6 +471,34 @@ static int kvm_riscv_vcpu_smstateen_get_csr(struct kvm_vcpu *vcpu, return 0; } +static inline int kvm_riscv_vcpu_sdtrig_set_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long reg_val) +{ + struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr; + + if (reg_num >= sizeof(struct kvm_riscv_sdtrig_csr) / + sizeof(unsigned long)) + return -EINVAL; + + ((unsigned long *)csr)[reg_num] = reg_val; + return 0; +} + +static int kvm_riscv_vcpu_sdtrig_get_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long *out_val) +{ + struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr; + + if (reg_num >= sizeof(struct kvm_riscv_sdtrig_csr) / + sizeof(unsigned long)) + return -EINVAL; + + *out_val = ((unsigned long *)csr)[reg_num]; + return 0; +} + static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -500,6 +528,11 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, rc = kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, ®_val); break; + case KVM_REG_RISCV_CSR_SDTRIG: + rc = -EINVAL; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SDTRIG)) + rc = kvm_riscv_vcpu_sdtrig_get_csr(vcpu, reg_num, ®_val); + break; default: rc = -ENOENT; break; @@ -545,6 +578,11 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu, rc = kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, reg_val); break; + case KVM_REG_RISCV_CSR_SDTRIG: + rc = -EINVAL; + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SDTRIG)) + rc = kvm_riscv_vcpu_sdtrig_set_csr(vcpu, reg_num, reg_val); + break; default: rc = -ENOENT; break; @@ -803,6 +841,8 @@ static inline unsigned long num_csr_regs(const struct kvm_vcpu *vcpu) n += sizeof(struct kvm_riscv_aia_csr) / sizeof(unsigned long); if (riscv_isa_extension_available(vcpu->arch.isa, SMSTATEEN)) n += sizeof(struct kvm_riscv_smstateen_csr) / sizeof(unsigned long); + if (riscv_isa_extension_available(vcpu->arch.isa, SDTRIG)) + n += sizeof(struct kvm_riscv_sdtrig_csr) / sizeof(unsigned long); return n; } @@ -811,7 +851,7 @@ static int copy_csr_reg_indices(const struct kvm_vcpu *vcpu, u64 __user *uindices) { int n1 = sizeof(struct kvm_riscv_csr) / sizeof(unsigned long); - int n2 = 0, n3 = 0; + int n2 = 0, n3 = 0, n4 = 0; /* copy general csr regs */ for (int i = 0; i < n1; i++) { @@ -863,7 +903,25 @@ static int copy_csr_reg_indices(const struct kvm_vcpu *vcpu, } } - return n1 + n2 + n3; + /* copy Sdtrig csr regs */ + if (riscv_isa_extension_available(vcpu->arch.isa, SDTRIG)) { + n4 = sizeof(struct kvm_riscv_sdtrig_csr) / sizeof(unsigned long); + + for (int i = 0; i < n4; i++) { + u64 size = IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; + u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | + KVM_REG_RISCV_CSR_SDTRIG | i; + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + } + } + + return n1 + n2 + n3 + n4; } static inline unsigned long num_timer_regs(void) From patchwork Fri Mar 29 09:26:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610467 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5BF97E575 for ; Fri, 29 Mar 2024 09:28:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704498; cv=none; b=DH2kJ1uc6/z7oZqYC086W1dK3dfIn/6zigcZVDic87FgotiTUzgq+FANP9q3pnhWoUbeSCVoSE45i3R6kKBJFxID03QRhb/c4Al0Ugqk3tKEJnwbtNaXqgcK5f38z9ejuTsZhpABlMlt5a+t2CYEoYFtSyyxPAeRU+BfyS7ZZkM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704498; c=relaxed/simple; bh=bQlDZHUxe+DlLwpEaFAb1U/lWAzGpXz5Uk4pAXpoJP0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BHIQFXnjaoFEcwzenaSnxMBGDfJUyghpYWEM0qFxMQu44360Ta/VV6JVFWoM8ixrNRTaQV+egHJmNKlolv3Fqyn9O3YgCWULcL1hlVqYpabWlSZ3T5IlpWuxRLyEfhx0X0PjWIY58xypc2ZWOloeQBSFgWwidMNCCALP2ldF8fU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=FYXbOwAT; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="FYXbOwAT" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-1def2a1aafaso13691775ad.3 for ; Fri, 29 Mar 2024 02:28:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704496; x=1712309296; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/lyzq0wGOrToQ2iQEyeXKMeMPovCKQNw+2NCntCzWKQ=; b=FYXbOwATeZgdTGKgPxwSFYqJVy/+FaR3oLsB/zmkjxmTcYUjC8TUp5GVi3DQaw94xt 4qQ/nVjczIXj7dBM27oOGl7QQSy1bY6pP3AaqWUjC/GVTpS209Dwpe04XMhKwVRbv6eN FGwvpjQyjm8F1uepTaUHgnY8ru5Mc6mK3L31cUlAPCTSVd390oawVFcRMuyc5KLZEpnA JqRb0Wc+JKsr9/qbjWojGxGNGW9PmTpDSX9DhtsM3NLCGMEIhxJMGNw+T2AID/v5RtKZ 5NaY4NlUI2/mgrRZowVb23fE/mx+toxgl+PaGYQNgL2YpOCfaKIAJXI2IUNAcf42MmJw ASjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704496; x=1712309296; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/lyzq0wGOrToQ2iQEyeXKMeMPovCKQNw+2NCntCzWKQ=; b=dzCpeyK53M8E1JHeS8DZq+Lw+vpur7DzQg1AEHjvsksAGPdofCGhYTejpXIqHS5ep1 RmP27nq52v1phldR9HVyZN/IJeBgKunUi30WwJzBq8HU94KU8qfPuGB+AQy+WQdnvSZZ YQ4i1RrnTephr43o/m60DuXx9ifVzNtzJeD0s6eOR/YYOf3o6ZnV2VcN9l1gFlf4eySg WLTiJV2x9NL1on3uDBsIBQUOezcosQ3uu+2j0N29x2NNWcD/3vWth4/pEFOijHOhMcI3 c7mDYqIJ4uwzXsxoxdlBsPfiApUMAbDH3QmYRobDlhDaj/OQZ1l/LIsEPVBBZIQrwiL6 V3DQ== X-Forwarded-Encrypted: i=1; AJvYcCV+IRKwOkP0p0HawFcApC0vfJIeucgb3/0F1xF1JXFF9L6ZADFUl54t+9C2Wx6EnOQIIysbctUQJpfRYBkrj+ZXEzm2 X-Gm-Message-State: AOJu0YwjQ4azroUeysZs4aelxj+Y4QMtv82OeKccGCZWRoT933dzoVMJ 4EbVAyf+48128J21jcxNGX2oX+RnuIdvAOgy3Lj0jkFz2hgheWs9Zl9/fGGSp1I= X-Google-Smtp-Source: AGHT+IERD9iL6cC6QBlpwrE+WhviS3lzGnj6I0fmkcIha5EAxHWeUpBSJ6740UpJGEHt1s0r02s0NQ== X-Received: by 2002:a17:90b:1091:b0:2a0:2b14:6d8d with SMTP id gj17-20020a17090b109100b002a02b146d8dmr1780476pjb.1.1711704496150; Fri, 29 Mar 2024 02:28:16 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.28.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:15 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:26 +0800 Subject: [PATCH RFC 10/11] riscv: KVM: Add hcontext support Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-10-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu , Yong-Xuan Wang X-Mailer: b4 0.13.0 From: Yong-Xuan Wang hcontext CSR store the ID of the currently running machine status. When a virtual machine is initialized, it will obtain and utilize the first available ID. It will be updated to VM ID when switch to a virtual machine, and updated to 0 when switch back to host machine. Signed-off-by: Yong-Xuan Wang Co-developed-by: Max Hsu Signed-off-by: Max Hsu --- arch/riscv/include/asm/kvm_host.h | 3 ++ arch/riscv/include/asm/kvm_vcpu_debug.h | 7 +++ arch/riscv/kvm/main.c | 4 ++ arch/riscv/kvm/vcpu_debug.c | 78 +++++++++++++++++++++++++++++++++ arch/riscv/kvm/vm.c | 4 ++ 5 files changed, 96 insertions(+) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm_host.h index d495279d99e1..b5d972783116 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -103,6 +103,9 @@ struct kvm_arch { /* AIA Guest/VM context */ struct kvm_aia aia; + + /* hcontext ID for guest VM */ + unsigned long hcontext; }; struct kvm_cpu_trap { diff --git a/arch/riscv/include/asm/kvm_vcpu_debug.h b/arch/riscv/include/asm/kvm_vcpu_debug.h index 6e7ce6b408a6..0a025fc4e6dd 100644 --- a/arch/riscv/include/asm/kvm_vcpu_debug.h +++ b/arch/riscv/include/asm/kvm_vcpu_debug.h @@ -11,6 +11,13 @@ #include +DECLARE_STATIC_KEY_FALSE(use_hcontext); +extern atomic_long_t hcontext_id_share; + +void kvm_riscv_debug_init(void); +void kvm_riscv_debug_exit(void); +void kvm_riscv_debug_get_hcontext_id(struct kvm *kvm); +void kvm_riscv_debug_return_hcontext_id(struct kvm *kvm); void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu); void kvm_riscv_debug_vcpu_swap_in_host_context(struct kvm_vcpu *vcpu); diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c index 225a435d9c9a..ff28b96ad70b 100644 --- a/arch/riscv/kvm/main.c +++ b/arch/riscv/kvm/main.c @@ -125,6 +125,8 @@ static int __init riscv_kvm_init(void) return rc; } + kvm_riscv_debug_init(); + return 0; } module_init(riscv_kvm_init); @@ -133,6 +135,8 @@ static void __exit riscv_kvm_exit(void) { kvm_riscv_aia_exit(); + kvm_riscv_debug_exit(); + kvm_exit(); } module_exit(riscv_kvm_exit); diff --git a/arch/riscv/kvm/vcpu_debug.c b/arch/riscv/kvm/vcpu_debug.c index e7e9263c2e30..5081c272f01d 100644 --- a/arch/riscv/kvm/vcpu_debug.c +++ b/arch/riscv/kvm/vcpu_debug.c @@ -6,6 +6,84 @@ #include #include +DEFINE_SPINLOCK(hcontext_lock); +unsigned long *hcontext_bitmap; +unsigned long hcontext_bitmap_len; + +static __always_inline bool has_hcontext(void) +{ + return static_branch_likely(&use_hcontext); +} + +void kvm_riscv_debug_init(void) +{ + /* + * As from riscv-debug-spec, Chapter 5.7.9: + * If the H extension is implemented, it’s recommended to + * implement no more than 7 bits on RV32 and 14 on RV64. + * Allocating bit array according to spec size. + */ +#if __riscv_xlen > 32 + unsigned long tmp = atomic_long_read(&hcontext_id_share) & GENMASK(13, 0); +#else + unsigned long tmp = atomic_long_read(&hcontext_id_share) & GENMASK(6, 0); +#endif + if (has_hcontext()) { + while (tmp) { + kvm_info("hcontext: try to allocate 0x%lx-bit array\n", tmp); + hcontext_bitmap_len = tmp + 1; + hcontext_bitmap = bitmap_zalloc(tmp, 0); + if (hcontext_bitmap) + break; + tmp = tmp >> 1; + } + + if (tmp == 0) { + /* We can't allocate any space for hcontext bitmap */ + static_branch_disable(&use_hcontext); + } else { + /* ID 0 is hypervisor */ + set_bit(0, hcontext_bitmap); + } + } +} + +void kvm_riscv_debug_exit(void) +{ + if (has_hcontext()) { + static_branch_disable(&use_hcontext); + kfree(hcontext_bitmap); + } +} + +void kvm_riscv_debug_get_hcontext_id(struct kvm *kvm) +{ + if (has_hcontext()) { + unsigned long free_id; + + spin_lock(&hcontext_lock); + free_id = find_first_zero_bit(hcontext_bitmap, hcontext_bitmap_len); + + /* share the maximum ID when we run out of the hcontext ID */ + if (free_id <= hcontext_bitmap_len) + set_bit(free_id, hcontext_bitmap); + else + free_id -= 1; + + kvm->arch.hcontext = free_id; + spin_unlock(&hcontext_lock); + } +} + +void kvm_riscv_debug_return_hcontext_id(struct kvm *kvm) +{ + if (has_hcontext()) { + spin_lock(&hcontext_lock); + clear_bit(kvm->arch.hcontext, hcontext_bitmap); + spin_unlock(&hcontext_lock); + } +} + void kvm_riscv_debug_vcpu_swap_in_guest_context(struct kvm_vcpu *vcpu) { struct kvm_vcpu_sdtrig_csr *csr = &vcpu->arch.sdtrig_csr; diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index ce58bc48e5b8..275f5f05d4dd 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -45,6 +45,8 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) kvm_riscv_guest_timer_init(kvm); + kvm_riscv_debug_get_hcontext_id(kvm); + return 0; } @@ -53,6 +55,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm_destroy_vcpus(kvm); kvm_riscv_aia_destroy_vm(kvm); + + kvm_riscv_debug_return_hcontext_id(kvm); } int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irql, From patchwork Fri Mar 29 09:26:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Hsu X-Patchwork-Id: 13610468 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C770B81752 for ; Fri, 29 Mar 2024 09:28:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704502; cv=none; b=m/aJvwUQS/3Z7cYUmGyezyY8RsF2hCPpZddp7pvYJZmJoOrkd+X5r4rrl7UxBneK6jAHynX5I82U2m73XhjkWw4OhOqwku3A88E3WiTWNSWC/ClH7FS6gWct0dYFzdAh3IIHke0vCWYi6deRgSfu4RaLIX28R2cQo/YVDRqV+bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711704502; c=relaxed/simple; bh=wCFKSKMKTlZBWK3ZXaR4BvVSeSCHMmEnNsjJo8lvTyY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=da7rh150cxPwS73LUuwo13/Scye4bvllkT/5PdEyrEzlm5weIpq81kgR9h59bjl2v59s9vG1P07ylKJHhq3IaT2Qx3rDbHm4YLOIY+2JCHvl+w9hP/Rv95yz6rt48txtQT8BTcC8QnxO7xXKWFy1OXcK7r8ME3iHpT36nL2r95c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com; spf=pass smtp.mailfrom=sifive.com; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b=Z8YTS1mX; arc=none smtp.client-ip=209.85.215.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=sifive.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sifive.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sifive.com header.i=@sifive.com header.b="Z8YTS1mX" Received: by mail-pg1-f176.google.com with SMTP id 41be03b00d2f7-5d42e7ab8a9so1070077a12.3 for ; Fri, 29 Mar 2024 02:28:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1711704500; x=1712309300; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PDqUNVfVcL5Rx2dx6lOA54ZEoR9Eohs4e4oftX2EMwM=; b=Z8YTS1mXlorb4QJ+VKgpjh1j737YZEyXRBcxuYkfsv+qaXxJpKTIyvzJfVZ667X5sb Dfv68oz+XWbhqUqPo2xOON/WfvfwXXlyIS6A8bsPD2l3f1ws6/S/JyCTY+Dwl3QMI9L3 4X2tfogzJb1Mmw3qWnYQnQBZ3ByTp9K7RHH1HRiqS+0aC5Rkc8HMNtrPox+Uev0HV3be YRag0tagInmGSKgX9Qx+GzmdRBssG2sUn0ce5X1We9K9j9tHrxcX+bRXY8tf87XaVqgM RgPiBH5JHeb/y+cr9IprPEjqF5PIQ2KNg29Qen7oEiKgdDaU69oLlmxoFIPr4fkC7Hj+ YtCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711704500; x=1712309300; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PDqUNVfVcL5Rx2dx6lOA54ZEoR9Eohs4e4oftX2EMwM=; b=K3+UWqhLcRxDcFYvn3ehPGyus3W34CDe/Jx5blvkz0Y1WX3mlokTEjPvGA1zFo6EyE 7D9+0iMNEJCseQLdzMg7/3daUvn0X/COS1hadZnTeMeB1uqydMdwJHF5tMOMbio6R9wB LAwbhIAYNMAvvQmDl9ubxMTHomn1eg5mS3uABJPjH4Kv6FyoVin0k987FH5W2VhIzsAR tEUg+fVEwDYcLY/QQfx35MRdBxwZbGRltxXSz7XshN09CA+DYYQhXKB2yXc5xK50d6GA wfdPQqMR7wgp5aUVj3nuixECqS4LyO1StWQPSIjAYyQFteX536aaN8mZkTd3J4RP3bD0 zL8w== X-Forwarded-Encrypted: i=1; AJvYcCXHd4ZS2uCUmZjgnMztjrgfi+5M0RqGamQ7bRBWz6J38qoWz02BT2APnejfsxw39ur0RK2VoRI5iNCnGPSNcm+6b2CD X-Gm-Message-State: AOJu0Yw/A2Mr/j2AxU6oCsuWaQtNXKYctJNmZl1SNmQHfsXOA2bJJlVV ych/t5YJriZxxoOxBGHVTzr5F3rIE12m3+Y9XR4GPWtlbSZ0krFQHJG6RjS0Zqc= X-Google-Smtp-Source: AGHT+IEFn6lnpp94KNj8bwQ5NgWC2ILdPrLL6jG7Xd8BF08mkXal/x6HNlt14p0P0bkYq09hEnt/mA== X-Received: by 2002:a17:90a:ea06:b0:2a0:310b:2cac with SMTP id w6-20020a17090aea0600b002a0310b2cacmr1663501pjy.25.1711704499969; Fri, 29 Mar 2024 02:28:19 -0700 (PDT) Received: from [127.0.1.1] (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.28.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:28:19 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:27 +0800 Subject: [PATCH RFC 11/11] KVM: riscv: selftests: Add Sdtrig Extension to get-reg-list test Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-11-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu , Yong-Xuan Wang X-Mailer: b4 0.13.0 From: Yong-Xuan Wang Update the get-reg-list test to test the Sdtrig Extension is available for guest OS. Signed-off-by: Yong-Xuan Wang Co-developed-by: Max Hsu Signed-off-by: Max Hsu --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..f2696e308509 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -41,6 +41,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SDTRIG: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC: @@ -247,6 +248,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_SMSTATEEN(csr) \ "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SDTRIG(csr) \ + "KVM_REG_RISCV_CSR_SDTRIG | KVM_REG_RISCV_CSR_REG(" #csr ")" static const char *general_csr_id_to_str(__u64 reg_off) { @@ -314,6 +317,18 @@ static const char *smstateen_csr_id_to_str(__u64 reg_off) return NULL; } +static const char *sdtrig_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_SDTRIG_REG(scontext): + return RISCV_CSR_SDTRIG(scontext); + } + + TEST_FAIL("Unknown sdtrig csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -330,6 +345,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id) return aia_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_SMSTATEEN: return smstateen_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_SDTRIG: + return sdtrig_csr_id_to_str(reg_off); } return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); @@ -406,6 +423,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SDTRIG), KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), @@ -764,6 +782,11 @@ static __u64 smstateen_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN, }; +static __u64 sdtrig_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SDTRIG | KVM_REG_RISCV_CSR_SDTRIG_REG(scontext), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SDTRIG, +}; + static __u64 fp_f_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), @@ -853,6 +876,8 @@ static __u64 fp_d_regs[] = { {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),} #define SUBLIST_AIA \ {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} +#define SUBLIST_SDTRIG \ + {"sdtrig", .feature = KVM_RISCV_ISA_EXT_SDTRIG, .regs = sdtrig_regs, .regs_n = ARRAY_SIZE(sdtrig_regs),} #define SUBLIST_SMSTATEEN \ {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),} #define SUBLIST_FP_F \ @@ -930,6 +955,7 @@ KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA); KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F); KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D); KVM_ISA_EXT_SIMPLE_CONFIG(h, H); +KVM_ISA_EXT_SUBLIST_CONFIG(sdtrig, SDTRIG); KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN); KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC); KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); @@ -985,6 +1011,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_fp_f, &config_fp_d, &config_h, + &config_sdtrig, &config_smstateen, &config_sstc, &config_svinval,