From patchwork Fri Mar 29 09:51:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aleksandr Aprelkov X-Patchwork-Id: 13610503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CCF6C6FD1F for ; Fri, 29 Mar 2024 09:52:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=g/Q5nJqiYp7wxO5m3SVNHz+lITVWm7AQfzmC+16QHdU=; b=bzmpdTHgIZ42Zd 46lwuJejv1v+R2BtZee9XaJYeru68dQyZf65ARXrSAffEX/2HLQwLkADw5/Bs8DFvkIV3n+N0zmL+ 0VGAooRsD6O1+OjSq+TCXKm6Q2IVXe2RtpTsUK4lC7yI9uFNH4JNCqN7bBIXp97CZ4mG6iA2gzrEB yKjnRDITHf5Mkw2WkD/UPLxPs9vqJIdE/QMJh27VmdbhyPsk2BmzcCLoUPhy2snLnXz7BF632TWy+ 3A9isAoLsM9/jpSzfcBMzsnF6Ux4pDYSchsqbp9wXRUjCMcGoXVCeX3Edqf2KBCB0l5h8QdI/R7ZU 7rYgARTKSqMU7a7onrHg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8uQ-0000000HYxi-2fI3; Fri, 29 Mar 2024 09:52:26 +0000 Received: from mx2.usergate.com ([46.229.79.1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rq8uN-0000000HYt7-2NM8 for linux-arm-kernel@lists.infradead.org; Fri, 29 Mar 2024 09:52:25 +0000 Received: from mail.usergate.com[192.168.90.36] by mx2.usergate.com with ESMTP id BC4409493A1E471D95606304D683D4D4; Fri, 29 Mar 2024 16:51:58 +0700 From: Aleksandr Aprelkov To: Will Deacon CC: Aleksandr Aprelkov ,Robin Murphy ,Joerg Roedel ,Jason Gunthorpe ,Nicolin Chen ,Michael Shavit ,Lu Baolu ,Marc Zyngier ,,, Subject: [PATCH] iommu/arm-smmu-v3: Free MSIs in case of ENOMEM Date: Fri, 29 Mar 2024 16:51:33 +0700 Message-ID: <20240329095133.576605-1-aaprelkov@usergate.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [192.168.54.39] X-ClientProxiedBy: ESLSRV-EXCH-01.esafeline.com (192.168.90.36) To nsk02-mbx01.esafeline.com (10.10.1.35) X-Message-Id: E2443D9AE363436E83C57DC670C39DEC X-MailFileId: BB9C20720B464D518296C717F3B14E88 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_025224_052029_5B8BF2C9 X-CRM114-Status: UNSURE ( 8.82 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org If devm_add_action() returns ENOMEM, then MSIs allocated but not freed on teardown. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 166bdbd23161 ("iommu/arm-smmu: Add support for MSI on SMMUv3") Signed-off-by: Aleksandr Aprelkov --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 41f93c3ab160..136d0cdce6a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3402,7 +3402,12 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); /* Add callback to free MSIs on teardown */ - devm_add_action(dev, arm_smmu_free_msis, dev); + ret = devm_add_action(dev, arm_smmu_free_msis, dev); + if (ret) { + dev_warn(dev, "failed to add free MSIs callback - falling back to wired irqs\n"); + arm_smmu_free_msis(dev); + return; + } } static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu)