From patchwork Sat Mar 30 13:34:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilles Talis X-Patchwork-Id: 13611571 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02BAE14A96 for ; Sat, 30 Mar 2024 13:34:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805665; cv=none; b=k90DfTVi5RTWjtOm6/LiQYp08DaaAn2ZV3km4iwojzMSZ1tg/5SgX0jwUyOvC+dxx4Z0H7cgUFmh1E29s/lTU+vuMcitzzHcaAK75T8RhJprk40xsmZktrQegPXW50SzXoGkRf0D9ey/0W9Wj4zC4ocu1u41fi3eWKHydB2J47Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805665; c=relaxed/simple; bh=LGw6kak4lZFihhndUY61EFLYz8x56qhQ5QE0nUpuhjo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=hMaCjNNXH8XMFcf1JvwX560bvGLLuccyjZrYYFKsT6ypTvdP/aPE7tsw7brl9lwwnm3H8MAa48U7X/ygPhgMIruBx+YdT/B53mUNQBH6Bd/hdVhOnlf/gvWiVQpf5I/577vBA7tLrp2HleFuLhwCMjGU0iEV74MLtfC4zPhN+yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=aupcDnp9; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="aupcDnp9" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-33ed4dd8659so2382612f8f.0 for ; Sat, 30 Mar 2024 06:34:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711805662; x=1712410462; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hwVvoPowNn0OI3aCiowgffdI708sY5tNSiLWt+MX6xI=; b=aupcDnp9kfpwuJGJ04riaWO02aOuJH55ofguz2oz6l7IESEUVzFeLD3StCwIo9lIWS sXT2Hwmw5SRIlJW0jjEn70zjTtgMmgiy/ivt7OpVnQEEGkXUPDvYmeUM+6/NCTBB9mRH nsEEK0BT5ZmMq9XpdopAiY90s/dO2DXO3o2TTEu48Ys+UXFoF+cmz2AYGcmvsSlCKwaG ahI+AkA/pByCTYyINymwZSSrewGAEDkHrfbiDnkDs2k6F+LVL+K7nj+76yGbAKjiE3Zc jWguz/SuZi/GnTFc0MFGqvftcX8mgNJJ+cC+8lwheGn1L84GCj+djYSCYvKAczSz30I5 M8Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711805662; x=1712410462; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hwVvoPowNn0OI3aCiowgffdI708sY5tNSiLWt+MX6xI=; b=pNBFPV4hjG6/+ZwmdqraRFy+ou8nD2aGyddGnobNqjp7PsiDTPs128VGka0SgmesAB fugGAwbBoXilVWWSQjHZpU6XFAho3ozTGFeQ7Bk+N/rwHktFfudpOfqUzycmDQj7yC2Q v7TgFGdjp+JwDyFavk/WdES+wPqJWTgnF29uXW18CAzO4syHPFo+BVfERZ9bqZ7qodry gI6wwFkpSZWaYpH+s6fALLt9qB+1KYEZ95TWSUtLsFx7hvRcO3BXVP/6O0zeP3R7DFdz 32AHUiGH/Espb3tLCqHS0WrVdR2GPwUBfGiM3W0UFxKfWsS51LaLv5Tz+OnOeF9sJuMy 16SQ== X-Forwarded-Encrypted: i=1; AJvYcCWvBONoF6PucLYmX6xD3MVIc8/FnNb6rOVhMWWrt6NdhPxwvzGsS5ONl6U/8ebhvITAzFhkgMlQDa1vZU7jKj6NmceK X-Gm-Message-State: AOJu0Yyv3oUkQoONtbCDYBABr05D9pknf2yK1ci5Jkgd6/QWfkoiHats DKJBto+p6xlB+TQ3baDFbZNOM+gz2VpPAJVD607GcptfiwChDQJ628mF0Aj2FdzIlA== X-Google-Smtp-Source: AGHT+IHh9DQvqoy8Dp3di8r3TZhfjeHHkmjziX1hFRPX9T94+4F4w2FRwgmkStv6sOb068nXquIpew== X-Received: by 2002:adf:cc92:0:b0:341:8a0a:a354 with SMTP id p18-20020adfcc92000000b003418a0aa354mr3626691wrj.5.1711805662301; Sat, 30 Mar 2024 06:34:22 -0700 (PDT) Received: from gilles-Precision-3571.lan ([2605:59c8:6662:b310:962a:f8cf:49d0:f63e]) by smtp.gmail.com with ESMTPSA id dw11-20020a0560000dcb00b00341c7129e28sm6454869wrb.91.2024.03.30.06.34.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Mar 2024 06:34:22 -0700 (PDT) From: Gilles Talis To: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, shawnguo@kernel.org, festevam@gmail.com, alex@voxelbotics.com, andrew@lunn.ch, Gilles Talis , Krzysztof Kozlowski Subject: [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add Emcraft Systems Date: Sat, 30 Mar 2024 09:34:08 -0400 Message-Id: <20240330133410.41408-2-gilles.talis@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240330133410.41408-1-gilles.talis@gmail.com> References: <20240330133410.41408-1-gilles.talis@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add an entry for Emcraft Systems (https://www.emcraft.com/) Signed-off-by: Gilles Talis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index b97d298b3eb6..8b978c6f1dfd 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -438,6 +438,8 @@ patternProperties: description: Dongguan EmbedFire Electronic Technology Co., Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. + "^emcraft,.*": + description: Emcraft Systems "^emlid,.*": description: Emlid, Ltd. "^emmicro,.*": From patchwork Sat Mar 30 13:34:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilles Talis X-Patchwork-Id: 13611572 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07C8B22F19 for ; Sat, 30 Mar 2024 13:34:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805668; cv=none; b=V7ggDft7I9fw2nKZ5F0kRh34UuKi/wTQ8J4rZm2p1Q4e5sL/WVcylerdSd4Z46IuC6y5R1BZ/B4mFAagPcgfOvJJv9rykwnuO4CvAu9n6sytl+cn7c1y/w736lrezYHqIuxc9thbwIs2hrc6vHrYQfiDmaIYYL14TTgUpXz7/Z8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805668; c=relaxed/simple; bh=oXYRNgJdWbjdepWwOY/KvRs0KAk3andYOyVJDfzA6rA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RcS05dJXKvFNfdwtoHP+tGBRIr8ClptIAjBD9OOpWMkgiiFKNKL5OS25dC3SqEnbIgof9fdC1xOZN22UsHMJZ67WRsE9eBINdzAeL3jM93hucr/zLWY9kthui2GqFsTOwXSjdkbB7SrJBta2jjuF06QMBfJnW8rgZrEUSlMtF4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Y4y3K9n+; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Y4y3K9n+" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4154d24cc77so10533805e9.3 for ; Sat, 30 Mar 2024 06:34:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711805665; x=1712410465; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rymSuP0sS0VsQ6tf1rW9MJE5OL/RKLdSb3bB5F/aqEw=; b=Y4y3K9n+WdlEYE7IjWYDZD1oZBjba6r2bADl4CwUMEEo6FReIQUaKa9+IH3tO7me6H MoaLHxlUj5imLP5wRUiF0H6N+RwAmnTUoOlUNOz5iy9lUvuU5+Z7QrQ9nC1NOCWXaT3G 450025CyaXfwQYvqQ6tpvpuu9sa712vgh8IRO325eD1m54k7l4Zsm17orZU6RK2gyB/J LgOv+i7cJfgD/Tcs9hrTsy8GYg1Yaw8Jdwou2/Apy9CDJGwrWCgK8orS+JH5umkS5GRR hm1XJGhhxp6QgZROJPiO+Feb84INFGK6Bmfh0xQ5lWlIqQH/Ycqz2eOErOenS7T7wM1O 2MwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711805665; x=1712410465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rymSuP0sS0VsQ6tf1rW9MJE5OL/RKLdSb3bB5F/aqEw=; b=gCtOkjmWio+AQT3/BbOka1N2li+BGV4RDQi4vZVgL1kR1ID8VABuF5wZwhgb2nebWG TdJqRg4VFxJ+njuNrJVp35JYG1CbJRsLUd9u3S5UxV3tDyMF6EbK2oz3tMMSy/LnqhNk 0+A/g+gWdwW6/j7IFtgdAldzyX0aWa37llUvk7RrKXc/TbErfPLiywUSmaByucl0btal TneWQeGdSV2xAQa1DItlFZclrgSzEyeOC0ePPO8eDdq1QorJ6Juv/OyHioWTB7svzLTq nhJPJi8KHAyGglnOvRUzDbuPhx545ggmOdTQm0XOLx75XuC1XmkIWDcmHzymisvFGpfp zAcg== X-Forwarded-Encrypted: i=1; AJvYcCWiMtjhDbPAgoYxulR1uc39MJ7vbT0wy7Ljz1LjbrnYBfbqw8tkbzWPioQ+Xm6LkfMQFrVcpuMAxpme0fMd+yT8PTp3 X-Gm-Message-State: AOJu0YxiHhnnTBSSP+G8uvBDRVbSoosw97XNyGQTA2o31hA1Eocw2fSh 9Sf6mkdLXu2c6FwELhJ1KuVSdu0GtESXcKLRslOR9jopDs+guoZl X-Google-Smtp-Source: AGHT+IH/1wUccWdZ+DMlCtESPEkHwH88ePvv0ej6zdewXAdqnjnXpdf+0VZv9IAKFLfQ1mS9Gz6jgw== X-Received: by 2002:a05:6000:1863:b0:343:3a4b:41ee with SMTP id d3-20020a056000186300b003433a4b41eemr4744206wri.23.1711805665179; Sat, 30 Mar 2024 06:34:25 -0700 (PDT) Received: from gilles-Precision-3571.lan ([2605:59c8:6662:b310:962a:f8cf:49d0:f63e]) by smtp.gmail.com with ESMTPSA id dw11-20020a0560000dcb00b00341c7129e28sm6454869wrb.91.2024.03.30.06.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Mar 2024 06:34:24 -0700 (PDT) From: Gilles Talis To: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, shawnguo@kernel.org, festevam@gmail.com, alex@voxelbotics.com, andrew@lunn.ch, Gilles Talis , Krzysztof Kozlowski Subject: [PATCH v2 2/3] dt-bindings: arm: Add Emcraft Systems i.MX8M Plus NavQ+ Kit Date: Sat, 30 Mar 2024 09:34:09 -0400 Message-Id: <20240330133410.41408-3-gilles.talis@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240330133410.41408-1-gilles.talis@gmail.com> References: <20240330133410.41408-1-gilles.talis@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add DT compatible string for Emcraft NavQ+ kit based on the i.MX8M Plus SoC from NXP Signed-off-by: Gilles Talis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0027201e19f8..cec1b31d0792 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1050,6 +1050,7 @@ properties: - enum: - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC + - emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board From patchwork Sat Mar 30 13:34:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilles Talis X-Patchwork-Id: 13611573 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACDD02554B for ; Sat, 30 Mar 2024 13:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805671; cv=none; b=tt/5ve3eAl2ZwAbQpEuXIBrbjBUYCRl6SC6fR5YB0kwt4BjuTeb/UMeG4ru+nU/lVTf+i2WAmplWyqZYIb8qGBnZLaFgSlyFluOJgEDS03umV6JpoJ6o7e0ipEJFTRiw0yEs4+oB3HPz3Oowrt40HWW5AX246PC4zBRaF1b/71M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711805671; c=relaxed/simple; bh=XQBR7Bl3LJnIivKIN6xP9yQWfNClWwfP90d5WSoxOIY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s082tICqD63ATQI1kYnEIs7dDZMZU2D5gUmlt9IFPyCOZH7KtRBn8cOyuNCxec4vD6SfIj5y1zht+WBUINt38kAb+foct5npI0ck0GaEBqmwhHKpNKWLs8XUZ5zyX5BhxMAZD6CyPF2QqyQGf8dKJ3+gfR3okodSjpaYhc+/AZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=DHu+nWqn; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="DHu+nWqn" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-415482308f8so14594125e9.1 for ; Sat, 30 Mar 2024 06:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1711805668; x=1712410468; darn=lists.linux.dev; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XMevo6WW+3XwKNr2qFifmuK+V52q+KQp33DA4yqc8ZA=; b=DHu+nWqnRH8hSiWKTzAkefHQZpka6/6/X/llUiiHTI0f3l4vXeAPFf+ntXxHnI3IkM fHcWEszFv1dsQW6wcQLQnD5ZE5yxNgyqWr0r1gjU2pff7omTAlaHbJXsIj9EeB0OhGwX VLtG0Y4G9umS7y5cAZGennoLuASYCiBvWJ73Slltr4Ch1Ql28DpSXo/nA+a55Qj0j1KE zR7Xlhj7L3Oi1Gi3fWWHRTRgUoh3u8JAHQOUGeb4bPevNf8i5nrLEIADTwOEmKZUdnu9 /pUqCSgpgJUifykLTZQKOwFq8NesWzl1d+t0SbNkcqPnxFjCqR4zQKLaArwo1sE/pk1W fY3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711805668; x=1712410468; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XMevo6WW+3XwKNr2qFifmuK+V52q+KQp33DA4yqc8ZA=; b=ow9DI6IfLVK3o1I/BN8ruo8wdQZYE7vENUwc8pxeEVmED/KwYX64uU/Vz1tTiAYrz1 POSJatU0Slvwgm9c8EnCg2XMBPzE8XKiZARZZTO4kI0/OzPOKIYI1S0UhVfLdCZdFS3g tzS1ArcTSj7atlaq3lgCKzhnBM9z6fal+dgWfthQK+9gTqnHfIhq+gfWHheKTJHb0MEp 1BJoWVJfUUY5+LcZFYF4AR+3dkfezMdgxyiGx929AQZiP/NGASiTdzyT5ieuAYse/p3e L80BLYP3rg31U2cK5IdTpYGftISe8eCIJ/qxDKXgevcpIjCrq4ernPCebgZo/DIIDc16 bPjQ== X-Forwarded-Encrypted: i=1; AJvYcCVtkqib+diesZjqPEzGIHbqbDCDO7xZEX0/4Yr3KlsLOXqmQUKxP8VEqLP+XJtt/tSYzgBrU6YMTPtNKGkciRRSUkyr X-Gm-Message-State: AOJu0Yw5AAOe0nlWXkC/CP8qPw1x/e3p0IHckd8Uho3tT4XDf1mKasbD iKZU8ykZfLn3JNoLTl11rQx1MhFzt205fah45eFzDOldug05vJXF0yFSXw370eR8Zg== X-Google-Smtp-Source: AGHT+IEAEcm91VbHXKf101o7NWsZaI7EDIIaBR0W5taBaWfShc8iBCId2Z3maZmnFwRm1uRg2QeSOg== X-Received: by 2002:a5d:614e:0:b0:341:abd4:a6e8 with SMTP id y14-20020a5d614e000000b00341abd4a6e8mr3240842wrt.60.1711805667922; Sat, 30 Mar 2024 06:34:27 -0700 (PDT) Received: from gilles-Precision-3571.lan ([2605:59c8:6662:b310:962a:f8cf:49d0:f63e]) by smtp.gmail.com with ESMTPSA id dw11-20020a0560000dcb00b00341c7129e28sm6454869wrb.91.2024.03.30.06.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Mar 2024 06:34:27 -0700 (PDT) From: Gilles Talis To: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: conor+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, robh@kernel.org, shawnguo@kernel.org, festevam@gmail.com, alex@voxelbotics.com, andrew@lunn.ch, Gilles Talis Subject: [PATCH v2 3/3] arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit Date: Sat, 30 Mar 2024 09:34:10 -0400 Message-Id: <20240330133410.41408-4-gilles.talis@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240330133410.41408-1-gilles.talis@gmail.com> References: <20240330133410.41408-1-gilles.talis@gmail.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Emcraft Systems NavQ+ kit is a mobile robotics platform based on NXP i.MX8 MPlus SoC. The following interfaces and devices are enabled: - eMMC - Gigabit Ethernet - RTC - SD-Card - UART console Signed-off-by: Gilles Talis Reviewed-by: Andrew Lunn Reviewed-by: Fabio Estevam --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../arm64/boot/dts/freescale/imx8mp-navqp.dts | 424 ++++++++++++++++++ 2 files changed, 425 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-navqp.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 045250d0a040..bf99864c0bc4 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts new file mode 100644 index 000000000000..5fd1614982cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Emcraft Systems + * Copyright 2024 Gilles Talis + */ + +/dts-v1/; + +#include +#include +#include "imx8mp.dtsi" + +/ { + model = "Emcraft Systems i.MX8MPlus NavQ+ Kit"; + compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <10000>; + qca,disable-smarteee; + qca,disable-hibernation-mode; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + }; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +};