From patchwork Tue Apr 2 10:34:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13613674 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1CEB762EB; Tue, 2 Apr 2024 10:34:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712054077; cv=none; b=glq5/vZQ31iITK6RdAcG61yUpgu3w5nkVg0camwZof5U1WYMLopXleiXsAEqX0DZNV7avCeIvkiXmM4m1l2iJxFSxQg5zzhnfuFj5hrlrQDb3lWZGyz4wYFIPLfrt7VV4RfBipQczfoUa1wiH/pmUntwoPSDQleWp90jSC44jR4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712054077; c=relaxed/simple; bh=9W5yXmNP7RN0YDEaOnAqtXDqESh/DQbRqD3la8UsGLU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iUSSZlB3nAHyyd9TfN1sYmXpZQ4UQ9L+YSTHDEIlaA+HSIm9pIMPNO8OomcTURXqNkpYw+LtzIKNRwDuVhGJhSUMBHsLeLoF5pzIfdK+NK6hJyuGhjzN6bmWxdmgotHlTUP105Kd9iERSZ3F1aAzAMhWEzscTrEeKuLXO0NI6oA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=WotAlpp3; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WotAlpp3" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 432AXkVS012365; Tue, 2 Apr 2024 10:34:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=KKVLEPnJvIznfpi1YM59rxoCg/4dR7PZpPDKjrNgMsY=; b=Wo tAlpp3q+vQbMXf8lmUCDCE7s9t/CNYXvSWTBSasm0lfc5V2xYQEFOdThINdFR9sr 5eSqryjs+q2ExfQ/IYAiRkEVJVtloiauKFfT3mFYdroZSuui+KBA3GP6p2bquln6 luCeLFf1VMi5xGv5rw1WBE4JWDna2hJZ15U55ycsQsD8OQ3t04zr75vWaeIvBMYn OXyIwZlDQUc7tYnXzdkXs1bFCSVOEPG6lMpmC1ugrJv/zehcNFCKb6PpeUYDjGyz 6Riv5cZABPAgHDedF/jAeyJdjrBTJjs/y/N1IpoL2AO5OIVOiKUW+8juizKErE/2 dMJ5N3iRD9NeMey/LL6Q== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x893ts0nf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 02 Apr 2024 10:34:31 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 432AYUba012955 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 Apr 2024 10:34:30 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:25 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v6 1/6] dt-bindings: interconnect: Add Qualcomm IPQ9574 support Date: Tue, 2 Apr 2024 16:04:01 +0530 Message-ID: <20240402103406.3638821-2-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402103406.3638821-1-quic_varada@quicinc.com> References: <20240402103406.3638821-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aOCI7XKsU3cm437dwClUDrTzh0jPn9F8 X-Proofpoint-ORIG-GUID: aOCI7XKsU3cm437dwClUDrTzh0jPn9F8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 adultscore=0 impostorscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 mlxscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ9574 Network-On-Chip interfaces. This will be used by the gcc-ipq9574 driver that will for providing interconnect services using the icc-clk framework. Signed-off-by: Varadarajan Narayanan --- v6: Removed Reviewed-by: Krzysztof Kozlowski Redefine the bindings such that driver and DT can share them v3: Squash Documentation/ and include/ changes into same patch qcom,ipq9574.h Move 'first id' to clock driver --- .../bindings/clock/qcom,ipq9574-gcc.yaml | 3 ++ .../dt-bindings/interconnect/qcom,ipq9574.h | 36 +++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,ipq9574.h diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml index 944a0ea79cd6..824781cbdf34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml @@ -33,6 +33,9 @@ properties: - description: PCIE30 PHY3 pipe clock source - description: USB3 PHY pipe clock source + '#interconnect-cells': + const: 1 + required: - compatible - clocks diff --git a/include/dt-bindings/interconnect/qcom,ipq9574.h b/include/dt-bindings/interconnect/qcom,ipq9574.h new file mode 100644 index 000000000000..988124c39810 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,ipq9574.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef INTERCONNECT_QCOM_IPQ9574_H +#define INTERCONNECT_QCOM_IPQ9574_H + +#define ICC_ANOC_PCIE0 0 +#define ICC_SNOC_PCIE0 1 +#define ICC_ANOC_PCIE1 2 +#define ICC_SNOC_PCIE1 3 +#define ICC_ANOC_PCIE2 4 +#define ICC_SNOC_PCIE2 5 +#define ICC_ANOC_PCIE3 6 +#define ICC_SNOC_PCIE3 7 +#define ICC_SNOC_USB 8 +#define ICC_ANOC_USB_AXI 9 +#define ICC_NSSNOC_NSSCC 10 +#define ICC_NSSNOC_SNOC_0 11 +#define ICC_NSSNOC_SNOC_1 12 +#define ICC_NSSNOC_PCNOC_1 13 +#define ICC_NSSNOC_QOSGEN_REF 14 +#define ICC_NSSNOC_TIMEOUT_REF 15 +#define ICC_NSSNOC_XO_DCD 16 +#define ICC_NSSNOC_ATB 17 +#define ICC_MEM_NOC_NSSNOC 18 +#define ICC_NSSNOC_MEMNOC 19 +#define ICC_NSSNOC_MEM_NOC_1 20 + +#define ICC_NSSNOC_PPE 0 +#define ICC_NSSNOC_PPE_CFG 1 +#define ICC_NSSNOC_NSS_CSR 2 +#define ICC_NSSNOC_IMEM_QSB 3 +#define ICC_NSSNOC_IMEM_AHB 4 + +#define MASTER(x) ((ICC_ ## x) * 2) +#define SLAVE(x) (MASTER(x) + 1) + +#endif /* INTERCONNECT_QCOM_IPQ9574_H */ From patchwork Tue Apr 2 10:34:02 2024 Content-Type: text/plain; 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Tue, 2 Apr 2024 10:34:35 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:30 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , CC: kernel test robot Subject: [PATCH v6 2/6] interconnect: icc-clk: Remove tristate from INTERCONNECT_CLK Date: Tue, 2 Apr 2024 16:04:02 +0530 Message-ID: <20240402103406.3638821-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402103406.3638821-1-quic_varada@quicinc.com> References: <20240402103406.3638821-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RHLt1x75LZT-uKFCCcmhCB_22Gpz9Ymu X-Proofpoint-GUID: RHLt1x75LZT-uKFCCcmhCB_22Gpz9Ymu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 clxscore=1011 priorityscore=1501 mlxlogscore=849 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxscore=0 adultscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 drivers/clk/qcom/common.c uses devm_icc_clk_register under IS_ENABLED(CONFIG_INTERCONNECT_CLK). However, in kernel bot random config build test, with the following combination CONFIG_COMMON_CLK_QCOM=y and CONFIG_INTERCONNECT_CLK=m the following error is seen as devm_icc_clk_register is in a module and being referenced from vmlinux. powerpc64-linux-ld: drivers/clk/qcom/common.o: in function `qcom_cc_really_probe': >> common.c:(.text+0x980): undefined reference to `devm_icc_clk_register' Hence, ensure INTERCONNECT_CLK is not selected as a module. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202404012258.MFriF5BV-lkp@intel.com/ Fixes: 0ac2a08f42ce ("interconnect: add clk-based icc provider support") Signed-off-by: Varadarajan Narayanan --- drivers/interconnect/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index 5faa8d2aecff..f44be5469382 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -16,7 +16,6 @@ source "drivers/interconnect/qcom/Kconfig" source "drivers/interconnect/samsung/Kconfig" config INTERCONNECT_CLK - tristate depends on COMMON_CLK help Support for wrapping clocks into the interconnect nodes. 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Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- v5: Introduced devm_icc_clk_register --- drivers/interconnect/icc-clk.c | 29 +++++++++++++++++++++++++++++ include/linux/interconnect-clk.h | 4 ++++ 2 files changed, 33 insertions(+) diff --git a/drivers/interconnect/icc-clk.c b/drivers/interconnect/icc-clk.c index d787f2ea36d9..89f11fed8820 100644 --- a/drivers/interconnect/icc-clk.c +++ b/drivers/interconnect/icc-clk.c @@ -148,6 +148,35 @@ struct icc_provider *icc_clk_register(struct device *dev, } EXPORT_SYMBOL_GPL(icc_clk_register); +static void devm_icc_release(struct device *dev, void *res) +{ + icc_clk_unregister(res); +} + +struct icc_provider *devm_icc_clk_register(struct device *dev, + unsigned int first_id, + unsigned int num_clocks, + const struct icc_clk_data *data) +{ + struct icc_provider *prov, **provp; + + provp = devres_alloc(devm_icc_release, sizeof(*provp), GFP_KERNEL); + if (!provp) + return ERR_PTR(-ENOMEM); + + prov = icc_clk_register(dev, first_id, num_clocks, data); + + if (!IS_ERR(prov)) { + *provp = prov; + devres_add(dev, provp); + } else { + devres_free(provp); + } + + return prov; +} +EXPORT_SYMBOL_GPL(devm_icc_clk_register); + /** * icc_clk_unregister() - unregister a previously registered clk interconnect provider * @provider: provider returned by icc_clk_register() diff --git a/include/linux/interconnect-clk.h b/include/linux/interconnect-clk.h index 0cd80112bea5..cb7b648eb1c0 100644 --- a/include/linux/interconnect-clk.h +++ b/include/linux/interconnect-clk.h @@ -17,6 +17,10 @@ struct icc_provider *icc_clk_register(struct device *dev, unsigned int first_id, unsigned int num_clocks, const struct icc_clk_data *data); +struct icc_provider *devm_icc_clk_register(struct device *dev, + unsigned int first_id, + unsigned int num_clocks, + const struct icc_clk_data *data); void icc_clk_unregister(struct icc_provider *provider); #endif From patchwork Tue Apr 2 10:34:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13613677 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A61E7FBA1; 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Tue, 02 Apr 2024 10:34:46 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 432AYjpQ007033 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 Apr 2024 10:34:45 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:40 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v6 4/6] clk: qcom: common: Add interconnect clocks support Date: Tue, 2 Apr 2024 16:04:04 +0530 Message-ID: <20240402103406.3638821-5-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402103406.3638821-1-quic_varada@quicinc.com> References: <20240402103406.3638821-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JcOquWBiVx2CAFUcOSKWVJgwR48mtRka X-Proofpoint-ORIG-GUID: JcOquWBiVx2CAFUcOSKWVJgwR48mtRka X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 mlxscore=0 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=947 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 Unlike MSM platforms that manage NoC related clocks and scaling from RPM, IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. However, there is a requirement to enable some NoC interface clocks for accessing the peripheral controllers present on these NoCs. Though exposing these as normal clocks would work, having a minimalistic interconnect driver to handle these clocks would make it consistent with other Qualcomm platforms resulting in common code paths. This is similar to msm8996-cbf's usage of icc-clk framework. Signed-off-by: Varadarajan Narayanan --- v6: first_id -> icc_first_node_id Remove clock get so that the peripheral that uses the clock can do the clock get v5: Split changes in common.c to separate patch Fix error handling Use devm_icc_clk_register instead of icc_clk_register v4: Use clk_hw instead of indices Do icc register in qcom_cc_probe() call stream Add icc clock info to qcom_cc_desc structure v3: Use indexed identifiers here to avoid confusion Fix error messages and move to common.c v2: Move DTS to separate patch Update commit log Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error --- drivers/clk/qcom/common.c | 38 +++++++++++++++++++++++++++++++++++++- drivers/clk/qcom/common.h | 3 +++ 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 75f09e6e057e..d5c008048994 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -234,6 +235,41 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static int qcom_cc_icc_register(struct device *dev, + const struct qcom_cc_desc *desc) +{ + struct icc_clk_data *icd; + int i; + + if (!IS_ENABLED(CONFIG_INTERCONNECT_CLK)) + return 0; + + if (!desc->icc_hws) + return 0; + + icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL); + if (!icd) + return -ENOMEM; + + for (i = 0; i < desc->num_icc_hws; i++) { + /* + * get_clk will be done by the peripheral device using this + * clock with devm_clk_hw_get_clk() so that we can associate + * the clk handle with the consumer device. It would also help + * us make it so that drivers defer probe until their + * clk isn't an orphan. + */ + icd[i].clk = desc->icc_hws[i]->clk; + if (!icd[i].clk) + return dev_err_probe(dev, -ENOENT, + "(%d) clock entry is null\n", i); + icd[i].name = clk_hw_get_name(desc->icc_hws[i]); + } + + return PTR_ERR_OR_ZERO(devm_icc_clk_register(dev, desc->icc_first_node_id, + desc->num_icc_hws, icd)); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -303,7 +339,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (ret) return ret; - return 0; + return qcom_cc_icc_register(dev, desc); } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h index 9c8f7b798d9f..9058ffd46260 100644 --- a/drivers/clk/qcom/common.h +++ b/drivers/clk/qcom/common.h @@ -29,6 +29,9 @@ struct qcom_cc_desc { size_t num_gdscs; struct clk_hw **clk_hws; size_t num_clk_hws; + struct clk_hw **icc_hws; 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Tue, 2 Apr 2024 10:34:50 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:45 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v6 5/6] clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks Date: Tue, 2 Apr 2024 16:04:05 +0530 Message-ID: <20240402103406.3638821-6-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402103406.3638821-1-quic_varada@quicinc.com> References: <20240402103406.3638821-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WygmSi_lxJPle8N-r6YJSQMKC04K6D6d X-Proofpoint-ORIG-GUID: WygmSi_lxJPle8N-r6YJSQMKC04K6D6d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Signed-off-by: Varadarajan Narayanan --- v6: Move enum to dt-bindings and share between here and DT first_id -> icc_first_node_id v5: Split from common.c changes into separate patch No functional changes --- drivers/clk/qcom/Kconfig | 2 ++ drivers/clk/qcom/gcc-ipq9574.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 8ab08e7b5b6c..af73a0b396eb 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -243,6 +243,8 @@ config IPQ_GCC_8074 config IPQ_GCC_9574 tristate "IPQ9574 Global Clock Controller" + select INTERCONNECT + select INTERCONNECT_CLK help Support for global clock controller on ipq9574 devices. Say Y if you want to use peripheral devices such as UART, SPI, diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c index 0a3f846695b8..646cafcf8f0b 100644 --- a/drivers/clk/qcom/gcc-ipq9574.c +++ b/drivers/clk/qcom/gcc-ipq9574.c @@ -12,6 +12,7 @@ #include #include +#include #include "clk-alpha-pll.h" #include "clk-branch.h" @@ -4301,6 +4302,32 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, }; +#define IPQ_APPS_ID 9574 /* some unique value */ + +static struct clk_hw *icc_ipq9574_hws[] = { + [ICC_ANOC_PCIE0] = &gcc_anoc_pcie0_1lane_m_clk.clkr.hw, + [ICC_SNOC_PCIE0] = &gcc_anoc_pcie1_1lane_m_clk.clkr.hw, + [ICC_ANOC_PCIE1] = &gcc_anoc_pcie2_2lane_m_clk.clkr.hw, + [ICC_SNOC_PCIE1] = &gcc_anoc_pcie3_2lane_m_clk.clkr.hw, + [ICC_ANOC_PCIE2] = &gcc_snoc_pcie0_1lane_s_clk.clkr.hw, + [ICC_SNOC_PCIE2] = &gcc_snoc_pcie1_1lane_s_clk.clkr.hw, + [ICC_ANOC_PCIE3] = &gcc_snoc_pcie2_2lane_s_clk.clkr.hw, + [ICC_SNOC_PCIE3] = &gcc_snoc_pcie3_2lane_s_clk.clkr.hw, + [ICC_SNOC_USB] = &gcc_snoc_usb_clk.clkr.hw, + [ICC_ANOC_USB_AXI] = &gcc_anoc_usb_axi_clk.clkr.hw, + [ICC_NSSNOC_NSSCC] = &gcc_nssnoc_nsscc_clk.clkr.hw, + [ICC_NSSNOC_SNOC_0] = &gcc_nssnoc_snoc_clk.clkr.hw, + [ICC_NSSNOC_SNOC_1] = &gcc_nssnoc_snoc_1_clk.clkr.hw, + [ICC_NSSNOC_PCNOC_1] = &gcc_nssnoc_pcnoc_1_clk.clkr.hw, + [ICC_NSSNOC_QOSGEN_REF] = &gcc_nssnoc_qosgen_ref_clk.clkr.hw, + [ICC_NSSNOC_TIMEOUT_REF] = &gcc_nssnoc_timeout_ref_clk.clkr.hw, + [ICC_NSSNOC_XO_DCD] = &gcc_nssnoc_xo_dcd_clk.clkr.hw, + [ICC_NSSNOC_ATB] = &gcc_nssnoc_atb_clk.clkr.hw, + [ICC_MEM_NOC_NSSNOC] = &gcc_mem_noc_nssnoc_clk.clkr.hw, + [ICC_NSSNOC_MEMNOC] = &gcc_nssnoc_memnoc_clk.clkr.hw, + [ICC_NSSNOC_MEM_NOC_1] = &gcc_nssnoc_mem_noc_1_clk.clkr.hw, +}; + static const struct of_device_id gcc_ipq9574_match_table[] = { { .compatible = "qcom,ipq9574-gcc" }, { } @@ -4323,6 +4350,9 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = { .num_resets = ARRAY_SIZE(gcc_ipq9574_resets), .clk_hws = gcc_ipq9574_hws, .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws), + .icc_hws = icc_ipq9574_hws, + .num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws), + .icc_first_node_id = IPQ_APPS_ID, }; static int gcc_ipq9574_probe(struct platform_device *pdev) From patchwork Tue Apr 2 10:34:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13613679 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 544DB83CC9; Tue, 2 Apr 2024 10:35:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 02 Apr 2024 10:34:56 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 432AYts1017948 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 Apr 2024 10:34:55 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 2 Apr 2024 03:34:50 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , Subject: [PATCH v6 6/6] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Date: Tue, 2 Apr 2024 16:04:06 +0530 Message-ID: <20240402103406.3638821-7-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240402103406.3638821-1-quic_varada@quicinc.com> References: <20240402103406.3638821-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 6q9RLj5_sOpvdOjVX6d2GS411X_4Fj8I X-Proofpoint-ORIG-GUID: 6q9RLj5_sOpvdOjVX6d2GS411X_4Fj8I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-02_04,2024-04-01_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 impostorscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 suspectscore=0 lowpriorityscore=0 phishscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2404020076 IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..5b3e69379b1f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -306,6 +307,7 @@ gcc: clock-controller@1800000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 {