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[99.107.94.179]) by smtp.googlemail.com with ESMTPSA id h15-20020a05620a13ef00b00789effdd500sm4700834qkl.76.2024.04.02.17.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 17:47:28 -0700 (PDT) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v3 1/4] platform/chrome: cros_ec_lpc: introduce a priv struct for the lpc device Date: Tue, 2 Apr 2024 19:47:10 -0500 Message-ID: <20240403004713.130365-2-dustin@howett.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240403004713.130365-1-dustin@howett.net> References: <20231126192452.97824-1-dustin@howett.net> <20240403004713.130365-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 lpc_driver_data stores the MMIO port base for EC mapped memory. cros_ec_lpc_readmem uses this port base instead of hardcoding EC_LPC_ADDR_MEMMAP. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index f0f3d3d56157..5e2856c5185b 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,14 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/** + * struct cros_ec_lpc - LPC device-specific data + * @mmio_memory_base: The first I/O port addressing EC mapped memory. + */ +struct cros_ec_lpc { + u16 mmio_memory_base; +}; + /** * struct lpc_driver_ops - LPC driver operations * @read: Copy length bytes from EC address offset into buffer dest. Returns @@ -290,6 +298,7 @@ static int cros_ec_cmd_xfer_lpc(struct cros_ec_device *ec, static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, unsigned int bytes, void *dest) { + struct cros_ec_lpc *ec_lpc = ec->priv; int i = offset; char *s = dest; int cnt = 0; @@ -299,13 +308,13 @@ static int cros_ec_lpc_readmem(struct cros_ec_device *ec, unsigned int offset, /* fixed length */ if (bytes) { - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + offset, bytes, s); + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + offset, bytes, s); return bytes; } /* string */ for (; i < EC_MEMMAP_SIZE; i++, s++) { - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + i, 1, s); + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + i, 1, s); cnt++; if (!*s) break; @@ -353,9 +362,16 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) struct acpi_device *adev; acpi_status status; struct cros_ec_device *ec_dev; + struct cros_ec_lpc *ec_lpc; u8 buf[2] = {}; int irq, ret; + ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); + if (!ec_lpc) + return -ENOMEM; + + ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + /* * The Framework Laptop (and possibly other non-ChromeOS devices) * only exposes the eight I/O ports that are required for the Microchip EC. @@ -380,7 +396,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) cros_ec_lpc_ops.write = cros_ec_lpc_mec_write_bytes; cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, buf); if (buf[0] != 'E' || buf[1] != 'C') { - if (!devm_request_region(dev, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE, + if (!devm_request_region(dev, ec_lpc->mmio_memory_base, EC_MEMMAP_SIZE, dev_name(dev))) { dev_err(dev, "couldn't reserve memmap region\n"); return -EBUSY; @@ -389,7 +405,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) /* Re-assign read/write operations for the non MEC variant */ cros_ec_lpc_ops.read = cros_ec_lpc_read_bytes; cros_ec_lpc_ops.write = cros_ec_lpc_write_bytes; - cros_ec_lpc_ops.read(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID, 2, + cros_ec_lpc_ops.read(ec_lpc->mmio_memory_base + EC_MEMMAP_ID, 2, buf); if (buf[0] != 'E' || buf[1] != 'C') { dev_err(dev, "EC ID not detected\n"); @@ -423,6 +439,7 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) ec_dev->din_size = sizeof(struct ec_host_response) + sizeof(struct ec_response_get_protocol_info); ec_dev->dout_size = sizeof(struct ec_host_request); + ec_dev->priv = ec_lpc; /* * Some boards do not have an IRQ allotted for cros_ec_lpc, From patchwork Wed Apr 3 00:47:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dustin L. 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[99.107.94.179]) by smtp.googlemail.com with ESMTPSA id h15-20020a05620a13ef00b00789effdd500sm4700834qkl.76.2024.04.02.17.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 17:47:29 -0700 (PDT) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v3 2/4] platform/chrome: cros_ec_lpc: pass driver_data from DMI to the device Date: Tue, 2 Apr 2024 19:47:11 -0500 Message-ID: <20240403004713.130365-3-dustin@howett.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240403004713.130365-1-dustin@howett.net> References: <20231126192452.97824-1-dustin@howett.net> <20240403004713.130365-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 lpc_driver_data will be stored in drvdata until probe is complete. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 5e2856c5185b..b3aa60e0feb3 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -627,14 +627,16 @@ static int __init cros_ec_lpc_init(void) { int ret; acpi_status status; + const struct dmi_system_id *dmi_match; status = acpi_get_devices(ACPI_DRV_NAME, cros_ec_lpc_parse_device, &cros_ec_lpc_acpi_device_found, NULL); if (ACPI_FAILURE(status)) pr_warn(DRV_NAME ": Looking for %s failed\n", ACPI_DRV_NAME); - if (!cros_ec_lpc_acpi_device_found && - !dmi_check_system(cros_ec_lpc_dmi_table)) { + dmi_match = dmi_first_match(cros_ec_lpc_dmi_table); + + if (!cros_ec_lpc_acpi_device_found && !dmi_match) { pr_err(DRV_NAME ": unsupported system.\n"); return -ENODEV; } @@ -647,6 +649,9 @@ static int __init cros_ec_lpc_init(void) } if (!cros_ec_lpc_acpi_device_found) { + /* Pass the DMI match's driver data down to the platform device */ + platform_set_drvdata(&cros_ec_lpc_device, dmi_match->driver_data); + /* Register the device, and it'll get hooked up automatically */ ret = platform_device_register(&cros_ec_lpc_device); if (ret) { From patchwork Wed Apr 3 00:47:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Dustin L. 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[99.107.94.179]) by smtp.googlemail.com with ESMTPSA id h15-20020a05620a13ef00b00789effdd500sm4700834qkl.76.2024.04.02.17.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 17:47:30 -0700 (PDT) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v3 3/4] platform/chrome: cros_ec_lpc: add a "quirks" system Date: Tue, 2 Apr 2024 19:47:12 -0500 Message-ID: <20240403004713.130365-4-dustin@howett.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240403004713.130365-1-dustin@howett.net> References: <20231126192452.97824-1-dustin@howett.net> <20240403004713.130365-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Some devices ship a ChromeOS EC in a non-standard configuration. Quirks allow cros_ec_lpc to account for these non-standard configurations. It only supports one quirk right now: - CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for MMIO to the EC's memory region Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index b3aa60e0feb3..087131f159d4 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -34,6 +34,24 @@ /* True if ACPI device is present */ static bool cros_ec_lpc_acpi_device_found; +/* + * Indicates that lpc_driver_data.quirk_mmio_memory_base should + * be used as the base port for EC mapped memory. + */ +#define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0) + +/** + * struct lpc_driver_data - driver data attached to a DMI device ID to indicate + * hardware quirks. + * @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_* + * @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used + * when quirk ...REMAP_MEMORY is set.) + */ +struct lpc_driver_data { + u32 quirks; + u16 quirk_mmio_memory_base; +}; + /** * struct cros_ec_lpc - LPC device-specific data * @mmio_memory_base: The first I/O port addressing EC mapped memory. @@ -363,8 +381,10 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) acpi_status status; struct cros_ec_device *ec_dev; struct cros_ec_lpc *ec_lpc; + struct lpc_driver_data *driver_data; u8 buf[2] = {}; int irq, ret; + u32 quirks; ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); if (!ec_lpc) @@ -372,6 +392,17 @@ static int cros_ec_lpc_probe(struct platform_device *pdev) ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; + driver_data = platform_get_drvdata(pdev); + if (driver_data) { + quirks = driver_data->quirks; + + if (quirks) + dev_info(dev, "loaded with quirks %8.08x\n", quirks); + + if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY) + ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base; + } + /* * The Framework Laptop (and possibly other non-ChromeOS devices) * only exposes the eight I/O ports that are required for the Microchip EC. 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[99.107.94.179]) by smtp.googlemail.com with ESMTPSA id h15-20020a05620a13ef00b00789effdd500sm4700834qkl.76.2024.04.02.17.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Apr 2024 17:47:31 -0700 (PDT) From: "Dustin L. Howett" To: Tzung-Bi Shih , Guenter Roeck , chrome-platform@lists.linux.dev Cc: "Dustin L. Howett" Subject: [PATCH v3 4/4] platform/chrome: cros_ec_lpc: add quirks for the Framework Laptop (AMD) Date: Tue, 2 Apr 2024 19:47:13 -0500 Message-ID: <20240403004713.130365-5-dustin@howett.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240403004713.130365-1-dustin@howett.net> References: <20231126192452.97824-1-dustin@howett.net> <20240403004713.130365-1-dustin@howett.net> Precedence: bulk X-Mailing-List: chrome-platform@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The original Framework Laptop 13 platform (Intel 11th, 12th, and 13th Generation at this time) uses a Microchip embedded controller in a standard configuration. The newer devices in this product line--Framework Laptop 13 and 16 (AMD Ryzen)--use a NPCX embedded controller. However, they deviate from the configuration of ChromeOS platforms built with the NPCX EC. * The MMIO region for EC memory begins at port 0xE00 rather than the expected 0x900. cros_ec_lpc's quirks system is used to address this issue. Signed-off-by: Dustin L. Howett --- drivers/platform/chrome/cros_ec_lpc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/platform/chrome/cros_ec_lpc.c b/drivers/platform/chrome/cros_ec_lpc.c index 087131f159d4..beaf714e8568 100644 --- a/drivers/platform/chrome/cros_ec_lpc.c +++ b/drivers/platform/chrome/cros_ec_lpc.c @@ -527,6 +527,11 @@ static const struct acpi_device_id cros_ec_lpc_acpi_device_ids[] = { }; MODULE_DEVICE_TABLE(acpi, cros_ec_lpc_acpi_device_ids); +static const struct lpc_driver_data framework_laptop_amd_lpc_driver_data __initconst = { + .quirks = CROS_EC_LPC_QUIRK_REMAP_MEMORY, + .quirk_mmio_memory_base = 0xE00, +}; + static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { { /* @@ -581,7 +586,16 @@ static const struct dmi_system_id cros_ec_lpc_dmi_table[] __initconst = { }, /* A small number of non-Chromebook/box machines also use the ChromeOS EC */ { - /* the Framework Laptop */ + /* the Framework Laptop 13 (AMD Ryzen) and 16 (AMD Ryzen) */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Framework"), + DMI_MATCH(DMI_PRODUCT_NAME, "AMD Ryzen"), + DMI_MATCH(DMI_PRODUCT_FAMILY, "Laptop"), + }, + .driver_data = (void *)&framework_laptop_amd_lpc_driver_data, + }, + { + /* the Framework Laptop (Intel 11th, 12th, 13th Generation) */ .matches = { DMI_MATCH(DMI_SYS_VENDOR, "Framework"), DMI_MATCH(DMI_PRODUCT_NAME, "Laptop"),