From patchwork Fri Apr 5 08:41:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13618671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 40564CD1296 for ; Fri, 5 Apr 2024 08:41:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F3646113A87; Fri, 5 Apr 2024 08:41:40 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="NBc6TYOe"; dkim-atps=neutral Received: from mail-lf1-f51.google.com (mail-lf1-f51.google.com [209.85.167.51]) by gabe.freedesktop.org (Postfix) with ESMTPS id 736B410F2EF for ; Fri, 5 Apr 2024 08:41:36 +0000 (UTC) Received: by mail-lf1-f51.google.com with SMTP id 2adb3069b0e04-516d536f6f2so341237e87.2 for ; Fri, 05 Apr 2024 01:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712306494; x=1712911294; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=gSABBNNlKEhtSsrOAA7jkzf/IIG0fsXnntsFQ9SmQNk=; b=NBc6TYOeg710Z+I6kCbhWcW+nAlRPJa81kzQU3AiIcRZjbs/AQAH4VXo2pXk8tF9yZ iMtWu8ipR5HB7SWcShtmfWuDrUntT5T2ujaauHVfaaAHbQYWIx2C/wxRw2uMZBeK4dX/ smcNx9dx5rq9Pm7JqTdFa6fPqRSBo9T1sbTccz0BLyOoZnQVbMITXiZIDqjvFVlwGiEk oXBaXZxkph/BiF+CwxCoFxITYkcSi77cbaBGqXGScBCCa2EI5oFOAN7+uugDTpxNLXqi e7i7z88AR1av34bIMOsldCWY8GLiPqX08tRKmweOq1TAA+T3xwcIi49Qd3M7AYqSv+Ez FCJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712306494; x=1712911294; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gSABBNNlKEhtSsrOAA7jkzf/IIG0fsXnntsFQ9SmQNk=; b=CAyrZqupWYNaeOnhqI+64+4aE/LaRYC1LwL3Pf74kTv4CGyTZSUVBds5VwnKItwWQ5 FcsmZHc3gVKd/5c49uN6w93CFqGfTHK0XvhNm8sIrqLccxaxI5ZWIasHmHroabAZNhGk BMdP4ZF3yliVt7lU40jjLE2FphucPgjKyXHChkXxN+tfYDfwvzvGvyVE0y84rGeEhthb J10RHwgd1U1Zw8I3RZqkSwunVOnMqfG3fjUzd+7pKtGUxGtyhpIBbRyY4BKVouZAjU2t 6VRqKBBBSRo2s5oU7pZsXczqsj3C4IUfSmTdosayYBHMVqOwtLkShAiisg+E7AoPcPwT o+DA== X-Forwarded-Encrypted: i=1; AJvYcCW2yZ5QIZeFfr4m4CrrZKwdi49s7Alorv3t7Opom41OVmVlsMy1hQEpg8hzI4sOte284+inf+t4K0OSvVfuWtbbbbr+8OqkcIgdwdJewfT/ X-Gm-Message-State: AOJu0YwdN/uX8AdjAPfa3Ih8EeSCLUNOZqjxl6Mtj3pQSYky5Lzu+1vG h++L4/eEN8eQo/FdC4n8PR0vlb867jSCFZx4Wjd3erFXZqMBCEPhsopq76BAz00= X-Google-Smtp-Source: AGHT+IGElqD09S+bJG4HGQvHSKf6D8Gm7soI+u09xdQyhSPfpytTlYXflLgvpGmtQOzdAf/NVzT1EQ== X-Received: by 2002:a2e:7d07:0:b0:2d8:3cd3:35d with SMTP id y7-20020a2e7d07000000b002d83cd3035dmr709319ljc.33.1712306494294; Fri, 05 Apr 2024 01:41:34 -0700 (PDT) Received: from [127.0.1.1] (netpanel-87-246-222-101.pol.akademiki.lublin.pl. [87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:33 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:29 +0200 Subject: [PATCH 1/6] soc: qcom: Move some socinfo defines to the header, expand them MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-1-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" In preparation for parsing the chip "feature code" (FC) and "product code" (PC) (essentially the parameters that let us conclusively characterize the sillicon we're running on, including various speed bins), move the socinfo version defines to the public header and include some more FC/PC defines. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/socinfo.c | 8 -------- include/linux/soc/qcom/socinfo.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 277c07a6603d..cf4616a468f2 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -21,14 +21,6 @@ #include -/* - * SoC version type with major number in the upper 16 bits and minor - * number in the lower 16 bits. - */ -#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) -#define SOCINFO_MINOR(ver) ((ver) & 0xffff) -#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) - /* Helper macros to create soc_id table */ #define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id) #define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name) diff --git a/include/linux/soc/qcom/socinfo.h b/include/linux/soc/qcom/socinfo.h index e78777bb0f4a..ba7f683bd32c 100644 --- a/include/linux/soc/qcom/socinfo.h +++ b/include/linux/soc/qcom/socinfo.h @@ -3,6 +3,8 @@ #ifndef __QCOM_SOCINFO_H__ #define __QCOM_SOCINFO_H__ +#include + /* * SMEM item id, used to acquire handles to respective * SMEM region. @@ -12,6 +14,14 @@ #define SMEM_SOCINFO_BUILD_ID_LENGTH 32 #define SMEM_SOCINFO_CHIP_ID_LENGTH 32 +/* + * SoC version type with major number in the upper 16 bits and minor + * number in the lower 16 bits. + */ +#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff) +#define SOCINFO_MINOR(ver) ((ver) & 0xffff) +#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff)) + /* Socinfo SMEM item structure */ struct socinfo { __le32 fmt; @@ -74,4 +84,30 @@ struct socinfo { __le32 boot_core; }; +/* Internal feature codes */ +enum feature_code { + /* External feature codes */ + SOCINFO_FC_UNKNOWN = 0x0, + SOCINFO_FC_AA, + SOCINFO_FC_AB, + SOCINFO_FC_AC, + SOCINFO_FC_AD, + SOCINFO_FC_AE, + SOCINFO_FC_AF, + SOCINFO_FC_AG, + SOCINFO_FC_AH, + SOCINFO_FC_EXT_RESERVE, +}; + +/* Internal feature codes */ +/* Valid values: 0 <= n <= 0xf */ +#define SOCINFO_FC_Yn(n) (0xf1 + n) +#define SOCINFO_FC_INT_RESERVE SOCINFO_FC_Yn(0x10) + +/* Product codes */ +#define SOCINFO_PC_UNKNOWN 0 +/* Valid values: 0 <= n <= 8, the rest is reserved */ +#define SOCINFO_PCn(n) (n + 1) +#define SOCINFO_PC_RESERVE (BIT(31) - 1) + #endif From patchwork Fri Apr 5 08:41:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13618673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 029FCCD1296 for ; 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:35 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:30 +0200 Subject: [PATCH 2/6] soc: qcom: smem: Add pcode/fcode getters MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-2-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Introduce getters for SoC product and feature codes and export them. Signed-off-by: Konrad Dybcio --- drivers/soc/qcom/smem.c | 66 +++++++++++++++++++++++++++++++++++++++++++ include/linux/soc/qcom/smem.h | 2 ++ 2 files changed, 68 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 7191fa0c087f..e89b4d26877a 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -795,6 +795,72 @@ int qcom_smem_get_soc_id(u32 *id) } EXPORT_SYMBOL_GPL(qcom_smem_get_soc_id); +/** + * qcom_smem_get_feature_code() - return the feature code + * @id: On success, we return the feature code here. + * + * Look up the feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_feature_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EINVAL; + + raw_code = __le32_to_cpu(info->feature_code); + + /* Ensure the value makes sense */ + if (raw_code >= SOCINFO_FC_INT_RESERVE) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_feature_code); + +/** + * qcom_smem_get_product_code() - return the product code + * @id: On success, we return the product code here. + * + * Look up feature code identifier from SMEM and return it. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_smem_get_product_code(u32 *code) +{ + struct socinfo *info; + u32 raw_code; + + info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, NULL); + if (IS_ERR(info)) + return PTR_ERR(info); + + /* This only makes sense for socinfo >= 16 */ + if (__le32_to_cpu(info->fmt) < SOCINFO_VERSION(0, 16)) + return -EINVAL; + + raw_code = __le32_to_cpu(info->pcode); + + /* Ensure the value makes sense */ + if (raw_code >= SOCINFO_FC_INT_RESERVE) + raw_code = SOCINFO_FC_UNKNOWN; + + *code = raw_code; + + return 0; +} +EXPORT_SYMBOL_GPL(qcom_smem_get_product_code); + static int qcom_smem_get_sbl_version(struct qcom_smem *smem) { struct smem_header *header; diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index a36a3b9d4929..aef8c9fc6c08 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -13,5 +13,7 @@ int qcom_smem_get_free_space(unsigned host); phys_addr_t qcom_smem_virt_to_phys(void *p); int qcom_smem_get_soc_id(u32 *id); +int qcom_smem_get_feature_code(u32 *code); +int qcom_smem_get_product_code(u32 *code); #endif From patchwork Fri Apr 5 08:41:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13618672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB4C6CD11C2 for ; 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:37 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:31 +0200 Subject: [PATCH 3/6] drm/msm/adreno: Allow specifying default speedbin value MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-3-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Neil Armstrong Usually, speedbin 0 is the "super SKU", a.k.a the one which can clock the highest. Falling back to it when things go wrong is largely suboptimal, as more often than not, the top frequencies are not supposed to work on other bins. Let the developer specify the intended "lowest common denominator" bin in struct adreno_info. If not specified, partial struct initialization will ensure it's set to zero, retaining previous behavior. Signed-off-by: Neil Armstrong [Konrad: clean up, add commit message] Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0674aca0f8a3..4cbdfabbcee5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2915,7 +2915,7 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", speedbin); - supp_hw = BIT(0); /* Default */ + supp_hw = BIT(info->default_speedbin); /* Default */ } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..460b399be37b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -110,6 +110,7 @@ struct adreno_info { * {SHRT_MAX, 0} sentinal. */ struct adreno_speedbin *speedbins; + unsigned int default_speedbin; }; #define ADRENO_CHIP_IDS(tbl...) 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:38 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:32 +0200 Subject: [PATCH 4/6] drm/msm/adreno: Implement SMEM-based speed bin MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-4-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On recent (SM8550+) Snapdragon platforms, the GPU speed bin data is abstracted through SMEM, instead of being directly available in a fuse. Add support for SMEM-based speed binning, which includes getting "feature code" and "product code" from said source and parsing them to form something that lets us match OPPs against. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 8 +++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 39 +++++++++++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++++++--- 4 files changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4cbdfabbcee5..6776fd80f7a6 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2890,13 +2890,15 @@ static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) +static int a6xx_set_supported_hw(struct adreno_gpu *adreno_gpu, + struct device *dev, + const struct adreno_info *info) { u32 supp_hw; u32 speedbin; int ret; - ret = adreno_read_speedbin(dev, &speedbin); + ret = adreno_read_speedbin(adreno_gpu, dev, &speedbin); /* * -ENOENT means that the platform doesn't support speedbin which is * fine @@ -3056,7 +3058,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); - ret = a6xx_set_supported_hw(&pdev->dev, config->info); + ret = a6xx_set_supported_hw(adreno_gpu, &pdev->dev, config->info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index c3703a51287b..901ef767e491 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -6,6 +6,8 @@ * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. */ +#include + #include "adreno_gpu.h" bool hang_debug = false; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 074fb498706f..0e4ff532ac3c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -21,6 +21,9 @@ #include "msm_gem.h" #include "msm_mmu.h" +#include +#include + static u64 address_space_size = 0; MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space"); module_param(address_space_size, ullong, 0600); @@ -1057,9 +1060,37 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } -int adreno_read_speedbin(struct device *dev, u32 *speedbin) +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin) { - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + u32 fcode, pcode; + int ret; + + /* Try reading the speedbin via a nvmem cell first */ + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); + if (!ret && ret != -EINVAL) + return ret; + + ret = qcom_smem_get_feature_code(&fcode); + if (ret) { + dev_err(dev, "Couldn't get feature code from SMEM!\n"); + return ret; + } + + ret = qcom_smem_get_product_code(&pcode); + if (ret) { + dev_err(dev, "Couldn't get product code from SMEM!\n"); + return ret; + } + + /* Don't consider fcode for external feature codes */ + if (fcode <= SOCINFO_FC_EXT_RESERVE) + fcode = SOCINFO_FC_UNKNOWN; + + *speedbin = FIELD_PREP(ADRENO_SKU_ID_PCODE, pcode) | + FIELD_PREP(ADRENO_SKU_ID_FCODE, fcode); + + return ret; } int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, @@ -1098,9 +1129,9 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) + if (adreno_read_speedbin(adreno_gpu, dev, &speedbin) || !speedbin) speedbin = 0xffff; - adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); + adreno_gpu->speedbin = speedbin; gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config->chip_id)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 460b399be37b..1770a9e20484 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -81,7 +81,12 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; struct adreno_speedbin { - uint16_t fuse; + /* <= 16-bit for NVMEM fuses, 32b for SOCID values */ + uint32_t fuse; +#define ADRENO_SKU_ID_PCODE GENMASK(31, 16) +#define ADRENO_SKU_ID_FCODE GENMASK(15, 0) +#define ADRENO_SKU_ID(pcode, fcode) (pcode << 16 | fcode) + uint16_t speedbin; }; @@ -137,7 +142,7 @@ struct adreno_gpu { struct msm_gpu base; const struct adreno_info *info; uint32_t chip_id; - uint16_t speedbin; + uint32_t speedbin; const struct adreno_gpu_funcs *funcs; /* interesting register offsets to dump: */ @@ -520,7 +525,8 @@ int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags, struct adreno_smmu_fault_info *info, const char *block, u32 scratch[4]); -int adreno_read_speedbin(struct device *dev, u32 *speedbin); +int adreno_read_speedbin(struct adreno_gpu *adreno_gpu, + struct device *dev, u32 *speedbin); /* * For a5xx and a6xx targets load the zap shader that is used to pull the GPU From patchwork Fri Apr 5 08:41:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13618675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56AECCD11C2 for ; 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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:40 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:33 +0200 Subject: [PATCH 5/6] drm/msm/adreno: Add speedbin data for SM8550 / A740 MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-5-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add speebin data for A740, as found on SM8550 and derivative SoCs. Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/adreno_device.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 901ef767e491..c976a485aef2 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -570,6 +570,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { ADRENO_SKU_ID(SOCINFO_PC_UNKNOWN, SOCINFO_FC_AC), 0 }, + { ADRENO_SKU_ID(SOCINFO_PC_UNKNOWN, SOCINFO_FC_AF), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(1), SOCINFO_FC_UNKNOWN), 1 }, + { ADRENO_SKU_ID(SOCINFO_PCn(2), SOCINFO_FC_Yn(0x0)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(2), SOCINFO_FC_Yn(0x2)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(4), SOCINFO_FC_Yn(0x0)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(4), SOCINFO_FC_Yn(0x2)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(6), SOCINFO_FC_Yn(0x0)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(6), SOCINFO_FC_Yn(0x1)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(6), SOCINFO_FC_Yn(0xd)), 0 }, + { ADRENO_SKU_ID(SOCINFO_PCn(6), SOCINFO_FC_Yn(0xe)), 0 }, + ), + .default_speedbin = 1, }, { .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ .family = ADRENO_7XX_GEN3, From patchwork Fri Apr 5 08:41:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 13618676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25470C67861 for ; Fri, 5 Apr 2024 08:41:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 31F84113A92; Fri, 5 Apr 2024 08:41:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="U7g/mDQk"; dkim-atps=neutral Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) by gabe.freedesktop.org (Postfix) with ESMTPS id 15396113A8A for ; Fri, 5 Apr 2024 08:41:44 +0000 (UTC) Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2d700beb60bso31051811fa.1 for ; Fri, 05 Apr 2024 01:41:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1712306502; x=1712911302; darn=lists.freedesktop.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=X04cOGIXIpn74O231A72oQJ+8vGZIsJ7iLKhJyEMwh4=; b=U7g/mDQkw6zSiqpA/CWa5ZOCviMs1zfesMl7R3HtkbT5pAM1unwn8mJ7xs6w05mOA6 ZNgI8+ghU37jsIvmitfJzI1jFbIL2SWiu72q8CO2N5SR61ywLdd6TWSl3fviC4OwAlIT DAsqiRs4YEtGtEugzvz2cO7jPcA8Matbv5hUudI8LAL1TdU6w5AwnA72avQ4sW14UNa6 7ihy/KtJmQHa/uSTFPjNEHLcGU59wMInvZouPMj6e4u+PusP4seDnt5suLf77KvzKzeS A3Rr669zpl6O788UFynY7yr0d91wE/J5+Cp+Jbb2rpsCElSOA4tXOk9jSR1M2/BHVxj3 dA/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712306502; x=1712911302; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X04cOGIXIpn74O231A72oQJ+8vGZIsJ7iLKhJyEMwh4=; b=nTLGOocnU3W548muInmLz43JZU77l3/MVjC988ywPtF00d3lvQKpJAav37pVqXOI3z dgV0joSobQQ9OE4DGKD7xSEr1H71uk0JlaPDD76LGKvE9iGoyILDJ+eGNTU0rEN9TsXG TSb9ExI9CBK4hHLqTbanLaZfBqi3RkOVBOa+yduwbmUT8WF7rVZHXnQRnQUmKa04g+xM UQq314gzBMPjVFLHOKj3DaM2klQKccn9P2nHfGEH6dbIP55dYstoVLKTjFQ/rDAQqLWT I+rFCUPfdCSjEF5OGkXyL+is+uz49lenG6m23xPjPLUAmICJIcSF4HyfKh7V0XjoNJbi F3hA== X-Forwarded-Encrypted: i=1; AJvYcCVeyOq2WLNiztUnS9Ixzl/L+lI/dvpEIME8ohXIgDWNtumToVu0nMpiHJrP6j0bOndbQ32R34VWHURTxfCpORX2D7rCD6WpqWTeOMW1aYwO X-Gm-Message-State: AOJu0Yz+W8mCQ/Jy8yROeWl3mKRDzpvW1RySRimTVO1fdYRqtoX+QdK5 CM0TZL5isVlPCr4A0XqGChnvCdi2xGt1cO1IfPIuJTM8QyUCfxQNKqpXeYNobHc= X-Google-Smtp-Source: AGHT+IEaoyjVPXNaHJVLqh2HFfjOBPe62rwY6OgCDrYa4WIoKPR3hqGj3KeEFkwYiLQdakO91Cypiw== X-Received: by 2002:a2e:980a:0:b0:2d6:c749:17bc with SMTP id a10-20020a2e980a000000b002d6c74917bcmr897025ljj.31.1712306502374; Fri, 05 Apr 2024 01:41:42 -0700 (PDT) Received: from [127.0.1.1] (netpanel-87-246-222-101.pol.akademiki.lublin.pl. [87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:42 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:34 +0200 Subject: [PATCH 6/6] arm64: dts: qcom: sm8550: Wire up GPU speed bin & more OPPs MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-6-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Add the speedbin masks to ensure only the desired OPPs are available on chips of a given bin. Using this, add the binned 719 MHz OPP and the non-binned 124.8 MHz. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 5cae8d773cec..2f6842f6a5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2087,48 +2087,67 @@ zap-shader { memory-region = <&gpu_micro_code_mem>; }; - /* Speedbin needs more work on A740+, keep only lower freqs */ gpu_opp_table: opp-table { compatible = "operating-points-v2"; + opp-719000000 { + opp-hz = /bits/ 64 <719000000>; + opp-level = ; + opp-supported-hw = <0x1>; + }; + opp-680000000 { opp-hz = /bits/ 64 <680000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-615000000 { opp-hz = /bits/ 64 <615000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-475000000 { opp-hz = /bits/ 64 <475000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-401000000 { opp-hz = /bits/ 64 <401000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-348000000 { opp-hz = /bits/ 64 <348000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-295000000 { opp-hz = /bits/ 64 <295000000>; opp-level = ; + opp-supported-hw = <0x3>; }; opp-220000000 { opp-hz = /bits/ 64 <220000000>; opp-level = ; + opp-supported-hw = <0x3>; + }; + + opp-124800000 { + opp-hz = /bits/ 64 <124800000>; + opp-level = ; + opp-supported-hw = <0x3>; }; }; };