From patchwork Fri Apr 5 15:02:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619169 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC4A216F83A; Fri, 5 Apr 2024 15:02:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329340; cv=none; b=JoCch8eCAgZX4N+/tXA79mX9pTYNHXAdAJUJA5gfAEjV2s4k9wsJ2TDwGvj8TmqbcRyO5ESK1V6XGSVmHPkkXQsaIufBanNPvZnlaN7fJcydLFELM+V8DMsOGrYkGm5fqVFv0vM8IENZ5a+PRAO5cDrGz1eslovilNAPjaaj6Gw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329340; c=relaxed/simple; bh=Fv59z7lNREOZ9zqggxggPs2+8dCuzPBU1A5Z3HcBFGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kbnL+GaLl+n/2iVSNhE6KHAATmkw4TKWQrNRoWk4st69WF4oj2NZ6alzznygFG2t3oR8Ys23MTfVV7z+0DVC5WgC48x9IgtHUbqpDmD9YmIM9EV9l/U1+rSq2ylYi9xNKUxqpxE91vNBDdI1U6Bh7SwUUIbPJZuIuDIK+artP4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NEXcKC/n; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NEXcKC/n" Received: by mail.gandi.net (Postfix) with ESMTPSA id 8027F1BF210; Fri, 5 Apr 2024 15:02:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RzJfFQbN8uRXN7g6fZUa72H4ER4DsHLI5fXnygcJqVA=; b=NEXcKC/nJoeOj4z85TKUHfO7Ufw4Hu1vLkHXsBoc4uu0qAxFacaLS3pPs8LFPGJapWNK15 pwgrBB5MQ1EfN2OdfFg3niRDEAdXnyMcjdR35QL0pUZKO0F6cfzfwMd0vF7jspYrraUQOq f9zK/ZFV72Z7Lmpjiw2JAmuN+BN53nmJy7uj4OU7vxU9P1fN0jEeuSKPqY6m7TLA5FGoPF wj1VtEwrBpco9jAOEj4x/kcloPVgIStfH6b6Cs7xJVNrPW5YfbLmG+RmreIq7FjouIOBPw G9hbkEfAsYr3i6ZDKHlRjYLdSNggg7rrA9rwSrEHtUcbB7+dvBEVuZ2sfiY3IQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:11 +0200 Subject: [PATCH v2 01/11] spi: dt-bindings: cdns,qspi-nor: add mobileye,eyeq5-ospi compatible Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-1-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= , Krzysztof Kozlowski X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Add Mobileye EyeQ5 compatible. FIFO depth shall not be passed; hardware can detect it. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Théo Lebrun --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index cca81f89e252..5509c126b1cf 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -61,6 +61,17 @@ allOf: cdns,fifo-depth: enum: [ 128, 256 ] default: 128 + - if: + properties: + compatible: + contains: + const: mobileye,eyeq5-ospi + then: + properties: + cdns,fifo-depth: false + else: + required: + - cdns,fifo-depth properties: compatible: @@ -68,6 +79,7 @@ properties: - items: - enum: - amd,pensando-elba-qspi + - mobileye,eyeq5-ospi - ti,k2g-qspi - ti,am654-ospi - intel,lgm-qspi @@ -145,7 +157,6 @@ required: - reg - interrupts - clocks - - cdns,fifo-depth - cdns,fifo-width - cdns,trigger-address - '#address-cells' From patchwork Fri Apr 5 15:02:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619170 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55DB616F0FB; Fri, 5 Apr 2024 15:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329340; cv=none; b=vE43xMU0ikewtHYn/0lNbi7zhuIw1X6naw6FsLsD1w8mnPHQK6h5h03M17SG6jsq2Rl6tm3Ta+rTT9Ncfg4dggvQqhqbFRtpwDRiwlwjetvrQwLcyNw9pdQKrquEpZ5AKoRi9Yp0cLrnpD2fmbi9Le5PbDA2WoUiPaWSiT4kXFI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329340; c=relaxed/simple; bh=kWHhdR9UQSbOBCijUt28orjnewhf0V+/gLGehzP8igM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GLZoN5/3Unnx1wUeM9x0vGnEuwgOBbQIqKn88sSmlKSRtKKbznEkFNE0IsfjGNFEYgnMaioGKM2jz0jybRMeoko76RMCKPf7UMsGc64jodqh4lBVR/MsY9IToUTxhUjVGCvZWvX1d+2Fn5u2S0W5zduGxi3qt2tpMeF17wyTgTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=mW0I9HEw; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="mW0I9HEw" Received: by mail.gandi.net (Postfix) with ESMTPSA id 30F3E1BF217; Fri, 5 Apr 2024 15:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329336; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RRgBiKVeJ2Jy7Ape+Lobb5Tr82aRXUnmBplRp1OZZNA=; b=mW0I9HEwwZDMIO+C+TQ5ZjVohADU0OBQmmyF2LkCE46oCbPNhM4s1/Yu6LaZn5jy5Cc1Ni adDm15EpMl2e3+o6BEHKfi9NdGKbc9ekwkKOP54rzXj9W69eOHCx9M7uvq5e8flaJ77vgG JXsLgd9zv2JVt3SAg+IoSPTsjYL5dg3EO0o49h6n8/aRTXHAnCNznE5xYlpk1It/oCI5Lo XfRmrLXDyP1esHtWQJ0JEI5tKPusZ0/bxUfZEFBbnk2KwzPgwXDni4ec5G/C9beHvskZ0O m3nEvDlowyScKSiDi1D2hVQhIDg/39PfVKPHJT+xVcQyj1Ipj4rxuJW2VRUQmw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:12 +0200 Subject: [PATCH v2 02/11] spi: dt-bindings: cdns,qspi-nor: sort compatibles alphabetically Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-2-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Compatibles are ordered by date of addition. Switch to (deterministic) alphabetical ordering. Signed-off-by: Théo Lebrun Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index 5509c126b1cf..e53d443c6f93 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -79,13 +79,13 @@ properties: - items: - enum: - amd,pensando-elba-qspi - - mobileye,eyeq5-ospi - - ti,k2g-qspi - - ti,am654-ospi - intel,lgm-qspi - - xlnx,versal-ospi-1.0 - intel,socfpga-qspi + - mobileye,eyeq5-ospi - starfive,jh7110-qspi + - ti,am654-ospi + - ti,k2g-qspi + - xlnx,versal-ospi-1.0 - const: cdns,qspi-nor - const: cdns,qspi-nor From patchwork Fri Apr 5 15:02:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619171 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA72C16F826; Fri, 5 Apr 2024 15:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329341; cv=none; b=f01a6dKIhTeIONX6Gbw8EDQ5iV6NIt+cE1iezGVdcDmZ7uvaZooUH+0U41iXeaMsy8VEp3sPqUJ7Mi8nQaoyBAL6h9daT1a0Yf+xsst21Sqfup+Xe7juokhXtQgiUu1uFng2cl3ChaUvwnwLy6J16CthrUa69mQCAxWjyh4rfwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329341; c=relaxed/simple; bh=JYqa8ClMGY37mf7kIy93d39+cOUrt+d9iRtScZqNWn4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IRP/Ct391JRYruGQcNr+4xw7SRTGWK0W9jLEOWrBCtUVfzS8tusSUltsAXQ8rRWSQtiq56AvxOfat+JAteT38iBM0b/B0oetBLQZJe5ZjG6uaYAorac3KlCX3NgBO0a0kmM7Gp2X9CzKHNFYJhYDFkaw7uLeFTDqcusU0VSh7vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=CU+Bk9VN; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="CU+Bk9VN" Received: by mail.gandi.net (Postfix) with ESMTPSA id CC8FE1BF203; Fri, 5 Apr 2024 15:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329337; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=//mrmmNpsITXWI/YjExwEf3g6/noqwNFwDTbVRFFcWs=; b=CU+Bk9VNIPYfIPNQw8srECJKdGq5AePaAEO9uYNuRQUoheQVYuTAO8bFjQeC28ZcDL7oAn Cz+70+5ToE1x9xbbEWb2ws1b+cVeYh82YrAIbYG8cKh1TGZZzqO8LpAevanT2Xm1N9iX8t 6RH8cJLxtjfjFKNkoPumB4NwQXaFLZDnsBNCOowY4NW8mQSPk1WHuekMIayn+Es5J0ABJM SWBSxlWUkmeEtqCjSRKTHCYewkidrGfQhAMuaEJK81Z26z0/o3nPrbSCJiq98X1Mv2glGB aSBLr5yDt6WTJPOSm36WDEDEiLB3y+P7T0QmrQW8zPlehyuJ9ecJGWcmZcUsWA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:13 +0200 Subject: [PATCH v2 03/11] spi: cadence-qspi: allow building for MIPS Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-3-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com The Cadence QSPI Controller driver is used on Mobileye EyeQ5 platform. Allow building on MIPS. Signed-off-by: Théo Lebrun --- drivers/spi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bc7021da2fe9..548af3d9e30d 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -246,7 +246,7 @@ config SPI_CADENCE config SPI_CADENCE_QUADSPI tristate "Cadence Quad SPI controller" - depends on OF && (ARM || ARM64 || X86 || RISCV || COMPILE_TEST) + depends on OF && (ARM || ARM64 || X86 || RISCV || MIPS || COMPILE_TEST) help Enable support for the Cadence Quad SPI Flash controller. From patchwork Fri Apr 5 15:02:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619172 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6ED916F82C; Fri, 5 Apr 2024 15:02:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329342; cv=none; b=TXKyPB7/QuOE/atxI48EF8Qt6UcfCMUbdyKc9EurxxemP28Ts/BrDn/OvDrk5xuCT+i9B9YRxBAunpXp7pt/7FK5ZgqGwYfhBlvWjlyTEkNH0R3k+p0GtmF/gGHKyP/NlDO7TIK6mAaC+v2IOHil/sSNskgKiFiHqE8rGzBysaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329342; c=relaxed/simple; bh=Wj+u6ruHBUJBotyvFJYd7sZqwOLVa4pj2XBfnuzmF2c=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LVRBAvL3j4QImOccVuoMTX4AB61MXmUDSfQCiliISACcVtUmicSt8gpVVHvdXcDaNWsU6FN1psK5iZDAL3tlwGceDw2276VNE3n1J/dR742ppvPWPi2qlvNG7FucpE/yIqFZYP/6nicghWa/X4QUOou0MyWYLPsuHhy1RzBqmBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=dobKdTLP; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="dobKdTLP" Received: by mail.gandi.net (Postfix) with ESMTPSA id 7BA2B1BF218; Fri, 5 Apr 2024 15:02:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329338; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7awS6QTNvJz7vJeE9+3leQq2yx+aHNtkDKIF/ROzt+4=; b=dobKdTLPQjLIMKUvRLnHzRmMrgSKTHGfMdCEtwANB1e3DW61caDvZtIgetPR9oi9Oxdnkf 24HwyB/UPNnNz/J5N3cu8hwqBoEm5JjJDpYLju5ek1Qni5r2VcIyMwH9UwjeVf/YIt1mBn Amt4sNLwroPO5GhZAe0jZPlSa3wLk7XWm0A43kek/MRay7b8TlXyYTpGatrZK2p0jnwZkh qaPe002zM8fWRFW1kClhy/7uKx4X7HSugVB5FJ9dO0PoaUrGO91OoNKdREGX1GrHhhfeUJ 6i9KtRunvESZjKrFVOFFzQYE6IbH6DltHW4S8UzCn7lY1UOi0dExM7eg0p/weg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:14 +0200 Subject: [PATCH v2 04/11] spi: cadence-qspi: store device data pointer in private struct Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-4-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Avoid of_device_get_match_data() call on each IRQ and each read operation. Store pointer in `struct cqspi_st` device instance. End-to-end performance measurements improve with this patch. On a given octal flash, reading 235M over UBIFS is ~3.4% faster. During that read, the average cqspi_exec_mem_op() call goes from 85.4µs to 80.7µs according to ftrace. The worst case goes from 622.4µs to 615.2µs. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 350b3dab3a05..abc1c35929cc 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -102,6 +102,8 @@ struct cqspi_st { bool apb_ahb_hazard; bool is_jh7110; /* Flag for StarFive JH7110 SoC */ + + const struct cqspi_driver_platdata *ddata; }; struct cqspi_driver_platdata { @@ -334,11 +336,8 @@ static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi) static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) { struct cqspi_st *cqspi = dev; + const struct cqspi_driver_platdata *ddata = cqspi->ddata; unsigned int irq_status; - struct device *device = &cqspi->pdev->dev; - const struct cqspi_driver_platdata *ddata; - - ddata = of_device_get_match_data(device); /* Read interrupt status */ irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); @@ -1358,16 +1357,13 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, const struct spi_mem_op *op) { struct cqspi_st *cqspi = f_pdata->cqspi; - struct device *dev = &cqspi->pdev->dev; - const struct cqspi_driver_platdata *ddata; + const struct cqspi_driver_platdata *ddata = cqspi->ddata; loff_t from = op->addr.val; size_t len = op->data.nbytes; u_char *buf = op->data.buf.in; u64 dma_align = (u64)(uintptr_t)buf; int ret; - ddata = of_device_get_match_data(dev); - ret = cqspi_read_setup(f_pdata, op); if (ret) return ret; @@ -1822,7 +1818,8 @@ static int cqspi_probe(struct platform_device *pdev) /* write completion is supported by default */ cqspi->wr_completion = true; - ddata = of_device_get_match_data(dev); + ddata = of_device_get_match_data(dev); + cqspi->ddata = ddata; if (ddata) { if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, From patchwork Fri Apr 5 15:02:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619173 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CE4016F854; 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arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="PxQN75Id" Received: by mail.gandi.net (Postfix) with ESMTPSA id 2CCE91BF21B; Fri, 5 Apr 2024 15:02:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329338; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jXGUgPteTgG103mmpT+uk+Z0LmFOU065TLnoYvPItNU=; b=PxQN75IdiqDieoXjFrJbS+oYV0dqsp2PxpzPnqE8+bgc/80r2/FPpE4CEsYF3PqS5JXKq5 +FkuKdbHOJJdC0xxB4RHPkfs6pNvHYOfXrkmqWUVgRFomgZ40QOyHASNzlBTRcVRFJXy5u 0rgWmyOemYp9yw2SlTmET5SuJ39walPKKZ6WQuMeljXGe2JZc5KAxm3WGJ5s9xWdrlH/sG 6DY8qX5sGHBh6/roIhQobQvaR4PVqNs0s2loSJZi4XNL65PrBrW1ejk+KEk9L1eRXwaRhr SSwtzExb9sOa9I5UBg7Qr4hjxWcA5USW0Myg4KaQ1ON4Y12A05+xVfUKKNrYcg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:15 +0200 Subject: [PATCH v2 05/11] spi: cadence-qspi: add FIFO depth detection quirk Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-5-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Use hardware ability to read the FIFO depth thanks to CQSPI_REG_SRAMPARTITION that is partially read-only. Keep current behavior identical for existing compatibles. Hide feature behind a flag. If unset and detected value is different from the devicetree-provided value, warn. Move probe cqspi->ddata assignment prior to cqspi_of_get_pdata() call. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index abc1c35929cc..04a473fafe43 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -42,6 +42,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); #define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3) #define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) +#define CQSPI_DETECT_FIFO_DEPTH BIT(6) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -1500,13 +1501,15 @@ static int cqspi_of_get_flash_pdata(struct platform_device *pdev, static int cqspi_of_get_pdata(struct cqspi_st *cqspi) { + const struct cqspi_driver_platdata *ddata = cqspi->ddata; struct device *dev = &cqspi->pdev->dev; struct device_node *np = dev->of_node; u32 id[2]; cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); - if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { + if (!(ddata && ddata->quirks & CQSPI_DETECT_FIFO_DEPTH) && + of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { dev_err(dev, "couldn't determine fifo-depth\n"); return -ENXIO; } @@ -1538,8 +1541,6 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) { u32 reg; - cqspi_controller_enable(cqspi, 0); - /* Configure the remap address register, no remap */ writel(0, cqspi->iobase + CQSPI_REG_REMAP); @@ -1573,8 +1574,29 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) reg |= CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); } +} - cqspi_controller_enable(cqspi, 1); +static void cqspi_controller_detect_fifo_depth(struct cqspi_st *cqspi) +{ + const struct cqspi_driver_platdata *ddata = cqspi->ddata; + struct device *dev = &cqspi->pdev->dev; + u32 reg, fifo_depth; + + /* + * Bits N-1:0 are writable while bits 31:N are read as zero, with 2^N + * the FIFO depth. + */ + writel(U32_MAX, cqspi->iobase + CQSPI_REG_SRAMPARTITION); + reg = readl(cqspi->iobase + CQSPI_REG_SRAMPARTITION); + fifo_depth = reg + 1; + + if (ddata && ddata->quirks & CQSPI_DETECT_FIFO_DEPTH) { + cqspi->fifo_depth = fifo_depth; + dev_dbg(dev, "using FIFO depth of %u\n", fifo_depth); + } else if (fifo_depth != cqspi->fifo_depth) { + dev_warn(dev, "detected FIFO depth (%u) different from config (%u)\n", + fifo_depth, cqspi->fifo_depth); + } } static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) @@ -1727,6 +1749,7 @@ static int cqspi_probe(struct platform_device *pdev) cqspi->pdev = pdev; cqspi->host = host; cqspi->is_jh7110 = false; + cqspi->ddata = ddata = of_device_get_match_data(dev); platform_set_drvdata(pdev, cqspi); /* Obtain configuration from OF. */ @@ -1818,8 +1841,6 @@ static int cqspi_probe(struct platform_device *pdev) /* write completion is supported by default */ cqspi->wr_completion = true; - ddata = of_device_get_match_data(dev); - cqspi->ddata = ddata; if (ddata) { if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, @@ -1861,7 +1882,10 @@ static int cqspi_probe(struct platform_device *pdev) } cqspi_wait_idle(cqspi); + cqspi_controller_enable(cqspi, 0); + cqspi_controller_detect_fifo_depth(cqspi); cqspi_controller_init(cqspi); + cqspi_controller_enable(cqspi, 1); cqspi->current_cs = -1; cqspi->sclk = 0; @@ -1944,7 +1968,9 @@ static int cqspi_runtime_resume(struct device *dev) clk_prepare_enable(cqspi->clk); cqspi_wait_idle(cqspi); + cqspi_controller_enable(cqspi, 0); cqspi_controller_init(cqspi); + cqspi_controller_enable(cqspi, 1); cqspi->current_cs = -1; cqspi->sclk = 0; From patchwork Fri Apr 5 15:02:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619174 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA17716F8F5; Fri, 5 Apr 2024 15:02:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="WqNX9wVm" Received: by mail.gandi.net (Postfix) with ESMTPSA id C0CB31BF21D; Fri, 5 Apr 2024 15:02:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329339; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cm7TX0bpIVYxGLrSDwf5aBC/t6bqErKnJF7vHkAQ4uY=; b=WqNX9wVmYWN05Tct3L98MvxWThB5skZXtlNBvqusNA48PvOw0pPmqn91/WtW/9bdPd8yT5 DF/6/dii85vj6jGz+FUtFzyhO80dvVy1W/3ms1Kwx7G3dHoBWvwNPKXuRSOaZpXgJ2LSbr CATvbqHa7B22qF6UlYXtafcm9CxcZO57JcCG6eaVIsXAzYQXBLKaDWNrN+G4V7m86F7n2Y c8xV6PbI58/92IVluO3my73okmF1hjZb1FHBe4q+CD68OCIJI5qXui42Aq1TmfPBexze5+ h/64fmLmwHP04YB+Q9Wm4kigBKKRCRla+49bJ3ktxAWO0VZJgqOuMh+wcGvQMQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:16 +0200 Subject: [PATCH v2 06/11] spi: cadence-qspi: minimise register accesses on each op if !DTR Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-6-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com cqspi_enable_dtr() is called for each operation, commands or not, reads or writes. It writes CQSPI_REG_CONFIG then waits for idle (three successful reads). Skip that in the no-DTR case if DTR is already disabled. It cannot be skipped in the DTR case as cqspi_setup_opcode_ext() writes to a register and we must wait for idle state. According to ftrace, the average cqspi_exec_mem_op() call goes from 85.4µs to 83.6µs when reading 235M over UBIFS on an octal flash. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 04a473fafe43..55d20d565fe5 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -492,8 +492,11 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, if (ret) return ret; } else { - reg &= ~CQSPI_REG_CONFIG_DTR_PROTO; - reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE; + unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE; + /* Shortcut if DTR is already disabled. */ + if ((reg & mask) == 0) + return 0; + reg &= ~mask; } writel(reg, reg_base + CQSPI_REG_CONFIG); From patchwork Fri Apr 5 15:02:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619175 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8565316F915; Fri, 5 Apr 2024 15:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329344; cv=none; b=CJ0cu/7Qn8U7kiBXq+eZjVKrPT9c40MHnhyJUD+VgpL1ravCevYhod+J659Irp/Y0waPNfol4syVBPO+jLNt7jake43JG2kSaOjUXfg4TV18aJoE9Zjnr59ogI7+cDEod/29oE2HEWD5H/C7v0o1eGhlDMI4cg7AEY3ZG2TXNr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329344; c=relaxed/simple; bh=Ar8fBamV+L9arbDgrVzcqRsw0ePZyBU1WIsWO6nxU6U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XUMy5Ia6IyYpBsrGZolEcbxm2LohCXv+GK+HXpkIj7dEzmXWx7npQKGg8ZZDUJFDQ/Umb3Gw/NbH6YOwRuGtXzidhDp6RcivFFevsj42cjS3xTyQMf1mp9i5mWp7nhxwv9cFFHvlZPQ2EkAjELvDHIhTFW5eCGhK/VMTp0VBzyE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=NynxWG/G; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="NynxWG/G" Received: by mail.gandi.net (Postfix) with ESMTPSA id 63B991BF209; Fri, 5 Apr 2024 15:02:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329339; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Bw7wAnZBCykLnl0Z3hjw2J86RWa0b9ykf06ta9MdRww=; b=NynxWG/G+Vi1I1vRSv3V+VS+uycDUWI3UMhT1mgbqi2cnPbwAAm6cPKJ7OSlMI5M4JGFnW BOwY/vrzJ489BFeb4O1VgyxyrA0NjazrGoA5wICWvb6/BTt4UynaTwo18hd5uS2tGxZLZt ThoQoGBCbiPQz+RMZ0mUQ3yPcTA5cxWQUY7i6YRqlMU5jnFbdplNoBG7lQFDDa5PDN1SYM xxH1yT9OZOpyZAK1qqfzXgXJbm59UEFyLV2S7zRGatrCsC1lugDDFgbbzJUj621aq5ModA LesEkhdCte5jprORy1eAGECcO8ejvoVV/bCqdXCkXQfCH5UV1IcQ6HiEkiBTzQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:17 +0200 Subject: [PATCH v2 07/11] spi: cadence-qspi: add no-IRQ mode to indirect reads Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-7-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Support reads through polling, without any IRQ. The main reason is performance; profiling shows that the first IRQ comes quickly on our specific hardware. Once this IRQ arrives, we poll until all data is retrieved. Avoid initial sleep to reduce IRQ count. Hide this behavior behind a quirk flag. This is confirmed through micro-benchmarks, but also end-to-end performance tests. Mobileye EyeQ5, octal flash, reading 235M on a UBIFS filesystem: - No optimizations, ~10.34s, ~22.7 MB/s, 199230 IRQs - CQSPI_SLOW_SRAM, ~10.34s, ~22.7 MB/s, 70284 IRQs - CQSPI_RD_NO_IRQ, ~9.37s, ~25.1 MB/s, 521 IRQs Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 55d20d565fe5..ebb8c35f50fd 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -43,6 +43,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); #define CQSPI_SLOW_SRAM BIT(4) #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_DETECT_FIFO_DEPTH BIT(6) +#define CQSPI_RD_NO_IRQ BIT(7) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -703,6 +704,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, const size_t n_rx) { struct cqspi_st *cqspi = f_pdata->cqspi; + bool use_irq = !(cqspi->ddata && cqspi->ddata->quirks & CQSPI_RD_NO_IRQ); struct device *dev = &cqspi->pdev->dev; void __iomem *reg_base = cqspi->iobase; void __iomem *ahb_base = cqspi->ahb_base; @@ -726,17 +728,20 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, * all the read interrupts disabled for max performance. */ - if (!cqspi->slow_sram) + if (use_irq && cqspi->slow_sram) + writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + else if (use_irq) writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK); else - writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); + writel(0, reg_base + CQSPI_REG_IRQMASK); reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTRD_START_MASK, reg_base + CQSPI_REG_INDIRECTRD); while (remaining > 0) { - if (!wait_for_completion_timeout(&cqspi->transfer_complete, + if (use_irq && + !wait_for_completion_timeout(&cqspi->transfer_complete, msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) ret = -ETIMEDOUT; @@ -778,7 +783,7 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, bytes_to_read = cqspi_get_rd_sram_level(cqspi); } - if (remaining > 0) { + if (use_irq && remaining > 0) { reinit_completion(&cqspi->transfer_complete); if (cqspi->slow_sram) writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK); From patchwork Fri Apr 5 15:02:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619176 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E41A16FF30; Fri, 5 Apr 2024 15:02:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329344; cv=none; b=H3ycEEqXBdKb1UlzY7/xCiRHW1zAp0TVpIjo9lmRM68GcyuU6M3h5ziOSWseQIYGvJtsJA4U7V2Jkw82ZEADu71nr9qysDcib4gKA1VjW5HR2qsyVeRbBHLvbiIW6KaOCDOrF0mPGgxckGuxkcsZSVoWwrGsXzwlQIXA3KueVvA= ARC-Message-Signature: i=1; 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Fri, 5 Apr 2024 15:02:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329340; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D3TlB4DpD1JnUAQGSHUPmeuRrja5TpZ3NixofruQ0EE=; b=EjGfpTRHJNzjvcKzdqxSPjpu/sg6m4z/X/aGKA9zIscyiH46cSFfgFPNyw8gJWAWIQ4xDO mgRbsz+n6Hucfamf0MOLKzGFnk+k77IqGCjNjCXkFN9yR3q6sji+03wz+34xZf4VTra5JV EQ/7vv4Pqblu98yO81vm23fdeKx9P+kKHFjQoNiYML0QEIi3vCLhO9tya5BtQTVpF8d1ks 8X3A/afkl4Ii0y/7g6Qt4VKo3KnO5SA3wN+K86Nx+0qx16JrG/wSROAVUAqnmAqCcu6yoD DUwbW3mN2zvF/MSfHDFUK13BR5plKcOqc2WK3V+je8n2meCRw7VIRfxlcEUFxA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:18 +0200 Subject: [PATCH v2 08/11] spi: cadence-qspi: add early busywait to cqspi_wait_for_bit() Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-8-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com If the CQSPI_BUSYWAIT_EARLY quirk flag is on, call readl_relaxed_poll_timeout() with no sleep at the start of cqspi_wait_for_bit(). If its short timeout expires, a sleeping readl_relaxed_poll_timeout() call takes the relay. Behavior is hidden behind a quirk flag to keep the previous behavior the same on all platforms. The reason is to avoid hrtimer interrupts on the system. All read operations take less than 100µs. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 34 +++++++++++++++++++++++++--------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index ebb8c35f50fd..230aad490e03 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -44,6 +44,7 @@ static_assert(CQSPI_MAX_CHIPSELECT <= SPI_CS_CNT_MAX); #define CQSPI_NEEDS_APB_AHB_HAZARD_WAR BIT(5) #define CQSPI_DETECT_FIFO_DEPTH BIT(6) #define CQSPI_RD_NO_IRQ BIT(7) +#define CQSPI_BUSYWAIT_EARLY BIT(8) /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) @@ -110,7 +111,7 @@ struct cqspi_st { struct cqspi_driver_platdata { u32 hwcaps_mask; - u8 quirks; + u16 quirks; int (*indirect_read_dma)(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx); u32 (*get_dma_status)(struct cqspi_st *cqspi); @@ -121,6 +122,7 @@ struct cqspi_driver_platdata { /* Operation timeout value */ #define CQSPI_TIMEOUT_MS 500 #define CQSPI_READ_TIMEOUT_MS 10 +#define CQSPI_BUSYWAIT_TIMEOUT_US 500 /* Runtime_pm autosuspend delay */ #define CQSPI_AUTOSUSPEND_TIMEOUT 2000 @@ -299,13 +301,27 @@ struct cqspi_driver_platdata { #define CQSPI_REG_VERSAL_DMA_VAL 0x602 -static int cqspi_wait_for_bit(void __iomem *reg, const u32 mask, bool clr) +static int cqspi_wait_for_bit(const struct cqspi_driver_platdata *ddata, + void __iomem *reg, const u32 mask, bool clr, + bool busywait) { + u64 timeout_us = CQSPI_TIMEOUT_MS * USEC_PER_MSEC; u32 val; + if (busywait && ddata && ddata->quirks & CQSPI_BUSYWAIT_EARLY) { + int ret = readl_relaxed_poll_timeout(reg, val, + (((clr ? ~val : val) & mask) == mask), + 0, CQSPI_BUSYWAIT_TIMEOUT_US); + + if (ret != -ETIMEDOUT) + return ret; + + timeout_us -= CQSPI_BUSYWAIT_TIMEOUT_US; + } + return readl_relaxed_poll_timeout(reg, val, (((clr ? ~val : val) & mask) == mask), - 10, CQSPI_TIMEOUT_MS * 1000); + 10, timeout_us); } static bool cqspi_is_idle(struct cqspi_st *cqspi) @@ -435,8 +451,8 @@ static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg) writel(reg, reg_base + CQSPI_REG_CMDCTRL); /* Polling for completion. */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL, - CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_CMDCTRL, + CQSPI_REG_CMDCTRL_INPROGRESS_MASK, 1, true); if (ret) { dev_err(&cqspi->pdev->dev, "Flash command execution timed out.\n"); @@ -791,8 +807,8 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, } /* Check indirect done status */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD, - CQSPI_REG_INDIRECTRD_DONE_MASK, 0); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTRD, + CQSPI_REG_INDIRECTRD_DONE_MASK, 0, true); if (ret) { dev_err(dev, "Indirect read completion error (%i)\n", ret); goto failrd; @@ -1092,8 +1108,8 @@ static int cqspi_indirect_write_execute(struct cqspi_flash_pdata *f_pdata, } /* Check indirect done status */ - ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR, - CQSPI_REG_INDIRECTWR_DONE_MASK, 0); + ret = cqspi_wait_for_bit(cqspi->ddata, reg_base + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE_MASK, 0, false); if (ret) { dev_err(dev, "Indirect write completion error (%i)\n", ret); goto failwr; From patchwork Fri Apr 5 15:02:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619177 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1082E171640; 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arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="l0FcwKe2" Received: by mail.gandi.net (Postfix) with ESMTPSA id A983F1BF207; Fri, 5 Apr 2024 15:02:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329342; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F5PO+vwFUf8/nCeUbsDaSi0BqfsaPd3EG3ZxXLAXPXU=; b=l0FcwKe2Ye0H9G9ba6GIOniWdY40nd0ZUewY7xLyhmy8co9ZAgIkFyMQz/hpjvZxRhC/bq M+IWIl+KZRtkNxOthL6vFid9w5zsYBmlCjgxJhNZ2bvBGOv0cgMBsXl35/JAzvkut1xzmz UqKMwx7TAOEm88tqPB/E2u1IqbtatJ5kCQnU61+wF1j9nU4tmwuV6NiOtXdweFmTARkVyt 05LGg3Oiq3sIvQ6KkKiJ52FnsiVp0yBHdgaJxi64UzEADK4lCup7LYxK7HKl6jEGErbUOY 5549ia/0Bxtgckw1nsnXQwE9wCrAf3L6aGu8quYw2enu0apAQwJfjUlHJQDdtw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:19 +0200 Subject: [PATCH v2 09/11] spi: cadence-qspi: add mobileye,eyeq5-ospi compatible Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-9-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Declare a new mobileye,eyeq5-ospi compatible. Exploit quirk flags: detect FIFO depth through SRAMPARTITION register; avoid IRQs during read operations. Signed-off-by: Théo Lebrun --- drivers/spi/spi-cadence-quadspi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 230aad490e03..11f54f507787 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -2059,6 +2059,13 @@ static const struct cqspi_driver_platdata pensando_cdns_qspi = { .quirks = CQSPI_NEEDS_APB_AHB_HAZARD_WAR | CQSPI_DISABLE_DAC_MODE, }; +static const struct cqspi_driver_platdata mobileye_eyeq5_ospi = { + .hwcaps_mask = CQSPI_SUPPORTS_OCTAL, + .quirks = CQSPI_DISABLE_DAC_MODE | CQSPI_NO_SUPPORT_WR_COMPLETION | + CQSPI_DETECT_FIFO_DEPTH | CQSPI_RD_NO_IRQ | + CQSPI_BUSYWAIT_EARLY, +}; + static const struct of_device_id cqspi_dt_ids[] = { { .compatible = "cdns,qspi-nor", @@ -2092,6 +2099,10 @@ static const struct of_device_id cqspi_dt_ids[] = { .compatible = "amd,pensando-elba-qspi", .data = &pensando_cdns_qspi, }, + { + .compatible = "mobileye,eyeq5-ospi", + .data = &mobileye_eyeq5_ospi, + }, { /* end of table */ } }; From patchwork Fri Apr 5 15:02:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619178 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7EB4171665; Fri, 5 Apr 2024 15:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329346; cv=none; b=Eb1IVYMOA10zuyoB1E9DWK5Gw8meNXKg6TO/JuvvzZCclq47N5IXW4y1TqUSVK530qVX9Xh2rzVBBNMDGbMkTQQnUcajPmDObGMrwoXWmQ6e5Ub6KzGzXLlAPm2hVOkf4G3lAxxtabSOXaDqUSd1FIv+nDlrHgDpd8Mr3eASun8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329346; c=relaxed/simple; bh=vuFml2Tbieyo6tIWPbphQoCJOz5E27f346lkQPXpqDA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ItGpp8SNbEDxowHN9H/PvFNYnNy1yf60dl9zlL200205TS9571qI9Walng5i02+0xxer8c4A7TLH6mk4lGEhws1XiUqcMb0961dXvKOUTASGRiqODCJUZFQg2B6b6vUddxpn35q/M94PIgKLI9CfYxKgBxBFU0CEGct5tfWKTA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=i9FHPIFB; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="i9FHPIFB" Received: by mail.gandi.net (Postfix) with ESMTPSA id 911331BF20D; Fri, 5 Apr 2024 15:02:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/Ysm4DbzpqSZj84XzesirmTyGQsD5pPgqx8ZXriQXW0=; b=i9FHPIFB1bOTuAZcGIoU/ftnZ1SVa2TEZ4z60oYsvn9aHVv/Uk4SbpUmrq1vaMA8ZmrVtJ LU6OEAASLKMZu8HWnEztddFvjSLGMUJ5nEvF/SegcCPd4tYZd+GP1bN/OV0jwEVOxhiWG5 g+judT4b4OySqJnJBIYLbaDgHcEG0O7Al9MDknvb7npfUcN2pfUskWYfoVKg7LHJ4Wr8Ia 5xpKHPgynaNhpZrfvygj3Uzzg0+/NQJV6JL9xpPg2oR80MCFtGZpKEMznlXnD3zoEwUZzo UauH5cs5bCB8SWHnDVQ6qN6FHh3SpBXn1hGonj7YtDH//eWGJLEI4OZ3YPkXDg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:20 +0200 Subject: [PATCH v2 10/11] MIPS: mobileye: eyeq5: Add SPI-NOR controller node Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-10-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Add Cadence Quad SPI controller node to EyeQ5 SoC devicetree. Octal is supported. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 8d4f65ec912d..1543c2b9bcb6 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -158,6 +158,21 @@ timer { clocks = <&core0_clk>; }; }; + + ospi: spi@2100000 { + compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor"; + reg = <0 0x2100000 0x0 0x1000>, + <0 0x10000000 0x0 0x8000000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clocks = <&clocks EQ5C_DIV_OSPI>; + assigned-clock-rates = <167000000>; + #address-cells = <1>; + #size-cells = <0>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + }; }; }; From patchwork Fri Apr 5 15:02:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 13619179 Received: from relay8-d.mail.gandi.net (relay8-d.mail.gandi.net [217.70.183.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E492C171672; Fri, 5 Apr 2024 15:02:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329347; cv=none; b=AymI9QPRinGg3y+wcG0pkG+Nft5HMhhGpsTc/TBLf6h5SA1nSLP9vSY08JpQ+7CdkBXDfxkgJvSRKnz1mTTvfs2VhwJK14fr2SVaEzSxxYn0GAtCDs4aKaQUQH/97KNgIAmEAsvzxres+ClPlpXcghqhVtHW5pdCpEo3RvGd4bQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712329347; c=relaxed/simple; bh=F/9Yanst1hBH0HDc3LX9DP2jVFZb4lsc+NgoZKuU+jU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RhatQ+LEVZIc7eS9AB6tzkK8ctWmjSef3U+NofL1VyXNkvYjP5nZJ7TKxyHyLRhsGW1QjE1hOVC6IZiS5sp1IRWLZr7WzpWRPajSdFArgihjuuISe2S+KfoNBva5i4NWMFIAZWaKsTfZgTBsDShDyXIZ+uvYFnTuzKsOSbAWPtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=GIQs3hGh; arc=none smtp.client-ip=217.70.183.201 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="GIQs3hGh" Received: by mail.gandi.net (Postfix) with ESMTPSA id 25F8A1BF203; Fri, 5 Apr 2024 15:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1712329343; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0sXwCu/pnKjPhnbG0qZ+rGnft7Ztmr1z9mGamghTqGc=; b=GIQs3hGhLcuP+LdHR2rHZwIM/h0pDqFkngfYPjRM4qN38clW0VZH1RY71AeNvym1gp0iHF AdGrHLOKsX8l4ExSEN2GE+2NGIAicp/wtBPysSxWb8b7z579/6Lnp4nh95+tbESLMdHkXG 2U6sIv86k8mLgtoH6CDFfVXFP/3qtSFA7X7+Zgj4GxNzw2+/GaV13N7j6bj54IHfzqKOQn 3KPuyd1WiUVN7KTIgoexeLSpWMAr5iQp4SPyAkN30u7sFSsEJr3XfJxYSAG8140LeSSKL1 FnpkfHRUXXTL3+Y0JgkPUuwHd5u7QImghRtHvkBjsgBWUJ0RUrzaus/37+rh3g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Fri, 05 Apr 2024 17:02:21 +0200 Subject: [PATCH v2 11/11] MIPS: mobileye: eyeq5: add octal flash node to eval board DTS Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-cdns-qspi-mbly-v2-11-956679866d6d@bootlin.com> References: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> In-Reply-To: <20240405-cdns-qspi-mbly-v2-0-956679866d6d@bootlin.com> To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vaishnav Achath , Thomas Bogendoerfer , Rob Herring Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org, Vladimir Kondratiev , Gregory CLEMENT , Thomas Petazzoni , Tawfik Bayouk , =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.13.0 X-GND-Sasl: theo.lebrun@bootlin.com Add SPI-NOR octal flash node to evaluation board devicetree. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts index 6898b2d8267d..0e5fee7b680c 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -21,3 +21,18 @@ memory@0 { <0x8 0x02000000 0x0 0x7E000000>; }; }; + +&ospi { + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; /* chip select */ + + spi-max-frequency = <40000000>; + spi-rx-bus-width = <8>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <400>; + cdns,tsd2d-ns = <400>; + cdns,tchsh-ns = <125>; + cdns,tslch-ns = <50>; + }; +};