From patchwork Sat Apr 6 11:21:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13619784 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2063AC67861 for ; Sat, 6 Apr 2024 11:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/I0aWIUb8Y/t8WFWL2X9X3187Ce/9i+WQIj/bkr3CgM=; b=3hhJUMltBscjql u/INmp2rpmqa+iEH7FJqJ7G1gNNpU8VUYutyVqFxEB7FkSnhonQ0gd0B8zup8uT7rLJnYM2RluUDN 9BN2ildiNYoHZS4bj3XkOzGDNcaEEwM3G5aOsBdAuE8+QnmNmhlx7GsQ/mzqH/gKvrCGLkMZ/0058 s7EZbP37a86a4TfWcozbBRCUqa5A03KX/YofPbZKleud5EusvyqGXhObgDyjh6mFQwq0mOyFhvkpC jwmMEzKHXfRwvyCR4ZmQLhjDRaCyPxUcL9wjsGfsWtw5NjS9p6OWTPRxlKx2++nbdOhx+6np/jp/u MVQ5wdVvXCzA/4ealn2g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KT-0000000ADfD-3gNW; Sat, 06 Apr 2024 11:35:25 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KR-0000000ADe5-1fRy for linux-riscv@lists.infradead.org; Sat, 06 Apr 2024 11:35:24 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id C1DD760B2C; Sat, 6 Apr 2024 11:35:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC128C433F1; Sat, 6 Apr 2024 11:35:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712403322; bh=pFynrsYJOJ+5eJpGClthQv/4eVfcqNbrm44H7lrcyi4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O4CTEJzKCq0QwjZWEpBOFtuASv2SkLVYz3MRBuGvJ/ReH8U04k7rSV78aUSwyEF2T EUk5pA29fS13562QJZU0NtHAGQ32uu7l+DdUSlHiC1D+AV2dDvxTqf/7g1KaIykefB 65cui7Iijh+o2G8aJgRr9JLhvMFEmpDebc5+nGBwGM5ERDP9THwjgohpHVKObDK1hM SLtq9iGP9iLvceLdcxMPnFgQxvbpaLgTy6D1BadHVFetf+Fr8y178JZ0n1gvso++l5 RsW7Aiz79I7Bt0nyO44hKEruFP401sfXpPxcA7tzx0JVRznNJb1XiceDWr/DA/luOQ nT1hhTtWK7M1Q== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] riscv: nommu: remove PAGE_OFFSET hardcoding Date: Sat, 6 Apr 2024 19:21:57 +0800 Message-ID: <20240406112159.1634-2-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org> References: <20240406112159.1634-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240406_043523_523294_7AA9BC60 X-CRM114-Status: UNSURE ( 9.19 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Currently, PAGE_OFFSET is hardcoded as 0x8000_0000, it works fine since there's only one nommu platform in the mainline. However, there are many cases where the (S)DRAM base address isn't 0x8000_0000, so remove the hardcoding value, and introduce DRAM_BASE which will be set by users during configuring. DRAM_BASE is 0x8000_0000 by default. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7895c77545f1..b4af1df86352 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -247,10 +247,16 @@ config MMU Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'. +if !MMU +config DRAM_BASE + hex '(S)DRAM Base Address' + default 0x80000000 +endif + config PAGE_OFFSET hex default 0xC0000000 if 32BIT && MMU - default 0x80000000 if !MMU + default DRAM_BASE if !MMU default 0xff60000000000000 if 64BIT config KASAN_SHADOW_OFFSET From patchwork Sat Apr 6 11:21:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13619786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EA5CCD1292 for ; Sat, 6 Apr 2024 11:35:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=0PFt1fqhA7NXGKO/x982oMu7MyCLh6Lw5VnsZX7Mcr8=; b=44h64dFFwpPnvd T4B6wmlUYLkCnvB5lNxtey5IUgH9+/wCcrlgqh9nKAfXJXlsRk1dogENRK5L02Mm9N3Io+zjXF2xI RnuYscjtDTFEq63iNoxwgtAt4C0ESAYQdAAWrLjwMhwblMAQ6/LUzTmZl9g1gHd9l5DuFJHBIGXiE W/Q0n41zdOqetZ5sHWmFrpVhKXXS0anMQZ30szZqLg9gswkJLCM9chO4b3ZfGty4NI68Gzr54MZP8 y1DMx4Us7DdnCroYqxpX2WVaJaEHviDxFueA1MXe8OgqNp4fymcKMDCDHPfaP2MYHhnJcs9NDKO6T pPm1UedAjqaI5aJhPdoA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KV-0000000ADfe-2lr2; Sat, 06 Apr 2024 11:35:27 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KT-0000000ADei-1tsS for linux-riscv@lists.infradead.org; Sat, 06 Apr 2024 11:35:26 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id EF37660B2C; Sat, 6 Apr 2024 11:35:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0E50C43390; Sat, 6 Apr 2024 11:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712403324; bh=P4a9KYACvIIRNW48O2VQT45jjUsOBcQvvKsYyjPbY5g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l0ZeV5ZCLAozcfubDL9o5rFOQR1+aqsnMrGjnK5RkVMi0AK653WLvHm9FWjD/3bV/ GPIq9K7BruLtMize8NP++CRewTgdCOYYrG1bwdb5C4b7yp2cZWVeKE9IxEW28tF9ks +9zW/QLnp5L6aGIUzIGEG2u7p6tnOMILYYL6VkJpFjTCw1WIjg1mPnaM5Z8f2dKMEp jf8yyeH8Tl9kLVRkhzK7zP4/byvejzsoROKUU92Ov8UXN90YAN3QgbsvOkkQ837gMO wSNXf4iTIpSdqVHhRnZoCNcwayoaG02MA6ydDoLRTKYLIszGRljPd3aksEK7B+EkTz ADbyryrsZY0yw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] clocksource/drivers/timer-clint: Add option to use CSR instead of mtime Date: Sat, 6 Apr 2024 19:21:58 +0800 Message-ID: <20240406112159.1634-3-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org> References: <20240406112159.1634-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240406_043525_625755_177620A1 X-CRM114-Status: GOOD ( 16.62 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer: add a quirk for lacking mtime register") of opensbi: "T-Head developers surely have a different understanding of time CSR and CLINT's mtime register with SiFive ones, that they did not implement the mtime register at all -- as shown in openC906 source code, their time CSR value is just exposed at the top of their processor IP block and expects an external continous counter, which makes it not overrideable, and thus mtime register is not implemented, even not for reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS extended CSR, these systems still rely on the mtimecmp registers to generate timer interrupts. This makes it necessary to implement T-Head C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing reading mtime register and falls back to default code that reads time CSR." To use the clint in RISCV-M NOMMU env on Milkv Duo little core, we need to fall back to read time CSR instead of mtime register. Add the option for this purpose. Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/timex.h | 6 +++--- drivers/clocksource/Kconfig | 9 +++++++++ drivers/clocksource/timer-clint.c | 7 +++++++ 3 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h index a06697846e69..1c3eed4263cd 100644 --- a/arch/riscv/include/asm/timex.h +++ b/arch/riscv/include/asm/timex.h @@ -10,7 +10,7 @@ typedef unsigned long cycles_t; -#ifdef CONFIG_RISCV_M_MODE +#if defined(CONFIG_RISCV_M_MODE) && !defined(CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME) #include @@ -46,7 +46,7 @@ static inline unsigned long random_get_entropy(void) } #define random_get_entropy() random_get_entropy() -#else /* CONFIG_RISCV_M_MODE */ +#else /* CONFIG_RISCV_M_MODE && !CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */ static inline cycles_t get_cycles(void) { @@ -60,7 +60,7 @@ static inline u32 get_cycles_hi(void) } #define get_cycles_hi get_cycles_hi -#endif /* !CONFIG_RISCV_M_MODE */ +#endif /* !CONFIG_RISCV_M_MODE || CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */ #ifdef CONFIG_64BIT static inline u64 get_cycles64(void) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 34faa0320ece..7bbdbf2f96a8 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -650,6 +650,15 @@ config CLINT_TIMER This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. +config CLINT_USE_CSR_INSTEADOF_MTIME + bool "Use TIME CSR instead of the mtime register" + depends on CLINT_TIMER + help + Use TIME CSR instead of mtime register. Enable this option if + prefer TIME CSR over MTIME register, or if the implementation + doesn't implement the mtime register in CLINT, so fall back on + TIME CSR. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index f468fa8bf5f0..0d3890e00b75 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -76,6 +76,12 @@ static void clint_ipi_interrupt(struct irq_desc *desc) #define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1) #endif +#ifdef CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME +static u64 notrace clint_get_cycles64(void) +{ + return get_cycles64(); +} +#else #ifdef CONFIG_64BIT static u64 notrace clint_get_cycles64(void) { @@ -94,6 +100,7 @@ static u64 notrace clint_get_cycles64(void) return ((u64)hi << 32) | lo; } #endif /* CONFIG_64BIT */ +#endif /* CONFIG_CLINT_USE_CSR_INSTEADOF_MTIME */ static u64 clint_rdtime(struct clocksource *cs) { From patchwork Sat Apr 6 11:21:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 13619787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7B9EC67861 for ; Sat, 6 Apr 2024 11:35:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Yjzo1BvZVsQXjy9/EjDk4De7ehXMfNSr8JPvf4XFZLg=; b=4tdJgdYXSYk9OG AdHvFmp4XybYPVFGdLX3LoOVx+C7lrAETuX1VNEcLgpy6GXvUSXgeVVpQxtfX35GyGOZNhjX4tcNq yBycsoykWaKejszyWb3IR0rD1Ah1TW//4hczXK8MVz55R8yG/xKZaBo5lto5/bpccICFoZkeS2Zii myfPdXeW2fzTjTtUf2uD0ThXr6f233QbXFzNrrPGofXK46yBgJQXg+nB282fzQyG8ywJS/0AAZ4pm IlGyCaO4dAFAyS2g132IPdqRNWf11Wk/SXOxQHKftXJBRyWMdYuWe8JAMOzeOHJJuxEbbT5LQPTqc eMRy3d0btiGjc065zGUA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KY-0000000ADh8-2g3E; Sat, 06 Apr 2024 11:35:30 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rt4KV-0000000ADff-3xHp for linux-riscv@lists.infradead.org; Sat, 06 Apr 2024 11:35:29 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 5A85260B4F; Sat, 6 Apr 2024 11:35:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DD54C433C7; Sat, 6 Apr 2024 11:35:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712403326; bh=R97Q2QZSx04EEg2PLja5HX11nqpX6+6Z/tNLhIWtFfk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GBDDrChk1RUq4DtnWONvFCFXv1lrG6pW0ZHR2l8oUKM0hzrs63WR0FLoz0PP9FwEB fUzdWpR9hmpGQAl/Jc94fGxDJRBr6VNV9g/FVmcXpYcEjVHpXlBOKXGBf2KhgfNbwd 2mGvpKF/07K0hb1i2zLkobtmewHREGYShNg3IfLOUpYI5a0cwPfV0vSBgFg7CO3TLa 5E4HPquhMzxBoAxRlOvzr4A/pHviHN5HPHwaOzxeo1u4ihNyKjf/SNfxHiHEzklIf0 fUlWKp5vYZ9Pbh05QW2A/5xEY1ARe9jicwbtDx43kWjHuNqJnvti9S2skkgT5foVJG +Ip4WtUlN8iZw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Samuel Holland Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] clocksource/drivers/timer-clint: Add T-Head C9xx clint Date: Sat, 6 Apr 2024 19:21:59 +0800 Message-ID: <20240406112159.1634-4-jszhang@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240406112159.1634-1-jszhang@kernel.org> References: <20240406112159.1634-1-jszhang@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240406_043528_088734_4D955775 X-CRM114-Status: GOOD ( 10.27 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The mtimecmp in T-Head C9xx clint only supports 32bit read/write, implement such support. Signed-off-by: Jisheng Zhang --- drivers/clocksource/timer-clint.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 0d3890e00b75..655ea81071ff 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -39,6 +39,7 @@ static u64 __iomem *clint_timer_cmp; static u64 __iomem *clint_timer_val; static unsigned long clint_timer_freq; static unsigned int clint_timer_irq; +static bool is_c900_clint; #ifdef CONFIG_RISCV_M_MODE u64 __iomem *clint_time_val; @@ -135,6 +136,19 @@ static int clint_clock_shutdown(struct clock_event_device *evt) return 0; } +static int c900_clint_clock_next_event(unsigned long delta, + struct clock_event_device *ce) +{ + void __iomem *r = clint_timer_cmp + + cpuid_to_hartid_map(smp_processor_id()); + u64 val = clint_get_cycles64() + delta; + + csr_set(CSR_IE, IE_TIE); + writel_relaxed(val, r); + writel_relaxed(val >> 32, r + 4); + return 0; +} + static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { .name = "clint_clockevent", .features = CLOCK_EVT_FEAT_ONESHOT, @@ -148,6 +162,9 @@ static int clint_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); + if (is_c900_clint) + ce->set_next_event = c900_clint_clock_next_event; + ce->cpumask = cpumask_of(cpu); clockevents_config_and_register(ce, clint_timer_freq, 100, ULONG_MAX); @@ -291,5 +308,12 @@ static int __init clint_timer_init_dt(struct device_node *np) return rc; } +static int __init c900_clint_timer_init_dt(struct device_node *np) +{ + is_c900_clint = true; + return clint_timer_init_dt(np); +} + TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt); +TIMER_OF_DECLARE(clint_timer2, "thead,c900-clint", c900_clint_timer_init_dt);