From patchwork Sat Feb 23 02:39:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10827217 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 58D7814E1 for ; Sat, 23 Feb 2019 02:41:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D0CE31F4A for ; Sat, 23 Feb 2019 02:41:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EC2D31F72; Sat, 23 Feb 2019 02:41:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A94C231F4A for ; Sat, 23 Feb 2019 02:41:33 +0000 (UTC) Received: from localhost ([127.0.0.1]:60041 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNFs-00044X-5y for patchwork-qemu-devel@patchwork.kernel.org; Fri, 22 Feb 2019 21:41:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNER-0002us-HR for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:04 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNEQ-0002UM-OO for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:03 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35919) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNEQ-0002TJ-Gz for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:02 -0500 Received: by mail-pg1-x543.google.com with SMTP id r124so1939050pgr.3 for ; Fri, 22 Feb 2019 18:40:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hO9tI0gl+7v0EEROptE0nDBUbXhf6NtyQAL92HWtEUU=; b=NIr/tER7mzZqZwnnkYCMxNMPtpOBmMKHL7ZIFR1IOIWMqJnj+2HZiVJa0/ngZO6ioU WNLz/nTFrxcakbARY/6jfLWhYkxFpJBoZMc/2VMfcjsGikWyrTbmJ/7os4oPgegH1jDd BlDs20+fDhL5GMBjmxnZQr2hslIZC55w0IvMgFwCEZPHRVeOicgxPV9hXjExIVn2mijB 5GhIoLau/S42K5PEzMMAMOMfyI5qHoPJC7xwex2g4ymKANwceoU6DXeaHs3S/Xx375wF myIAOwY4J20bxu8GCaMxEdia8g+tlDQI/EoFOUnFRwWKU834ZfcdN400bwkltn4HHFjC srMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hO9tI0gl+7v0EEROptE0nDBUbXhf6NtyQAL92HWtEUU=; b=PXv6RBTICtaJ8U6tJKxU9GZ1RERkcyHbuVWLescvqyij1yqgqIBGVMB3CXyEbQqoV1 3FvV7qc5coj3GyWDsrHdUvwPspqychjxVwe01qMrKBC9Gg9TXUHblIuvIfuFiSm6lEfW Oi2IPZwLxTUtKYtHg4fcZ/S81jBvo08tUUd3H+f65CkqksDGnwH0wUDSzp/EnYPPdDZm fMldboiSr9BLnfgsFp4VyiTOCfFxhSTrSZ/Sf3yQGF443LWxg0kj0qlSUkIhLXE0GUzZ VEwbHPsRlwZnhOOud4uSMu5CKIE54dm0QnQbwKP7C8rul0Sjj4Gulik+XwFF1OI3eq/y bfRQ== X-Gm-Message-State: AHQUAuZK+whCFePfBWhLO+AE+dNbAe2tZdFrBW/+PY05aM/OfRsrkPDG ikSUH71Xmn8k6tlN/gHeo0i1CljvKzs= X-Google-Smtp-Source: AHgI3IaXjxlZ6A8N7Rt62U+XuhzU409Z41H0NCYWlq1f0M/2YVMShxeiOoXruRrh3/nGqhqH8k97DQ== X-Received: by 2002:a63:f806:: with SMTP id n6mr6877471pgh.19.1550889601116; Fri, 22 Feb 2019 18:40:01 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.39.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:52 -0800 Message-Id: <20190223023957.18865-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 1/6] target/arm: Implement ID_PFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This was defined at some point before ARMv8.4, and will shortly be used by new processor descriptions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 84ae6849c2..c57f8e9ba8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -863,6 +863,7 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; + uint32_t id_pfr2; uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; diff --git a/target/arm/helper.c b/target/arm/helper.c index a018eb23fe..8903cc13d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6092,10 +6092,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, - { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_PFR2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->id_pfr2 }, { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST, From patchwork Sat Feb 23 02:39:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10827225 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 470F714E1 for ; Sat, 23 Feb 2019 02:44:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 24ACE1FF41 for ; Sat, 23 Feb 2019 02:44:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F35B431FCA; Sat, 23 Feb 2019 02:44:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5EFFD1FF41 for ; Sat, 23 Feb 2019 02:44:07 +0000 (UTC) Received: from localhost ([127.0.0.1]:60061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNIM-0005ty-OW for patchwork-qemu-devel@patchwork.kernel.org; Fri, 22 Feb 2019 21:44:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:55614) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gxNET-0002v3-7Q for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gxNER-0002WT-UQ for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:05 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:41976) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gxNER-0002V6-Nc for qemu-devel@nongnu.org; Fri, 22 Feb 2019 21:40:03 -0500 Received: by mail-pf1-x433.google.com with SMTP id d25so1919002pfn.8 for ; Fri, 22 Feb 2019 18:40:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G4evj0XBLDZtPvZuW0tTZFLLxSmrGZzJJB60I33Ox90=; b=Cei4nqcMlXReg0NZz6LP4eVjvgqqRPx3au3dW1dHUxJ4MsOuPa1MfcZVv43YDYkD2X dckgvsV0oeE7tvgiD912AWbjqWI9smJd4OnDj4VoTlFPygazdUiOt2seSdURF+gSF9QF f35kXzR663FoozOp6HgmpvMLzZkOLD0fPa5WX7QLKEqgVyx2IMoW3FfTVHt8UGXHqlgA ESHE2xFQzqa7lC44hW5ilPq5fwx4y4IKnkdoR7x/nGp5F2qF26H6r9j3hI4SHZ8i3Fsf /5Df8fAEubH3KTo/g3E94Lxie6JZDriTdDKuirmTMqAqrQrLCudjROR9xh13c1AP/sDF UUFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G4evj0XBLDZtPvZuW0tTZFLLxSmrGZzJJB60I33Ox90=; b=FDmXsQCIxae5lqIqrf8sKjbymiBU9IxjRdNvDDVeUK5z7iwtIUSb/M3j4bBA6WQGU8 M4CGg8pQTga45Dt0YNGemKoE96JomAiT12VDmBlNL0dpXyFtREGt4/pwjwdDbEizF5SD 8htr+zxwEQr8HEkWeiBamlehiPiGhQaEU4fB2LsKYPjRVD9if+6+utM87rrU9GkdIKBt MNbit4SXE2zaTijn5skLniAXaf4bPYj6ByZl/6jwtp3/8ODANE8aeHiuWKaGKjNGbvP4 WfHB7rAPH/cMGYtTPJ1TIIFVDuelKxAF9aq+bwbol1oRB1outKi8GhzRrcjE5ImOhWe+ lBQw== X-Gm-Message-State: AHQUAuZGOINTNM5uDPTSYNCqn7ZzCpWY7uMpqxLllgsfyTvlP2F6K0lZ HbXBCrFAGRliiR531o853lz0JiaFUaI= X-Google-Smtp-Source: AHgI3IbxCFimmsR9dh4/SlDfkXxtcrwA3fOP/kC9bxkszMj2H8cTq+uQgwRwjvyQ1nO6ZEQ/Fs9tyQ== X-Received: by 2002:a65:5301:: with SMTP id m1mr6739860pgq.90.1550889602261; Fri, 22 Feb 2019 18:40:02 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-188-82.tukw.qwest.net. [97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:53 -0800 Message-Id: <20190223023957.18865-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::433 Subject: [Qemu-devel] [PATCH 2/6] target/arm: Define cortex-a73 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP There are new field definitions, CSV2 and CSV3, that do not yet appear in the main ARM ARM. Define the ID_AA64PF0 versions, since we already define the rest of those bits. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ hw/arm/virt.c | 1 + target/arm/cpu64.c | 63 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 62 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c57f8e9ba8..c2899f0bed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1694,6 +1694,8 @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4) FIELD(ID_AA64PFR0, GIC, 24, 4) FIELD(ID_AA64PFR0, RAS, 28, 4) FIELD(ID_AA64PFR0, SVE, 32, 4) +FIELD(ID_AA64PFR0, CSV2, 56, 4) +FIELD(ID_AA64PFR0, CSV3, 60, 4) FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 99c2b6e60d..c69a734878 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -173,6 +173,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..d34aa3af75 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -51,7 +51,8 @@ static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) } #endif -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { +/* These extra registers are used by (most of?) the cortex-a* series. */ +static const ARMCPRegInfo cortex_aXX_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, @@ -149,7 +150,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void aarch64_a53_initfn(Object *obj) @@ -203,7 +204,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void aarch64_a72_initfn(Object *obj) @@ -255,7 +256,60 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs = 4; cpu->gic_vpribits = 5; cpu->gic_vprebits = 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + +static void aarch64_a73_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a73"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr = 0x411fd090; + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x41034091; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x12111111; + cpu->isar.mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; + cpu->reset_sctlr = 0x00c50838; + cpu->id_pfr0 = 0x00010131; + cpu->id_pfr1 = 0x00011011; + cpu->id_pfr2 = 0x00000001; + cpu->id_dfr0 = 0x03010066; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02102211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_aa64pfr0 = 0x1100000000002222ull; + cpu->id_aa64dfr0 = 0x10305106; + cpu->isar.id_aa64isar0 = 0x00011120; + cpu->isar.id_aa64mmfr0 = 0x00101122; + cpu->dbgdidr = 0x3516d000; + cpu->clidr = 0x0a200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, @@ -378,6 +432,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, + { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } }; From patchwork Sat Feb 23 02:39:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10827219 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F4356C2 for ; Sat, 23 Feb 2019 02:41:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0C4F31F4A for ; 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X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 3/6] target/arm: Implement ID_AA64MMFR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This was res0 before ARMv8.2, but will shortly be used by new processor definitions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 2 ++ 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c2899f0bed..02642a7db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -855,6 +855,7 @@ struct ARMCPU { uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; + uint64_t id_aa64mmfr2; } isar; uint32_t midr; uint32_t revidr; @@ -1724,6 +1725,20 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4) FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) +FIELD(ID_AA64MMFR2, CNP, 0, 4) +FIELD(ID_AA64MMFR2, UAO, 4, 4) +FIELD(ID_AA64MMFR2, LSM, 8, 4) +FIELD(ID_AA64MMFR2, IESB, 12, 4) +FIELD(ID_AA64MMFR2, VARANGE, 16, 4) +FIELD(ID_AA64MMFR2, CCIDX, 20, 4) +FIELD(ID_AA64MMFR2, NV, 24, 4) +FIELD(ID_AA64MMFR2, ST, 28, 4) +FIELD(ID_AA64MMFR2, AT, 32, 4) +FIELD(ID_AA64MMFR2, IDS, 36, 4) +FIELD(ID_AA64MMFR2, FWB, 40, 4) +FIELD(ID_AA64MMFR2, TTL, 48, 4) +FIELD(ID_AA64MMFR2, BBM, 52, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8903cc13d8..fbdca9324b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6052,10 +6052,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->isar.id_aa64mmfr1 }, - { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64mmfr2 }, { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e3ba149248..c3d421b53b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -542,6 +542,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, ARM64_SYS_REG(3, 0, 0, 7, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2, + ARM64_SYS_REG(3, 0, 0, 7, 2)); /* * Note that if AArch32 support is not present in the host, From patchwork Sat Feb 23 02:39:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10827223 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0E20714E1 for ; Sat, 23 Feb 2019 02:41:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF83E31F4A for ; Sat, 23 Feb 2019 02:41:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E40A631F72; Sat, 23 Feb 2019 02:41:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7E7A231F4A for ; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:55 -0800 Message-Id: <20190223023957.18865-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [RFC 4/6] target/arm: Define cortex-a75 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c69a734878..06a155724c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -174,6 +174,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), + ARM_CPU_TYPE_NAME("cortex-a75"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d34aa3af75..325e0ecf17 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -312,6 +312,63 @@ static void aarch64_a73_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } +static void aarch64_a75_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a75"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr = 0x413fd0a1; + cpu->revidr = 0x00000000; + cpu->reset_fpsid = 0x410340a2; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + cpu->ctr = 0x84448004; + cpu->reset_sctlr = 0x00c50838; /* ??? can't find it in a75 trm */ + cpu->id_pfr0 = 0x00010131; + cpu->id_pfr1 = 0x00011011; + cpu->id_pfr2 = 0x00000001; + cpu->id_dfr0 = 0x04010088; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_aa64pfr0 = 0x1100000010112222ull; + cpu->id_aa64dfr0 = 0x10305408; + cpu->isar.id_aa64isar0 = 0x10211120; + cpu->isar.id_aa64isar1 = 0x00100001; + cpu->isar.id_aa64mmfr0 = 0x00101124; + cpu->isar.id_aa64mmfr1 = 0x10212122; + cpu->isar.id_aa64mmfr2 = 0x00001011; + cpu->dbgdidr = 0x3518d000; + cpu->clidr = 0x08200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -433,6 +490,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, + { .name = "cortex-a75", .initfn = aarch64_a75_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } }; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:56 -0800 Message-Id: <20190223023957.18865-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [RFC 5/6] target/arm: Conditionalize DBGDIDR vs ID_AA64DFR0_EL1 assert X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Only perform the assert when both registers exist. Extract the variables from ID_AA64DFR0_EL1 for AArch64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++++++++++++---------------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fbdca9324b..1d8c8998c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5544,32 +5544,50 @@ static void define_debug_regs(ARMCPU *cpu) /* Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ - int i; - int wrps, brps, ctx_cmps; - ARMCPRegInfo dbgdidr = { - .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, - .access = PL0_R, .accessfn = access_tda, - .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, - }; + int i, wrps, brps, ctx_cmps; + bool have_aa32; - /* Note that all these register fields hold "number of Xs minus 1". */ - brps = extract32(cpu->dbgdidr, 24, 4); - wrps = extract32(cpu->dbgdidr, 28, 4); - ctx_cmps = extract32(cpu->dbgdidr, 20, 4); - - assert(ctx_cmps <= brps); - - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties + /* + * The DBGDIDR and ID_AA64DFR0_EL1 define various properties * of the debug registers such as number of breakpoints; * check that if they both exist then they agree. + * + * Note that all these register fields hold "number of Xs minus 1". */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); - } + brps = extract32(cpu->id_aa64dfr0, 12, 4); + wrps = extract32(cpu->id_aa64dfr0, 20, 4); + ctx_cmps = extract32(cpu->id_aa64dfr0, 28, 4); - define_one_arm_cp_reg(cpu, &dbgdidr); + /* + * There are cpus with aarch32 only at EL0, and which do not + * have the 32-bit system registers. + */ + have_aa32 + = (FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL2) >= 2 || + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3) >= 2); + if (have_aa32) { + assert(extract32(cpu->dbgdidr, 24, 4) == brps); + assert(extract32(cpu->dbgdidr, 28, 4) == wrps); + assert(extract32(cpu->dbgdidr, 20, 4) == ctx_cmps); + } + } else { + have_aa32 = true; + brps = extract32(cpu->dbgdidr, 24, 4); + wrps = extract32(cpu->dbgdidr, 28, 4); + ctx_cmps = extract32(cpu->dbgdidr, 20, 4); + } + assert(ctx_cmps <= brps); + + if (have_aa32) { + ARMCPRegInfo dbgdidr = { + .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, + .opc1 = 0, .opc2 = 0, .access = PL0_R, .accessfn = access_tda, + .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } define_arm_cp_regs(cpu, debug_cp_reginfo); if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { From patchwork Sat Feb 23 02:39:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 10827229 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D4B886C2 for ; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id j6sm3052513pgq.33.2019.02.22.18.40.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Feb 2019 18:40:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 22 Feb 2019 18:39:57 -0800 Message-Id: <20190223023957.18865-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190223023957.18865-1-richard.henderson@linaro.org> References: <20190223023957.18865-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b Subject: [Qemu-devel] [RFC 6/6] target/arm: Define cortex-a76 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Richard Henderson --- hw/arm/virt.c | 1 + target/arm/cpu64.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 06a155724c..4495ce8918 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -175,6 +175,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a73"), ARM_CPU_TYPE_NAME("cortex-a75"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 325e0ecf17..4a92d7656a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -369,6 +369,63 @@ static void aarch64_a75_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); } +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_VFP4); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* + * Note that the A76 only supports AA32 at EL0, so the + * AA32-only EL1 id registers do not exist. + */ + cpu->midr = 0x413fd0b1; + cpu->revidr = 0x00000000; + cpu->ctr = 0x8444C004; + cpu->reset_sctlr = 0x30d50838; + cpu->id_pfr0 = 0x10010131; + cpu->id_pfr1 = 0x10010000; + cpu->id_pfr2 = 0x00000011; + cpu->id_dfr0 = 0x04010088; + cpu->id_afr0 = 0x00000000; + cpu->id_mmfr0 = 0x10201105; + cpu->id_mmfr1 = 0x40000000; + cpu->id_mmfr2 = 0x01260000; + cpu->id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00011142; + cpu->isar.id_isar5 = 0x00011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; + cpu->id_aa64dfr0 = 0x10305408; + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; + cpu->isar.id_aa64isar1 = 0x00100001; + cpu->isar.id_aa64mmfr0 = 0x00101122; + cpu->isar.id_aa64mmfr1 = 0x10212122; + cpu->isar.id_aa64mmfr2 = 0x00001011; + cpu->clidr = 0x08200023; + cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ + cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + define_arm_cp_regs(cpu, cortex_aXX_cp_reginfo); +} + static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -491,6 +548,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a73", .initfn = aarch64_a73_initfn }, { .name = "cortex-a75", .initfn = aarch64_a75_initfn }, + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, { .name = NULL } };