From patchwork Wed Apr 10 11:48:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624148 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59CB615AD9A; Wed, 10 Apr 2024 11:48:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749726; cv=none; b=C2gPwNQWBKhMM2/QjvjOpuCC3mtIdLNtRQ0rsqzGyb5kQTjJlESTtMF5T1dn3vxffzvZz8GSaptDewsmA0/yP9rUIRNj/tcTQAtQAhdSJyw/yDeKhTZjbarCfDHkg5c5OpNEJ9P6C25xpZu9WKrRqo5wQUnBgShf2aubVC87uqk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749726; c=relaxed/simple; bh=GqlGR0/bnyHHT0mMIB7cQ4ab2D9OvHonlB/nEngDxSk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mGcryLB8/FZYPAsuqugZaUr5MzwA8HWefktmRxwBSlnzQMbcoK94K/jE9bIcbUFfyvN4mZA2QQZoVEFQL+EQXa/LUCHmLu7ySsvFF4SwiZ0ObUXgDZBxvhiFJELppPCW7LuSIqiLvQc/qTMrPJHDs9NgFkZTZSEFg08NEDV0G+g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=RtiDgvFE; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="RtiDgvFE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712749725; x=1744285725; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GqlGR0/bnyHHT0mMIB7cQ4ab2D9OvHonlB/nEngDxSk=; b=RtiDgvFEWNCc4uLOUPNSSdujBbdbyKO6SoYcXcef/TfQkCXAL7AFYCB7 PInIcggoWAYUDRhMH/LBtPZwr8qxTbz//7TQKvhmAaKYbT3NVUxIsvOu+ 1Dkx+gmMWQWtU7HTPVEMPRBX/lMvMfmUUP9IbJRfCEoDQzBPhmwVLgPPW UPkXQmqbp3Wyr4L4LN8bqE3dyfTSRyywypzFNZzW9NEvsQycq02FEuRHP /oKhf36xWxt3ijNhJZgUCVfixyLibwukHxwnuyG2RjAf8Jywe3XoRUiLx lQAX9lYTXx1ePbCC0wVY2+Z8IfUyGILTxb0XEGCH/IB5/KZAmg3WZZq9H g==; X-CSE-ConnectionGUID: XQKVXGhvSP6w/FEZhv3smQ== X-CSE-MsgGUID: EZbm6cWxTP2Z4ora0CRA+A== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="11944060" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944060" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:48:44 -0700 X-CSE-ConnectionGUID: OiYQycsDQEWQMHuXWQWqAg== X-CSE-MsgGUID: bop2wKIVSHyYyRVO4W3TFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769241" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:48:36 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 01/11] x86/tsc: Add base clock properties in clocksource structure Date: Wed, 10 Apr 2024 17:18:18 +0530 Message-Id: <20240410114828.25581-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D Add base clock hardware abstraction in clocksource structure. Add clocksource ID for x86 ART(Always Running Timer). The newly added clocksource ID and conversion parameters are used to convert time in a clocksource domain to base clock and vice versa. Convert the base clock to the system clock using convert_base_to_cs() in get_device_system_crosststamp(). Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- arch/x86/kernel/tsc.c | 42 +++++++++++++++++++-------------- include/linux/clocksource.h | 27 +++++++++++++++++++++ include/linux/clocksource_ids.h | 1 + include/linux/timekeeping.h | 2 ++ kernel/time/timekeeping.c | 37 +++++++++++++++++++++++++++-- 5 files changed, 89 insertions(+), 20 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 5a69a49acc96..45bf2f6d0ffa 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -50,9 +50,9 @@ int tsc_clocksource_reliable; static int __read_mostly tsc_force_recalibrate; -static u32 art_to_tsc_numerator; -static u32 art_to_tsc_denominator; -static u64 art_to_tsc_offset; +static struct clocksource_base art_base_clk = { + .id = CSID_X86_ART, +}; static bool have_art; struct cyc2ns { @@ -1074,7 +1074,7 @@ core_initcall(cpufreq_register_tsc_scaling); */ static void __init detect_art(void) { - unsigned int unused[2]; + unsigned int unused; if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) return; @@ -1089,13 +1089,14 @@ static void __init detect_art(void) tsc_async_resets) return; - cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, - &art_to_tsc_numerator, unused, unused+1); + cpuid(ART_CPUID_LEAF, &art_base_clk.denominator, + &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); - if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) + art_base_clk.freq_khz /= KHZ; + if (art_base_clk.denominator < ART_MIN_DENOMINATOR) return; - rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); + rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); /* Make this sticky over multiple CPU init calls */ setup_force_cpu_cap(X86_FEATURE_ART); @@ -1303,13 +1304,13 @@ struct system_counterval_t convert_art_to_tsc(u64 art) { u64 tmp, res, rem; - rem = do_div(art, art_to_tsc_denominator); + rem = do_div(art, art_base_clk.denominator); - res = art * art_to_tsc_numerator; - tmp = rem * art_to_tsc_numerator; + res = art * art_base_clk.numerator; + tmp = rem * art_base_clk.numerator; - do_div(tmp, art_to_tsc_denominator); - res += tmp + art_to_tsc_offset; + do_div(tmp, art_base_clk.denominator); + res += tmp + art_base_clk.offset; return (struct system_counterval_t) { .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, @@ -1356,7 +1357,6 @@ struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) } EXPORT_SYMBOL(convert_art_ns_to_tsc); - static void tsc_refine_calibration_work(struct work_struct *work); static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); /** @@ -1458,8 +1458,10 @@ static void tsc_refine_calibration_work(struct work_struct *work) if (tsc_unstable) goto unreg; - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); unreg: clocksource_unregister(&clocksource_tsc_early); @@ -1484,8 +1486,10 @@ static int __init init_tsc_clocksource(void) * the refined calibration and directly register it as a clocksource. */ if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); clocksource_unregister(&clocksource_tsc_early); @@ -1509,10 +1513,12 @@ static bool __init determine_cpu_tsc_frequencies(bool early) if (early) { cpu_khz = x86_platform.calibrate_cpu(); - if (tsc_early_khz) + if (tsc_early_khz) { tsc_khz = tsc_early_khz; - else + } else { tsc_khz = x86_platform.calibrate_tsc(); + clocksource_tsc.freq_khz = tsc_khz; + } } else { /* We should not be here with non-native cpu calibration */ WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 0ad8b550bb4b..66a033bff17c 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -21,6 +21,7 @@ #include #include +struct clocksource_base; struct clocksource; struct module; @@ -48,6 +49,7 @@ struct module; * @archdata: Optional arch-specific data * @max_cycles: Maximum safe cycle value which won't overflow on * multiplication + * @freq_khz: Clocksource frequency in khz. * @name: Pointer to clocksource name * @list: List head for registration (internal) * @rating: Rating value for selection (higher is better) @@ -70,6 +72,8 @@ struct module; * validate the clocksource from which the snapshot was * taken. * @flags: Flags describing special properties + * @base: Hardware abstraction for clock on which a clocksource + * is based * @enable: Optional function to enable the clocksource * @disable: Optional function to disable the clocksource * @suspend: Optional suspend function for the clocksource @@ -105,12 +109,14 @@ struct clocksource { struct arch_clocksource_data archdata; #endif u64 max_cycles; + u32 freq_khz; const char *name; struct list_head list; int rating; enum clocksource_ids id; enum vdso_clock_mode vdso_clock_mode; unsigned long flags; + struct clocksource_base *base; int (*enable)(struct clocksource *cs); void (*disable)(struct clocksource *cs); @@ -306,4 +312,25 @@ static inline unsigned int clocksource_get_max_watchdog_retry(void) void clocksource_verify_percpu(struct clocksource *cs); +/** + * struct clocksource_base - hardware abstraction for clock on which a clocksource + * is based + * @id: Defaults to CSID_GENERIC. The id value is used for conversion + * functions which require that the current clocksource is based + * on a clocksource_base with a particular ID in certain snapshot + * functions to allow callers to validate the clocksource from + * which the snapshot was taken. + * @freq_khz: Nominal frequency of the base clock in kHz + * @offset: Offset between the base clock and the clocksource + * @numerator: Numerator of the clock ratio between base clock and the clocksource + * @denominator: Denominator of the clock ratio between base clock and the clocksource + */ +struct clocksource_base { + enum clocksource_ids id; + u32 freq_khz; + u64 offset; + u32 numerator; + u32 denominator; +}; + #endif /* _LINUX_CLOCKSOURCE_H */ diff --git a/include/linux/clocksource_ids.h b/include/linux/clocksource_ids.h index a4fa3436940c..2bb4d8c2f1b0 100644 --- a/include/linux/clocksource_ids.h +++ b/include/linux/clocksource_ids.h @@ -9,6 +9,7 @@ enum clocksource_ids { CSID_X86_TSC_EARLY, CSID_X86_TSC, CSID_X86_KVM_CLK, + CSID_X86_ART, CSID_MAX, }; diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 0ea7823b7f31..b2ee182d891e 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -310,10 +310,12 @@ struct system_device_crosststamp { * timekeeping code to verify comparability of two cycle values. * The default ID, CSID_GENERIC, does not identify a specific * clocksource. + * @use_nsecs: @cycles is in nanoseconds. */ struct system_counterval_t { u64 cycles; enum clocksource_ids cs_id; + bool use_nsecs; }; /* diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index b58dffc58a8f..2542cfefbdee 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1193,6 +1193,40 @@ static bool timestamp_in_interval(u64 start, u64 end, u64 ts) return false; } +static bool convert_clock(u64 *val, u32 numerator, u32 denominator) +{ + u64 rem, res; + + if (!numerator || !denominator) + return false; + + res = div64_u64_rem(*val, denominator, &rem) * numerator; + *val = res + div_u64(rem * numerator, denominator); + return true; +} + +static bool convert_base_to_cs(struct system_counterval_t *scv) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + u32 num, den; + + /* The timestamp was taken from the time keeper clock source */ + if (cs->id == scv->cs_id) + return true; + + /* Check whether cs_id matches the base clock */ + if (!base || base->id != scv->cs_id) + return false; + + num = scv->use_nsecs ? cs->freq_khz : base->numerator; + den = scv->use_nsecs ? USEC_PER_SEC : base->denominator; + + convert_clock(&scv->cycles, num, den); + scv->cycles += base->offset; + return true; +} + /** * get_device_system_crosststamp - Synchronously capture system/device timestamp * @get_time_fn: Callback to get simultaneous device time and @@ -1238,8 +1272,7 @@ int get_device_system_crosststamp(int (*get_time_fn) * system counter value is the same as for the currently * installed timekeeper clocksource */ - if (system_counterval.cs_id == CSID_GENERIC || - tk->tkr_mono.clock->id != system_counterval.cs_id) + if (!convert_base_to_cs(&system_counterval)) return -ENODEV; cycles = system_counterval.cycles; From patchwork Wed Apr 10 11:48:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624149 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07EA915B553; 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a="11944083" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944083" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:48:50 -0700 X-CSE-ConnectionGUID: QJH6IMdpTXu2SncDEgABkw== X-CSE-MsgGUID: gDsYZPgtR2W7s9Z7JzU/NA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769245" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:48:43 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 02/11] e1000e: remove convert_art_to_tsc() Date: Wed, 10 Apr 2024 17:18:19 +0530 Message-Id: <20240410114828.25581-3-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/e1000e/ptp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c index bbcfd529399b..89d57dd911dc 100644 --- a/drivers/net/ethernet/intel/e1000e/ptp.c +++ b/drivers/net/ethernet/intel/e1000e/ptp.c @@ -124,7 +124,8 @@ static int e1000e_phc_get_syncdevicetime(ktime_t *device, sys_cycles = er32(PLTSTMPH); sys_cycles <<= 32; sys_cycles |= er32(PLTSTMPL); - *system = convert_art_to_tsc(sys_cycles); + system->cycles = sys_cycles; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Wed Apr 10 11:48:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624150 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 951F015B553; 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/igc/igc_ptp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 885faaa7b9de..39656489d73e 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -901,7 +901,11 @@ static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) { #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) - return convert_art_ns_to_tsc(tstamp); + return (struct system_counterval_t) { + .cs_id = CSID_X86_ART, + .cycles = tstamp, + .use_nsecs = true, + }; #else return (struct system_counterval_t) { }; #endif From patchwork Wed Apr 10 11:48:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624151 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 343FF2837B; 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 60283543ffc8..e73fa34237d3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -390,10 +390,11 @@ static int intel_crosststamp(ktime_t *device, *device = ns_to_ktime(ptp_time); read_unlock_irqrestore(&priv->ptp_lock, flags); get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); - *system = convert_art_to_tsc(art_time); + system->cycles = art_time; } system->cycles *= intel_priv->crossts_adj; + system->cs_id = CSID_X86_ART; priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; return 0; From patchwork Wed Apr 10 11:48:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624152 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B84D615B118; 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a="11944134" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944134" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:49:10 -0700 X-CSE-ConnectionGUID: CPy+j/t/T/aJT9389dDQcA== X-CSE-MsgGUID: 7d+OO9KrQT21fLhg+OKhiw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769266" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:03 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 05/11] ALSA: hda: remove convert_art_to_tsc() Date: Wed, 10 Apr 2024 17:18:22 +0530 Message-Id: <20240410114828.25581-6-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- sound/pci/hda/hda_controller.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 206306a0eb82..6f648fae7a7b 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -463,7 +463,8 @@ static int azx_get_sync_time(ktime_t *device, *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); - *system = convert_art_to_tsc(tsc_counter); + system->cycles = tsc_counter; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Wed Apr 10 11:48:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624153 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E51DF15B136; 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/ice/ice_ptp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index c11eba07283c..c416dd2e6622 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2116,7 +2116,8 @@ ice_ptp_get_syncdevicetime(ktime_t *device, hh_ts_lo = rd32(hw, GLHH_ART_TIME_L); hh_ts_hi = rd32(hw, GLHH_ART_TIME_H); hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo; - *system = convert_art_ns_to_tsc(hh_ts); + system->cycles = hh_ts; + system->cs_id = CSID_X86_ART; /* Read Device source clock time */ hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx)); hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx)); From patchwork Wed Apr 10 11:48:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624154 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F59915B130; 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a="11944167" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944167" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:49:23 -0700 X-CSE-ConnectionGUID: ECWwyE1WS4ymir9lvVJPHA== X-CSE-MsgGUID: X/WnJFf1QXe0ShB8ecEl8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769278" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:16 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 07/11] x86/tsc: Remove art to tsc conversion functions which are obsolete Date: Wed, 10 Apr 2024 17:18:24 +0530 Message-Id: <20240410114828.25581-8-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D The convert_art_to_tsc() and convert_art_ns_to_tsc() interfaces are no longer required. This conversion is internally done in get_device_system_crosststamp() using convert_base_to_cs(). Signed-off-by: Lakshmi Sowjanya D --- arch/x86/include/asm/tsc.h | 3 -- arch/x86/kernel/tsc.c | 60 -------------------------------------- 2 files changed, 63 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 405efb3e4996..94408a784c8e 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -28,9 +28,6 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles -extern struct system_counterval_t convert_art_to_tsc(u64 art); -extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); - extern void tsc_early_init(void); extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 45bf2f6d0ffa..5f0bd441ed4d 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1297,66 +1297,6 @@ int unsynchronized_tsc(void) return 0; } -/* - * Convert ART to TSC given numerator/denominator found in detect_art() - */ -struct system_counterval_t convert_art_to_tsc(u64 art) -{ - u64 tmp, res, rem; - - rem = do_div(art, art_base_clk.denominator); - - res = art * art_base_clk.numerator; - tmp = rem * art_base_clk.numerator; - - do_div(tmp, art_base_clk.denominator); - res += tmp + art_base_clk.offset; - - return (struct system_counterval_t) { - .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, - .cycles = res, - }; -} -EXPORT_SYMBOL(convert_art_to_tsc); - -/** - * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. - * @art_ns: ART (Always Running Timer) in unit of nanoseconds - * - * PTM requires all timestamps to be in units of nanoseconds. When user - * software requests a cross-timestamp, this function converts system timestamp - * to TSC. - * - * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set - * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check - * that this flag is set before conversion to TSC is attempted. - * - * Return: - * struct system_counterval_t - system counter value with the ID of the - * corresponding clocksource: - * cycles: System counter value - * cs_id: The clocksource ID for validating comparability - */ - -struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) -{ - u64 tmp, res, rem; - - rem = do_div(art_ns, USEC_PER_SEC); - - res = art_ns * tsc_khz; - tmp = rem * tsc_khz; - - do_div(tmp, USEC_PER_SEC); - res += tmp; - - return (struct system_counterval_t) { - .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, - .cycles = res, - }; -} -EXPORT_SYMBOL(convert_art_ns_to_tsc); - static void tsc_refine_calibration_work(struct work_struct *work); static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); /** From patchwork Wed Apr 10 11:48:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624155 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03BD8159909; Wed, 10 Apr 2024 11:49:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749773; cv=none; b=mA5oRTtsT69bsjJGwG6c7d4r/s+70GHLZ+jPd/QvbGKQsADvWl0xEr9EZ7y/0S3LdhjrZSKeztet1JvKWow7Zu7ZNLVTDG3wMBDeQxegqw2BSF2HLDzG3pFrjb/yTeTVoiyBPsyP2K1Xj6me4FoPK8j/b40rlnjSBZHNXH09IwI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749773; c=relaxed/simple; bh=4yFG2epkMTZfSUzUaCaIYzcSlYJ6SfR0gapuEZJcQ7g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Ks1B/cIDCABpJMI6tEFJbjgqrp0KixXeIE3m0QuPNMULXHFAGsYR3H64a9oJxnYvmfAvXgfmuScZ3QukbC82sRvnb49Y3z1qUK0qVTrBzew78EKCjGIIT98WvRWbhM/YPi00I7TG4rgUuhuWhURYHMto2n80O1ufN7Q6G0zvIQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Co3uJtdH; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Co3uJtdH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712749773; x=1744285773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4yFG2epkMTZfSUzUaCaIYzcSlYJ6SfR0gapuEZJcQ7g=; b=Co3uJtdHcwdWqXlqdjCoBNxeZ8mjO6BO9EJ4g+yVG/o7oB/vYrILAKt3 UvXBx9OlpbcQolYISJaylZdIobxtIHy9FDkCGGa2S7a1OHk0BIHipvh+A 8MrNWeASyypPDkOxts9oLfuBcOygDjPO6M+Wsy/YKD2sey2NQUmcxGItC eLWo8FuZF37q+L6097A8rtVahU5WKENAQJj3NFbi8lb10rwVO/nRTKFtd +GERyYQAdu0Yv6kfiSwqVqGU7QXYcw2TkOddbBiS+oTc1k54FJqlI06UB kODlWLZBRStHBLeWUch0gGiGYG3oqBpCrFazkitbz95SlwNzkfu/lnyti w==; X-CSE-ConnectionGUID: QCHZKlxDR8aRcQPGJEFefA== X-CSE-MsgGUID: vmtNCXbXScutjf3Jq7AQ1w== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="11944185" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944185" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:49:30 -0700 X-CSE-ConnectionGUID: cv+Xk9N7SI+tpBWojhhwTg== X-CSE-MsgGUID: h15+G8CxQD6pKKxlg/oWUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769286" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:23 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 08/11] timekeeping: Add function to convert realtime to base clock Date: Wed, 10 Apr 2024 17:18:25 +0530 Message-Id: <20240410114828.25581-9-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D PPS(Pulse Per Second) generates signals in realtime, but Timed IO hardware understands time in base clock reference. Add an interface, ktime_real_to_base_clock() to convert realtime to base clock. Add the helper function timekeeping_clocksource_has_base(), to check whether the current clocksource has the same base clock. This will be used by Timed IO device to check if the base clock is X86_ART(Always Running Timer). Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- include/linux/timekeeping.h | 4 +++ kernel/time/timekeeping.c | 70 +++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index b2ee182d891e..fc12a9ba2c88 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -318,6 +318,10 @@ struct system_counterval_t { bool use_nsecs; }; +extern bool ktime_real_to_base_clock(ktime_t treal, + enum clocksource_ids base_id, u64 *cycles); +extern bool timekeeping_clocksource_has_base(enum clocksource_ids id); + /* * Get cross timestamp between system clock and device clock */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 2542cfefbdee..e4ecce722969 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1227,6 +1227,48 @@ static bool convert_base_to_cs(struct system_counterval_t *scv) return true; } +static bool convert_cs_to_base(u64 *cycles, enum clocksource_ids base_id) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + + /* Check whether base_id matches the base clock */ + if (!base || base->id != base_id) + return false; + + *cycles -= base->offset; + if (!convert_clock(cycles, base->denominator, base->numerator)) + return false; + return true; +} + +static u64 convert_ns_to_cs(u64 delta) +{ + struct tk_read_base *tkr = &tk_core.timekeeper.tkr_mono; + + return div_u64((delta << tkr->shift) - tkr->xtime_nsec, tkr->mult); +} + +bool ktime_real_to_base_clock(ktime_t treal, enum clocksource_ids base_id, u64 *cycles) +{ + struct timekeeper *tk = &tk_core.timekeeper; + unsigned int seq; + u64 delta; + + do { + seq = read_seqcount_begin(&tk_core.seq); + if ((u64)treal < tk->tkr_mono.base_real) + return false; + delta = (u64)treal - tk->tkr_mono.base_real; + *cycles = tk->tkr_mono.cycle_last + convert_ns_to_cs(delta); + if (!convert_cs_to_base(cycles, base_id)) + return false; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return true; +} +EXPORT_SYMBOL_GPL(ktime_real_to_base_clock); + /** * get_device_system_crosststamp - Synchronously capture system/device timestamp * @get_time_fn: Callback to get simultaneous device time and @@ -1337,6 +1379,34 @@ int get_device_system_crosststamp(int (*get_time_fn) } EXPORT_SYMBOL_GPL(get_device_system_crosststamp); +/** + * timekeeping_clocksource_has_base - Check whether the current clocksource + * has a base clock + * @id: The clocksource ID to check for + * + * Note: The return value is a snapshot which can become invalid right + * after the function returns. + * + * Return: true if the timekeeper clocksource has a base clock with @id, + * false otherwise + */ +bool timekeeping_clocksource_has_base(enum clocksource_ids id) +{ + unsigned int seq; + bool ret; + + do { + seq = read_seqcount_begin(&tk_core.seq); + if (tk_core.timekeeper.tkr_mono.clock->base) + ret = (tk_core.timekeeper.tkr_mono.clock->base->id == id); + else + ret = false; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return ret; +} +EXPORT_SYMBOL_GPL(timekeeping_clocksource_has_base); + /** * do_settimeofday64 - Sets the time of day. * @ts: pointer to the timespec64 variable containing the new time From patchwork Wed Apr 10 11:48:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624156 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46BCA159909; Wed, 10 Apr 2024 11:49:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749779; cv=none; b=ewoWnELWy+qxcsvYoZcy1vWXuj784OwBvIdn4fsRfNRFVgTd7HfbE2a/X6QhM/Pmk3xxn7h7OG3JF0sZNSctz3A9NJPxvs3Us7Vik0SaZNOMHQZlc8Bu2b6hJxkijkpgU/7MjU5xEhioc7Z4VzWWjpMrJrsg6GQrTNDfee/+xc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="43769314" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:29 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 09/11] pps: generators: Add PPS Generator TIO Driver Date: Wed, 10 Apr 2024 17:18:26 +0530 Message-Id: <20240410114828.25581-10-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 258 +++++++++++++++++++++++++++ 3 files changed, 275 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makefile index 2589fd0f2481..714e847ae193 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,5 +4,6 @@ # obj-$(CONFIG_PPS_GENERATOR_PARPORT) += pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) += pps_gen_tio.o ccflags-$(CONFIG_PPS_DEBUG) := -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c new file mode 100644 index 000000000000..74c2a92eddb8 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer early */ +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; + u32 prev_count; +}; + +static inline u32 pps_tio_read(struct pps_tio *tio, u32 offset) +{ + return readl(tio->base + offset); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_tio_read(tio, TIOCTL); + pps_compv_write(tio, 0); + + ctrl &= ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + tio->prev_count = 0; + + return ctrl; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &= ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |= TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + + ctrl |= TIOCTL_EN; + pps_ctl_write(tio, ctrl); +} + +static bool pps_generate_next_pulse(struct pps_tio *tio, ktime_t expires) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(tio, art - ART_HW_DELAY_CYCLES); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio = container_of(timer, struct pps_tio, timer); + ktime_t expires, now; + u32 event_count; + + guard(spinlock)(&tio->lock); + + /* Check if any event is missed. If an event is missed, TIO will be disabled*/ + event_count = pps_tio_read(tio, TIOEC); + if (!tio->prev_count && tio->prev_count == event_count) + goto err; + tio->prev_count = event_count; + expires = hrtimer_get_expires(timer); + now = ktime_get_real(); + + if (now - expires < SAFE_TIME_NS) { + if (!pps_generate_next_pulse(tio, expires + SAFE_TIME_NS)) + goto err; + } + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; +err: + dev_err(tio->dev, "Event missed, Disabling Timed I/O"); + pps_tio_disable(tio); + return HRTIMER_NORESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *attr, const char *buf, + size_t count) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + bool enable; + int err; + + err = kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err(tio->dev, "PPS cannot be started as clock is not related to ART"); + return -EPERM; + } + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + tio->enabled = true; + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + tio->enabled = false; + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + u32 ctrl; + + ctrl = pps_tio_read(tio, TIOCTL); + ctrl &= TIOCTL_EN; + + return sysfs_emit(buf, "%u\n", ctrl); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] = { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_tio_probe(struct platform_device *pdev) +{ + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(&pdev->dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio = devm_kzalloc(&pdev->dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev = &pdev->dev; + tio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function = hrtimer_callback; + spin_lock_init(&tio->lock); + tio->enabled = false; + platform_set_drvdata(pdev, tio); + + return 0; +} + +static int pps_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio = platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + + return 0; +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_tio_driver = { + .probe = pps_tio_probe, + .remove = pps_tio_remove, + .driver = { + .name = "intel-pps-generator", + .acpi_match_table = intel_pmc_tio_acpi_match, + .dev_groups = pps_tio_groups, + }, +}; +module_platform_driver(pps_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Apr 10 11:48:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624157 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED77115F3F7; Wed, 10 Apr 2024 11:49:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749785; cv=none; b=mDvblD3CIrun9A3lepq+qnauJNdiuhnoaS0dvG7FyaQHPyBRjUsmM7Dgpd/2DKnw0rDhYHDjYLHijJNYvvT8wD8HbjkmLof0Sbq14oZH+Z4/v4KJjdPKLhBfnC8A4DQ01YIAahMhgTgPWZi4cbz5Z9o8n7yLmGdcoXKgZ/r8BKI= ARC-Message-Signature: i=1; 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d="scan'208";a="43769356" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:36 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 10/11] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Wed, 10 Apr 2024 17:18:27 +0530 Message-Id: <20240410114828.25581-11-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pps.rst index 78dded03e5d8..52a6d5faf885 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -246,3 +246,25 @@ delay between assert and clear edge as small as possible to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signals. + +Timed I/O and system time are both driven by same hardware clock. The signal +is generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +share your clock with a device that receives PPS signal, generated by +Timed I/O device. There are dedicated Timed I/O pins to deliver the PPS signal +to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable From patchwork Wed Apr 10 11:48:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 13624158 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F3F815B990; Wed, 10 Apr 2024 11:49:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749791; cv=none; b=roAY/f74bVfmQYF7/jxVA5ImkeXrA9XgRZ/UZY8LRuYXu9kvEFXhyLl6rfFr1Dclz3/YBeZQms45w+Mue1mFKSCg/Aoin1NBdil4JP4WagoJCBw6zx3mWCTx8TOxUETsz1UE4ANNMoFNROaWBOB5mTHg0vz81M5bLtIsv0r+b+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712749791; c=relaxed/simple; bh=hZSWgcp7GnBBKQ/ANmuBJ1lGoqRIvIkLrQj6268hnRY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eyhMzbfSTN2rgS6jeN1y5lVBxJXhei8YnI9cfTUPVvplNfM/DzylLw+9HETlXbJL2Aydd6+C93HDmHFio2EJv2U/DLfUc7DZ8jvhfAkUxwNRL6kZkhWiPHpLh4plPppfFM36gRNIPbKpw1ob0axzlOSeqJ3VkhlAELurOiSQqIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PBmWg1Ej; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PBmWg1Ej" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1712749791; x=1744285791; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hZSWgcp7GnBBKQ/ANmuBJ1lGoqRIvIkLrQj6268hnRY=; b=PBmWg1EjZrOXZKwQpe3+9Mz58iby46bu4mwDcdV8V369+0fUfuN2OgVJ XrVylhGe54jkNyCHG0bkJhu0SqqFqEgufWZjSo/90hXdOAqigDQfOeMly 26kFezkNn1SizyPXGBZYPHpOTnFmTl5OGpiZUVH3GFh+ecSH+zUCKnLxC ViI04zdtIT6oxxdG3RbVWvl9jaDK5NkpUvNYZAKwePp7NZnWkgHQTUuna cRZn5sd+7UPFt2apkPiQVQpiCKkw3y00g1jyqiwztED/m//eg4swhdlUE ipjIyRsUBhwgAHyBP3c9BVRumjmS5CV5RL/UXkYzEgZy+lzeO+/gnBhL+ g==; X-CSE-ConnectionGUID: b/dqFYzlTp2kw2Cs+oV3ZQ== X-CSE-MsgGUID: xzslro3WSQmtcgbPx8tUfg== X-IronPort-AV: E=McAfee;i="6600,9927,11039"; a="11944240" X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="11944240" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2024 04:49:50 -0700 X-CSE-ConnectionGUID: OT+wDgJGSJqHR+RwN/KXfA== X-CSE-MsgGUID: QtnGadiqSc2BPgOAsMkeig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,190,1708416000"; d="scan'208";a="43769373" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa002.fm.intel.com with ESMTP; 10 Apr 2024 04:49:43 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v6 11/11] ABI: pps: Add ABI documentation for Intel TIO Date: Wed, 10 Apr 2024 17:18:28 +0530 Message-Id: <20240410114828.25581-12-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> References: <20240410114828.25581-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Lakshmi Sowjanya D Document sysfs interface for Intel Timed I/O PPS driver. Signed-off-by: Lakshmi Sowjanya D --- Documentation/ABI/testing/sysfs-platform-pps-tio | 7 +++++++ MAINTAINERS | 1 + 2 files changed, 8 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentation/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..b9b8c97a7840 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,7 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: March 2024 +KernelVersion 6.9 +Contact: Lakshmi Sowjanya D +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware (Enabled/Disabled). diff --git a/MAINTAINERS b/MAINTAINERS index aea47e04c3a5..e63365a2d029 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17684,6 +17684,7 @@ M: Rodolfo Giometti L: linuxpps@ml.enneenne.com (subscribers-only) S: Maintained W: http://wiki.enneenne.com/index.php/LinuxPPS_support +F: Documentation/ABI/testing/sysfs-platform-pps-tio F: Documentation/ABI/testing/sysfs-pps F: Documentation/devicetree/bindings/pps/pps-gpio.yaml F: Documentation/driver-api/pps.rst