From patchwork Thu Apr 11 13:01:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13625928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5D88CD1284 for ; Thu, 11 Apr 2024 13:02:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=MOV7AlA81QO2WwIb4zeQJ39fmeQn2U5qvwZOajw2sl0=; b=gxgur3bnvPwBUO ItCgAoXoHegEeSg8iwTfS3cy+wS/gxmp90lhJ++rWmxkYrZFLM0Z7dQ8P6Fg+OMLePR6Hg3zhQdPK CucaDY5EegURn4XCTQNw9YDkUnPiJ8VLa1HtigmZMD6bvvKtuUC0XxP6po9QDgBIRr78dUHetcPlD imW3djYdTFS2SH4sVZpSbAH2mhEv5Iweq2On2qmHcql5jRXFZqsjXmF+iDN/7/gswGv1/p6ukl4RF DAsW25aCmBZW3ceiX2TvC4+mdnpkHx40tOlTHyUSQd+5JzhNOLul33PV5ooYN6fnruGecz4SBTzSt RcFw7+WeOn1ShNSGyKwg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruu4B-0000000C3sm-291I; Thu, 11 Apr 2024 13:02:11 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruu44-0000000C3oQ-1CRl; Thu, 11 Apr 2024 13:02:06 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 58B34CE2F08; Thu, 11 Apr 2024 13:02:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CB70C43399; Thu, 11 Apr 2024 13:01:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712840521; bh=qArvCH0loValMvQRklgm8B3LhtKJu/iCEN816zFGIGc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ajlmh5HCGLK6fVFUczGYBXA+AV9/+dY89VDGtD8yQgC+ZQ/W9G6u6nLshRRVtGbrF IqDZ0GmrOuLgLdcC4yzzLHnefopsjLmOo7cNx0BVGZYvYL8+/Joj/CSPiskNY1376D +1BRi4Rgr2wMImxCv+EjufVDqBsDeeCMr41PR0KRmyoQFoE4T8wnfiiAaxIxpD5iLO qCdo7CSS3N3lBV3HPEXg6/6ikSVi9cUGg+54TjNrLqtU/X+oWQ8GwdTfpCGpC87Jmr +5MSSKy+oN//PW5AYcPy+6zwi2EmF0dFW+6FhZdS2A9/6PPfd93clMwhVJEkIhe2wr Nl6E4KjbZUxUA== From: Niklas Cassel To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: devicetree@vger.kernel.org, Sebastian Reichel , Michal Tomek , Damien Le Moal , Jon Lin , Niklas Cassel , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 1/2] dt-bindings: phy: rockchip,pcie3-phy: add rockchip,rx-common-refclk-mode Date: Thu, 11 Apr 2024 15:01:47 +0200 Message-ID: <20240411130150.128107-2-cassel@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411130150.128107-1-cassel@kernel.org> References: <20240411130150.128107-1-cassel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_060204_574642_4B5DF37E X-CRM114-Status: GOOD ( 11.26 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add a rockchip specific property to enable/disable the rxX_cmn_refclk_mode per lane. (Since this PHY supports bifurcation.) Signed-off-by: Niklas Cassel Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/phy/rockchip,pcie3-phy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml index c4fbffcde6e4..ba67dca5a446 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml @@ -54,6 +54,16 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the syscon managing the pipe "general register files" + rockchip,rx-common-refclk-mode: + description: which lanes (by position) should be configured to run in + RX common reference clock mode. 0 means disabled, 1 means enabled. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + items: + minimum: 0 + maximum: 1 + required: - compatible - reg From patchwork Thu Apr 11 13:01:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 13625929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6301CD128A for ; Thu, 11 Apr 2024 13:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=GMRCo5BdL9fjTsqHfyB4PFcAllI1+lt5T91Jx9d/6iQ=; b=DHvAU+K85fDP2c /nR3Gxpqp6CSDfz2tCs4SOdEnx8g7dNViWYodCmPoFuEl8GX8EYnEqkMerNfBBzsyKHTO+o206ink 43B/IKe70lSkv1sNnrVmhoMQPMikIpZAumsnabNVMFWaTt0+r96tC0v11H3wyi91hatCYyvKDZPm3 zlIDuxJNH2Q4YSiJsfwlOmn1OVOMcBlwTWao1FWpqIMxH4qimOjUmGeStM92F4TH7O/8Ot5lePEUS 0dUiQB/Qt5qi2S+sGe9M3+Ekz8lGNFd2aheTkoPNT4RzuArS8B0ERbfpF1N+z5utxUcXCJgGBFWZZ TshWOqF+ciluvD8j9ZBQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruu4K-0000000C3yJ-373B; Thu, 11 Apr 2024 13:02:20 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1ruu47-0000000C3qI-1X0f; Thu, 11 Apr 2024 13:02:09 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id AA2FECE3081; Thu, 11 Apr 2024 13:02:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 44BD0C43394; Thu, 11 Apr 2024 13:02:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712840524; bh=PERXIyqtvzuRMlWj3fA9x52yulWXjRx921xLECr3yao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Eh8Z/ER9BGdDdw14S9OLpYeeahIBpS42U+lZY++GBUTtjgDIXxzKh933pR4CHfMqH ysrnp3PGkhy+nrpZIu8ytkzblQdkYrMZmDQ1sqQC6d8O236yu8oY1PDArxuxnY/+NC 7sqrFWmrUfy5CyCMGmZQOlWdvkJ/EjIyXDnAmT0699Mcf1Vw/WEkb9+kjHYHreUGyh 8/Z6D4ds/4ZUIfCYolAstOoHr+AXMaxrKn3CysM65tOAx8WtRUScUPpw2XH+uXfiDJ 3NiSUJzoii29YAOjytx2zdipXTVwRzNEfHD6PSBkNMszd+BajqKdRUZFHLfgZgg8C8 gA9v11PEZQCOg== From: Niklas Cassel To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: devicetree@vger.kernel.org, Sebastian Reichel , Michal Tomek , Damien Le Moal , Jon Lin , Niklas Cassel , linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 2/2] phy: rockchip-snps-pcie3: add support for rockchip,rx-common-refclk-mode Date: Thu, 11 Apr 2024 15:01:48 +0200 Message-ID: <20240411130150.128107-3-cassel@kernel.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240411130150.128107-1-cassel@kernel.org> References: <20240411130150.128107-1-cassel@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240411_060207_931581_9ACEE579 X-CRM114-Status: GOOD ( 18.71 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From the RK3588 Technical Reference Manual, Part1, section 6.19 PCIe3PHY_GRF Register Description: "rxX_cmn_refclk_mode" RX common reference clock mode for lane X. This mode should be enabled only when the far-end and near-end devices are running with a common reference clock. The hardware reset value for this field is 0x1 (enabled). Note that this register field is only available on RK3588, not on RK3568. The link training either fails or is highly unstable (link state will jump continuously between L0 and recovery) when this mode is enabled while using an endpoint running in Separate Reference Clock with No SSC (SRNS) mode or Separate Reference Clock with SSC (SRIS) mode. (Which is usually the case when using a real SoC as endpoint, e.g. the RK3588 PCIe controller can run in both Root Complex and Endpoint mode.) Add support for the device tree property rockchip,rx-common-refclk-mode, such that the PCIe PHY can be used in configurations where the Root Complex and Endpoint are not using a common reference clock. Signed-off-by: Niklas Cassel --- .../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 9857ee45b89e..3c532658da4c 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -35,11 +35,17 @@ #define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0 #define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904 #define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04 +#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004 +#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104 +#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004 +#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104 #define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0)) #define RK3588_BIFURCATION_LANE_0_1 BIT(0) #define RK3588_BIFURCATION_LANE_2_3 BIT(1) #define RK3588_LANE_AGGREGATION BIT(2) +#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7)) +#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16) #define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) #define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) @@ -60,6 +66,7 @@ struct rockchip_p3phy_priv { int num_clks; int num_lanes; u32 lanes[4]; + u32 rx_cmn_refclk_mode[4]; }; struct rockchip_p3phy_ops { @@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) u8 mode = RK3588_LANE_AGGREGATION; /* default */ int ret; + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1, + priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN : + RK3588_RX_CMN_REFCLK_MODE_DIS); + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1, + priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN : + RK3588_RX_CMN_REFCLK_MODE_DIS); + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1, + priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN : + RK3588_RX_CMN_REFCLK_MODE_DIS); + regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1, + priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN : + RK3588_RX_CMN_REFCLK_MODE_DIS); + /* Deassert PCIe PMA output clamp mode */ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24)); @@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct platform_device *pdev) return priv->num_lanes; } + ret = of_property_read_variable_u32_array(dev->of_node, + "rockchip,rx-common-refclk-mode", + priv->rx_cmn_refclk_mode, 1, + ARRAY_SIZE(priv->rx_cmn_refclk_mode)); + /* + * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in + * order to be DT backwards compatible. (Since HW reset val is enabled.) + */ + if (ret == -EINVAL) { + for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++) + priv->rx_cmn_refclk_mode[i] = 1; + } else if (ret < 0) { + dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n", + ret); + return ret; + } + priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops); if (IS_ERR(priv->phy)) { dev_err(dev, "failed to create combphy\n");