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The "Message Routing" is in the section 2.2.8, and the "INTx Mechanism Messages" is in the section 2.2.8.1 on the PCI Express Base Specification, Rev 6.1. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas Signed-off-by: Frank Li --- drivers/pci/pci.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 17fed18468474..19b4227a8a7e8 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -22,6 +22,24 @@ */ #define PCIE_PME_TO_L2_TIMEOUT_US 10000 +/* Message Routing (r[2:0]) See: PCIe r6.0, sec 2.2.8 */ +#define PCIE_MSG_TYPE_R_RC 0 +#define PCIE_MSG_TYPE_R_ADDR 1 +#define PCIE_MSG_TYPE_R_ID 2 +#define PCIE_MSG_TYPE_R_BC 3 +#define PCIE_MSG_TYPE_R_LOCAL 4 +#define PCIE_MSG_TYPE_R_GATHER 5 + +/* INTx Mechanism Messages See: PCIe r6.0, sec 2.2.8.1 */ +#define PCIE_MSG_CODE_ASSERT_INTA 0x20 +#define PCIE_MSG_CODE_ASSERT_INTB 0x21 +#define PCIE_MSG_CODE_ASSERT_INTC 0x22 +#define PCIE_MSG_CODE_ASSERT_INTD 0x23 +#define PCIE_MSG_CODE_DEASSERT_INTA 0x24 +#define PCIE_MSG_CODE_DEASSERT_INTB 0x25 +#define PCIE_MSG_CODE_DEASSERT_INTC 0x26 +#define PCIE_MSG_CODE_DEASSERT_INTD 0x27 + extern const unsigned char pcie_link_speed[]; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?LeO/1qPvkLuClqSXy5j4yVeNjS/y?= =?utf-8?q?DohTYw/1c8XHXCeQDn6bYQV8etEVLXerkkznXFn/iwdjvT9/sbLLmjfBB6e+JXlGV?= =?utf-8?q?UbBn+C1HznWzgL49kLyDXjRJ8Kg1Xhk0+5DKcHFDedGX2DShHlIH0J0OcuNgPzEqy?= =?utf-8?q?liMUcyR8GGfuqh7yjOmMO/aBCUFBKhGFJ9yniJlQP3QSHQXaSQI7s+J1U7C75agoY?= =?utf-8?q?dL2i+uNcU9yW5OWeV8VbqIegkQRoryPAcMmF5Zlc1MoCZ9bl5/Tflx4IvnJ90/jN6?= =?utf-8?q?qENzYtkM3l1vdONWIxlfpyl0ezQhZgAyblS75ZyWwnsrP41XOUv9ZsL9pjyd8sm/t?= =?utf-8?q?IofGVbeA4wwpAlTY7rAwHe7z8gNGerc/bB0c+vxXt5zYliEv14CLNx1Ubxjvnrsf2?= =?utf-8?q?zdmhEm2zSMUG6OKGrzlXg1LXGzlLmAE152fLfzpet+OW995rHcgQrLAJyoS3ufAei?= =?utf-8?q?Hmk7ho3SX3JIpqOssmXXYRuPhEgWFandep4Fqv4T2XaEAnB+jbURp18rTo1TPlm+e?= =?utf-8?q?phJ1Q1JFO/X/24gTmLk911r8ybIW15NyliOtyn6BD8Mfo7xXF1FnF9ANJP+uMZOIF?= =?utf-8?q?GbDYO4qlQCzZkXp9eGDaaPaF9ycT17XWVcw8hl54WRBtQ0OibiCKgjLxvIFPEyICI?= =?utf-8?q?iIJSOHBBY5dmQTFk5GdZN0Tl0cgmWbwdyklysTPX1537ojXJigXTiqWIKtP1RcyMF?= =?utf-8?q?nMXyvg2R4pYfqRcdo9t1mwnKhnGFPvSCOCtRiSch1zmKw48XvpzZSdUbzv4DbE6pn?= =?utf-8?q?spV3IB2jHfx7XyYMasUKydK7Y3RVNxqbK360YMaMnTW7ggxXYRfyTJOgcQNUph3If?= =?utf-8?q?DfLnLCGfc7VMgf5ekoK+QuXDSZoPM4hlw1Qe3+KbyjWkFzVrHedc3s5QWihyIDwED?= =?utf-8?q?BTF4W6gLqPbw4rpFkPuMzUqBw+ekpRw0jMaQ2g9gMrAJuBHwMVnhOT2st/+9Kl6XS?= =?utf-8?q?cphtf2T/bZjRROHjDzdb/+icOz85dAHqSBTXx74wI+maYomLkDFXLQ8pWFgidwfh8?= =?utf-8?q?eli86jk293fajZ+u7CMSwnMl3O3+c+hSHvHDnVWhNvvvby3P3vkCVAPDR93a8y497?= =?utf-8?q?BZx73cYOrYv9NA+WVVb4ZWDaixbmF/ybwu+LhDclzgMKd+iA5QuvJx3GdCo1sikEX?= =?utf-8?q?CHnizqmCChmw+y3U4jso+9MxUVEDHaZzzr07PWgWKJwx4jDZpFA9lT1UiE2MeIzFN?= =?utf-8?q?EC0dQR/NW6oquRVOqExIStG+wWjOB12IhhdVkHEw9wuS3t3z8j80DX53yFL0MZdJe?= =?utf-8?q?ol8VBlyoubjULGcswAYkMzftI8TkgVbyLWAdmKrDrLIOLqwaVQ6AT4V5bWn+zmWrU?= =?utf-8?q?v6T4+RQTu1pAD9/iarQnk9rL0mYOE8YxCoc4Sq3PvO/wlN9WW/gL/5XAcjTw0tMAN?= =?utf-8?q?fuKPFayvi2+1Y7CBGXWJZjeHkB9++wKjkP4CICDz/3tJi+BzBFkSdlC65bFYm73zd?= =?utf-8?q?6RR9bFFXK3WSmRKiCuZS0GNNORR70CsrsPi12mb0BunqBNeSWtZa75qs=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 19686bfe-f121-435c-d7cd-08dc5d83001c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2024 19:34:00.4844 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jgSqw2FCQbEiTQnh2SMBYE7Vqq3F1tsyxpKrN5OfkBRcOMKB/0JD75a4fV14MGy3mnOO6NxAjhMd6wioshtFxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA2PR04MB10279 From: Yoshihiro Shimoda This is a preparation before adding the Msg-type outbound iATU mapping. The respective update will require two more arguments added to __dw_pcie_prog_outbound_atu(). That will make the already complicated function prototype even more hard to comprehend accepting _eight_ arguments. In order to prevent that and keep the code more-or-less readable all the outbound iATU-related arguments are moved to the new config-structure: struct dw_pcie_ob_atu_cfg pointer to which shall be passed to dw_pcie_prog_outbound_atu(). The structure is supposed to be locally defined and populated with the outbound iATU settings implied by the caller context. As a result of the denoted change there is no longer need in having the two distinctive methods for the Host and End-point outbound iATU setups since the corresponding code can directly call the dw_pcie_prog_outbound_atu() method with the config-structure populated. Thus dw_pcie_prog_ep_outbound_atu() is dropped. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-ep.c | 21 +++++---- drivers/pci/controller/dwc/pcie-designware-host.c | 52 ++++++++++++++++------- drivers/pci/controller/dwc/pcie-designware.c | 49 ++++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 15 +++++-- 4 files changed, 77 insertions(+), 60 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 746a11dcb67f1..9dd6a2edc7ae5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -160,9 +160,8 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, u8 func_no, int type, return 0; } -static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, - phys_addr_t phys_addr, - u64 pci_addr, size_t size) +static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, + struct dw_pcie_ob_atu_cfg *atu) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); u32 free_win; @@ -174,13 +173,13 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, u8 func_no, return -EINVAL; } - ret = dw_pcie_prog_ep_outbound_atu(pci, func_no, free_win, PCIE_ATU_TYPE_MEM, - phys_addr, pci_addr, size); + atu->index = free_win; + ret = dw_pcie_prog_outbound_atu(pci, atu); if (ret) return ret; set_bit(free_win, ep->ob_window_map); - ep->outbound_addr[free_win] = phys_addr; + ep->outbound_addr[free_win] = atu->cpu_addr; return 0; } @@ -280,8 +279,14 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no, int ret; struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - - ret = dw_pcie_ep_outbound_atu(ep, func_no, addr, pci_addr, size); + struct dw_pcie_ob_atu_cfg atu = { 0 }; + + atu.func_no = func_no; + atu.type = PCIE_ATU_TYPE_MEM; + atu.cpu_addr = addr; + atu.pci_addr = pci_addr; + atu.size = size; + ret = dw_pcie_ep_outbound_atu(ep, &atu); if (ret) { dev_err(pci->dev, "Failed to enable address\n"); return ret; diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d15a5c2d5b480..3a9cb4be22ab2 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -554,6 +554,7 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int type, ret; u32 busdev; @@ -576,8 +577,12 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, else type = PCIE_ATU_TYPE_CFG1; - ret = dw_pcie_prog_outbound_atu(pci, 0, type, pp->cfg0_base, busdev, - pp->cfg0_size); + atu.type = type; + atu.cpu_addr = pp->cfg0_base; + atu.pci_addr = busdev; + atu.size = pp->cfg0_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return NULL; @@ -589,6 +594,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int ret; ret = pci_generic_config_read(bus, devfn, where, size, val); @@ -596,9 +602,12 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, return ret; if (pp->cfg0_io_shared) { - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, - pp->io_base, pp->io_bus_addr, - pp->io_size); + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return PCIBIOS_SET_FAILED; } @@ -611,6 +620,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, { struct dw_pcie_rp *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; int ret; ret = pci_generic_config_write(bus, devfn, where, size, val); @@ -618,9 +628,12 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, return ret; if (pp->cfg0_io_shared) { - ret = dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, - pp->io_base, pp->io_bus_addr, - pp->io_size); + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) return PCIBIOS_SET_FAILED; } @@ -655,6 +668,7 @@ static struct pci_ops dw_pcie_ops = { static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu = { 0 }; struct resource_entry *entry; int i, ret; @@ -682,10 +696,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pci->num_ob_windows <= ++i) break; - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_MEM, - entry->res->start, - entry->res->start - entry->offset, - resource_size(entry->res)); + atu.index = i; + atu.type = PCIE_ATU_TYPE_MEM; + atu.cpu_addr = entry->res->start; + atu.pci_addr = entry->res->start - entry->offset; + atu.size = resource_size(entry->res); + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set MEM range %pr\n", entry->res); @@ -695,10 +712,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) if (pp->io_size) { if (pci->num_ob_windows > ++i) { - ret = dw_pcie_prog_outbound_atu(pci, i, PCIE_ATU_TYPE_IO, - pp->io_base, - pp->io_bus_addr, - pp->io_size); + atu.index = i; + atu.type = PCIE_ATU_TYPE_IO; + atu.cpu_addr = pp->io_base; + atu.pci_addr = pp->io_bus_addr; + atu.size = pp->io_size; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set IO range %pr\n", entry->res); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f40b858..df2575ec5f44c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -465,56 +465,56 @@ static inline u32 dw_pcie_enable_ecrc(u32 val) return val | PCIE_ATU_TD; } -static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, - int index, int type, u64 cpu_addr, - u64 pci_addr, u64 size) +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, + const struct dw_pcie_ob_atu_cfg *atu) { + u64 cpu_addr = atu->cpu_addr; u32 retries, val; u64 limit_addr; if (pci->ops && pci->ops->cpu_addr_fixup) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr); - limit_addr = cpu_addr + size - 1; + limit_addr = cpu_addr + atu->size - 1; if ((limit_addr & ~pci->region_limit) != (cpu_addr & ~pci->region_limit) || !IS_ALIGNED(cpu_addr, pci->region_align) || - !IS_ALIGNED(pci_addr, pci->region_align) || !size) { + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) { return -EINVAL; } - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_BASE, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_BASE, lower_32_bits(cpu_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_BASE, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_BASE, upper_32_bits(cpu_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LIMIT, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LIMIT, lower_32_bits(limit_addr)); if (dw_pcie_ver_is_ge(pci, 460A)) - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_LIMIT, + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_LIMIT, upper_32_bits(limit_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_LOWER_TARGET, - lower_32_bits(pci_addr)); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_UPPER_TARGET, - upper_32_bits(pci_addr)); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_LOWER_TARGET, + lower_32_bits(atu->pci_addr)); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, + upper_32_bits(atu->pci_addr)); - val = type | PCIE_ATU_FUNC_NUM(func_no); + val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; if (dw_pcie_ver_is(pci, 490A)) val = dw_pcie_enable_ecrc(val); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL1, val); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); /* * Make sure ATU enable takes effect before any subsequent config * and I/O accesses. */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { - val = dw_pcie_readl_atu_ob(pci, index, PCIE_ATU_REGION_CTRL2); + val = dw_pcie_readl_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2); if (val & PCIE_ATU_ENABLE) return 0; @@ -526,21 +526,6 @@ static int __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no, return -ETIMEDOUT; } -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u64 size) -{ - return __dw_pcie_prog_outbound_atu(pci, 0, index, type, - cpu_addr, pci_addr, size); -} - -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u64 pci_addr, - u64 size) -{ - return __dw_pcie_prog_outbound_atu(pci, func_no, index, type, - cpu_addr, pci_addr, size); -} - static inline u32 dw_pcie_readl_atu_ib(struct dw_pcie *pci, u32 index, u32 reg) { return dw_pcie_readl_atu(pci, PCIE_ATU_REGION_DIR_IB, index, reg); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 26dae48374627..d21db82e586d5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -299,6 +299,15 @@ enum dw_pcie_ltssm { DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, }; +struct dw_pcie_ob_atu_cfg { + int index; + int type; + u8 func_no; + u64 cpu_addr; + u64 pci_addr; + u64 size; +}; + struct dw_pcie_host_ops { int (*init)(struct dw_pcie_rp *pp); void (*deinit)(struct dw_pcie_rp *pp); @@ -434,10 +443,8 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); -int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, - u64 cpu_addr, u64 pci_addr, u64 size); -int dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index, - int type, u64 cpu_addr, u64 pci_addr, u64 size); +int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, + const struct dw_pcie_ob_atu_cfg *atu); int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type, u64 cpu_addr, u64 pci_addr, u64 size); int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index, From patchwork Mon Apr 15 19:33:27 2024 Content-Type: text/plain; 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PCIE_ATU_INHIBIT_PAYLOAD is set to issue TLP type of Msg instead of MsgD. So, this implementation supports the data-less messages only for now. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Serge Semin Reviewed-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++-- drivers/pci/controller/dwc/pcie-designware.h | 4 ++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index df2575ec5f44c..ba909fade9db1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -499,7 +499,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_UPPER_TARGET, upper_32_bits(atu->pci_addr)); - val = atu->type | PCIE_ATU_FUNC_NUM(atu->func_no); + val = atu->type | atu->routing | PCIE_ATU_FUNC_NUM(atu->func_no); if (upper_32_bits(limit_addr) > upper_32_bits(cpu_addr) && dw_pcie_ver_is_ge(pci, 460A)) val |= PCIE_ATU_INCREASE_REGION_SIZE; @@ -507,7 +507,12 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val = dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); - dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, PCIE_ATU_ENABLE); + val = PCIE_ATU_ENABLE; + if (atu->type == PCIE_ATU_TYPE_MSG) { + /* The data-less messages only for now */ + val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code; + } + dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL2, val); /* * Make sure ATU enable takes effect before any subsequent config diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index d21db82e586d5..703b50bc5e0f1 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -148,11 +148,13 @@ #define PCIE_ATU_TYPE_IO 0x2 #define PCIE_ATU_TYPE_CFG0 0x4 #define PCIE_ATU_TYPE_CFG1 0x5 +#define PCIE_ATU_TYPE_MSG 0x10 #define PCIE_ATU_TD BIT(8) #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20) #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 #define PCIE_ATU_UPPER_BASE 0x00C @@ -303,6 +305,8 @@ struct dw_pcie_ob_atu_cfg { int index; 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Mon, 15 Apr 2024 19:34:07 +0000 From: Frank Li Date: Mon, 15 Apr 2024 15:33:28 -0400 Subject: [PATCH v6 4/5] PCI: Add PCIE_MSG_CODE_PME_TURN_OFF message macro Message-Id: <20240415-pme_msg-v6-4-56dad968ad3a@nxp.com> References: <20240415-pme_msg-v6-0-56dad968ad3a@nxp.com> In-Reply-To: <20240415-pme_msg-v6-0-56dad968ad3a@nxp.com> To: Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , imx@lists.linux.dev Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1713209628; l=652; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=IvTQligpMXKWtQKY3rue7KFieXPNIHaS5ARIXkddXi0=; b=/sJleCQxCQNzeMnByvWoiRGRTJTUBnnLxGkQB9oRBlGlKa4H0G2IgsW1UozWK/GT1RhdOsKXe fyHMJu90FHIDSSt5BgP9/4L/phlWoI2r721k9rVyWHsb1YCyjMyrPIq X-Developer-Key: i=Frank.Li@nxp.com; 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Signed-off-by: Frank Li Acked-by: Bjorn Helgaas --- drivers/pci/pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 19b4227a8a7e8..1f6d54a5a7cfc 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -30,6 +30,8 @@ #define PCIE_MSG_TYPE_R_LOCAL 4 #define PCIE_MSG_TYPE_R_GATHER 5 +#define PCIE_MSG_CODE_PME_TURN_OFF 0x19 + /* INTx Mechanism Messages See: PCIe r6.0, sec 2.2.8.1 */ #define PCIE_MSG_CODE_ASSERT_INTA 0x20 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 From patchwork Mon Apr 15 19:33:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630590 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2045.outbound.protection.outlook.com [40.107.105.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 317D1157A7D for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?DAwen3cAvrq84C4h/ORky+gKN4ZP?= =?utf-8?q?k/e+Q8pJ4KrYfr/sefC8VQ+ZVCgYNsQ/R1np9vxfFPCTo5OlBBTJKus2RjIo8HyTg?= =?utf-8?q?evaSte4qSLx9FiWIhnssg9qnfqLl2fZohUNo842wYT/DB4VbGftHuJg3vEqeQ2KQC?= =?utf-8?q?HutWlb4QgU1BHbIZ/qpObmkj5Lk4Ccu+4NGTyeEGWoEvBERRZf6cbb26f2r42+3R9?= =?utf-8?q?Kqqh+5yKIBbY168Brt6mJJevyrebH4JS7SRYOtDhX5FGFR5wB+XG9pT+sj3LIkocx?= =?utf-8?q?VC78u+VhcnlAx5R/zQIu5IX2/l4Q03SkqqgLI7u8t5NcC/0W6Cg5v66T5EPXScwk2?= =?utf-8?q?geMYIBm2V0hWM0Mhox5vHdy+2SDj9XAZI5jVXTlY3MTfSIjg258WcZeDuIJUxpPYm?= =?utf-8?q?2f+WJf9IWcW+9t/DpUnIcTN3ZaYNDXThqLQkAVBw64h08m2vIHsZOVBRxnQqZoF8o?= =?utf-8?q?uyhrZIuFi2i9ysD5kBl3+CKLR2iJldHC1X2nA0f7qmvetdYb7ZLFbPTJA3BNGU9Bo?= =?utf-8?q?ufRWB7aLtTIUJ+9rDusPkpAdcfAEzB65I3Tp5LNLTQkbBtHEgp6PpiLzXfsOl4LLD?= =?utf-8?q?hFpcs4nOftHyYoBY5vmfd9P3/uwZx6vTQfD7voWjDnMP9OiDyp7JMqtmtHAGH4o+6?= =?utf-8?q?si4xnfQIXMv0bUYF+k+x+4bQnMQAzLp5VhqjbrJ9TI5bOlj0aDDX5WCJmBKaLJy2B?= =?utf-8?q?5hlwuwHVMKlq311wOTwNCwyABsZSnZNIoPHl1uIkV+CxtjrbU0sBSN8tMWXWHOueG?= =?utf-8?q?+qLGKrxTEw5SPc1DQzpAGAO2qiADz873dJZM1/VOEqYTaezNuw8U3bt1ZR+PAYDEh?= =?utf-8?q?ds6Wr9kkE+a3hF7EgupJUfB2dzg87WEJhqt8T58CPVz98IpgUO+HZdbqcJX55Ens6?= =?utf-8?q?FesJSnRceOg7Lwm3omlcESZnABFfKh+89M3rV5IwFziPW+VStDTMUnJoZKi2rhCMT?= =?utf-8?q?eW6IFB1yW/jaWVe/kx6BmBaIp769pi/6kFkbOFq4nNkXs7Tq1VxWzmWlDFV1BZIRg?= =?utf-8?q?Zw82d9PzeNtVttm939Htu2Gd7V580nkj8XmPI6yLmhy4t4kwnqMz8gQoEcVrxRPaN?= =?utf-8?q?+KHTWJaM6i0+EuIHkgAeKmerhR0d5EqyWswBJq3u0jv/CQ0MmnnzLysk+fA4kDLWK?= =?utf-8?q?F5a73oi3x9CDI3H2PMytCcCg1er7kbvId4uvvF9NHeenKB/rjZAVl8wriHF76xsBU?= =?utf-8?q?7WuoWwV0Epa4f0FXR5k51dGN7XchBXufhJeTgVa+DnrMbQFcpeTZEOUTMlb4YOepB?= =?utf-8?q?Fn7VZAJHEYoLoY8F+7QOsSIFicLNHFLVV+uEZinwpWTwXKw53bsM5QCXyjD1ss+z9?= =?utf-8?q?nb9gUr3rnVerkuGitu8MitQcccaFpybJf0djac+EaxlbK5+etL/u3KcTE7zJH9ScJ?= =?utf-8?q?P9zoc/lMZb71Z+CWwgxRDRIGaA/hCs802L7ngpuLQNnPqsipQlhrzQn0H3iueUHjb?= =?utf-8?q?Gj69djS49jXWJFE9PXNl7WFWDCag+WeIcY64+gv1V9eLRMf8UuVWIm9Q=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a019d729-429f-4868-fd8c-08dc5d8306c9 X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2024 19:34:11.7238 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zgEOQmaRJINeTMfGUR/2iPj+zmuwPe5WSJzQFJxsFEFsdHjaE1WkdYS3whxIjqRaQCAmk/5kAenbEJruxtAOiQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA2PR04MB10279 Instead of relying on the vendor specific implementations to send the PME_Turn_Off message, let's introduce a generic way of sending the message using the MSG TLP. This is achieved by reserving a region for MSG TLP of size 'pci->region_align', at the end of the first IORESOURCE_MEM window of the host bridge. And then sending the PME_Turn_Off message during system suspend with the help of iATU. The reserve space at end is a little bit better than alloc_resource() because the below reasons. - alloc_resource() will allocate space at begin of IORESOURCE_MEM window. There will be a hole when first Endpoint Device (EP) try to alloc a bigger space then 'region_align' size. - Keep EP device's IORESOURCE_MEM space unchange with/without this patch. It should be noted that this generic implementation is optional for the glue drivers and can be overridden by a custom 'pme_turn_off' callback. Signed-off-by: Frank Li --- drivers/pci/controller/dwc/pcie-designware-host.c | 94 ++++++++++++++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 3 + 2 files changed, 93 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 3a9cb4be22ab2..5001cdf220123 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -398,6 +398,31 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) return 0; } +static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct resource_entry *win; + struct resource *res; + + win = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + if (win) { + res = devm_kzalloc(pci->dev, sizeof(*res), GFP_KERNEL); + if (!res) + return; + + /* Reserve last region_align block as message TLP space */ + res->start = win->res->end - pci->region_align + 1; + res->end = win->res->end; + res->name = "msg"; + res->flags = win->res->flags | IORESOURCE_BUSY; + + if (!devm_request_resource(pci->dev, win->res, res)) + pp->msg_res = res; + else + devm_kfree(pci->dev, res); + } +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -484,6 +509,16 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) dw_pcie_iatu_detect(pci); + /* + * Allocate the resource for MSG TLP before programming the iATU outbound window in + * dw_pcie_setup_rc(). Since the allocation depends on the value of 'region_align', this has + * to be done after dw_pcie_iatu_detect(). + * + * Glue driver need set use_atu_msg before dw_pcie_host_init() if want MSG TLP feature. + */ + if (pp->use_atu_msg) + dw_pcie_host_request_msg_tlp_res(pp); + ret = dw_pcie_edma_detect(pci); if (ret) goto err_free_msi; @@ -541,6 +576,11 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) dw_pcie_edma_remove(pci); + if (pp->msg_res) { + release_resource(pp->msg_res); + devm_kfree(pci->dev, pp->msg_res); + } + if (pp->has_msi_ctrl) dw_pcie_free_msi(pp); @@ -702,6 +742,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) atu.pci_addr = entry->res->start - entry->offset; atu.size = resource_size(entry->res); + /* MSG TLB window resource reserve at one of end of IORESOURCE_MEM resource */ + if (pp->msg_res && pp->msg_res->parent == entry->res) + atu.size -= resource_size(pp->msg_res); + ret = dw_pcie_prog_outbound_atu(pci, &atu); if (ret) { dev_err(pci->dev, "Failed to set MEM range %pr\n", @@ -733,6 +777,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n", pci->num_ob_windows); + pp->msg_atu_index = i; + i = 0; resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) { if (resource_type(entry->res) != IORESOURCE_MEM) @@ -838,11 +884,48 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); +/* Using message outbound ATU to send out PME_Turn_Off message for dwc PCIe controller */ +static int dw_pcie_pme_turn_off(struct dw_pcie *pci) +{ + struct dw_pcie_ob_atu_cfg atu = { 0 }; + void __iomem *mem; + int ret; + + if (pci->num_ob_windows <= pci->pp.msg_atu_index) + return -EINVAL; + + if (!pci->pp.msg_res) + return -EINVAL; + + atu.code = PCIE_MSG_CODE_PME_TURN_OFF; + atu.routing = PCIE_MSG_TYPE_R_BC; + atu.type = PCIE_ATU_TYPE_MSG; + atu.size = resource_size(pci->pp.msg_res); + atu.index = pci->pp.msg_atu_index; + + atu.cpu_addr = pci->pp.msg_res->start; + + ret = dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + mem = ioremap(atu.cpu_addr, pci->region_align); + if (!mem) + return -ENOMEM; + + /* A dummy write is converted to a Msg TLP */ + writel(0, mem); + + iounmap(mem); + + return 0; +} + int dw_pcie_suspend_noirq(struct dw_pcie *pci) { u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); u32 val; - int ret; + int ret = 0; /* * If L1SS is supported, then do not put the link into L2 as some @@ -854,10 +937,13 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci) if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) return 0; - if (!pci->pp.ops->pme_turn_off) - return 0; + if (pci->pp.ops->pme_turn_off) + pci->pp.ops->pme_turn_off(&pci->pp); + else + ret = dw_pcie_pme_turn_off(pci); - pci->pp.ops->pme_turn_off(&pci->pp); + if (ret) + return ret; ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, PCIE_PME_TO_L2_TIMEOUT_US/10, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 703b50bc5e0f1..dca5de4c6e877 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -341,6 +341,9 @@ struct dw_pcie_rp { struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); + bool use_atu_msg; + int msg_atu_index; + struct resource *msg_res; }; struct dw_pcie_ep_ops {