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This change reduces future dependencies to add 'imx8qm-ss-audio'. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 897cbb7b67422..ff5df0fed9e96 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -447,7 +447,6 @@ dsp: dsp@596e8000 { <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; - memory-region = <&dsp_reserved>; status = "disabled"; }; From patchwork Mon Apr 15 19:46:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630671 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2066.outbound.protection.outlook.com [40.107.105.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E9A915E200 for ; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi | 473 +++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 86 ++++ 2 files changed, 559 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi new file mode 100644 index 0000000000000..ed5a1b4af1d76 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng + */ + +/delete-node/ &acm; +/delete-node/ &sai4; +/delete-node/ &sai5; +/delete-node/ &sai4_lpcg; +/delete-node/ &sai5_lpcg; + +/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ +&edma0{ + reg = <0x591f0000 0x150000>; + dma-channels = <20>; + dma-channel-mask = <0>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* spdif1 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai2 */ + , /* sai3 */ + , /* sai4 */ + ; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>, + <&pd IMX_SC_R_DMA_2_CH16>, + <&pd IMX_SC_R_DMA_2_CH17>, + <&pd IMX_SC_R_DMA_2_CH18>, + <&pd IMX_SC_R_DMA_2_CH19>; +}; + +/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ +&edma1{ + reg = <0x599F0000 0xc0000>; + dma-channels = <11>; + dma-channel-mask = <0xc0>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* no used */ + , /* no used */ + , /* sai6 */ + , + ; /* sai7 */ + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>, + <&pd IMX_SC_R_DMA_3_CH8>, + <&pd IMX_SC_R_DMA_3_CH9>, + <&pd IMX_SC_R_DMA_3_CH10>; +}; + +&asrc0 { + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, + <&asrc0_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_0>; +}; + +&esai0 { + clocks = <&esai0_lpcg IMX_LPCG_CLK_0>, + <&esai0_lpcg IMX_LPCG_CLK_4>, + <&esai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ESAI_0>; +}; + +&spdif0 { + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ + <&clk_dummy>, /* rxtx0 */ + <&spdif0_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ + <&clk_dummy>, /* rxtx2 */ + <&clk_dummy>, /* rxtx3 */ + <&clk_dummy>, /* rxtx4 */ + <&audio_ipg_clk>, /* rxtx5 */ + <&clk_dummy>, /* rxtx6 */ + <&clk_dummy>, /* rxtx7 */ + <&clk_dummy>; /* spba */ + power-domains = <&pd IMX_SC_R_SPDIF_0>; +}; + +&sai0 { + clocks = <&sai0_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai0_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_0>; +}; + +&sai1 { + clocks = <&sai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai1_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_1>; +}; + +&sai2 { + clocks = <&sai2_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai2_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_2>; +}; + +&sai3 { + clocks = <&sai3_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai3_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_SAI_3>; +}; + +&asrc1 { + clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>, + <&asrc1_lpcg IMX_LPCG_CLK_2>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>, + <&clk_dummy>; + power-domains = <&pd IMX_SC_R_ASRC_1>; +}; + +&amix { + dais = <&sai6>, <&sai7>; +}; + +&asrc0_lpcg { + clocks = <&audio_ipg_clk>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk"; +}; + +&esai0_lpcg { + clock-indices = , ; + clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk"; +}; + +&spdif0_lpcg { + clock-indices = , ; + clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw"; +}; + +&sai0_lpcg { + clock-indices = , ; + clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk"; +}; + +&sai1_lpcg { + clock-indices = , ; + clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk"; +}; + +&sai2_lpcg { + clock-indices = , ; + clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk"; +}; + +&sai3_lpcg { + clock-indices = , ; + clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk"; +}; + +&asrc1_lpcg { + clocks = <&audio_ipg_clk>, <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk"; +}; + +&mqs0_lpcg { + clock-indices = , ; + clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk"; +}; + +&dsp_lpcg { + status = "disabled"; +}; + +&dsp_ram_lpcg { + status = "disabled"; +}; + +&audio_subsys { + + acm: acm@59e00000 { + compatible = "fsl,imx8qm-acm"; + reg = <0x59e00000 0x1D0000>; + #clock-cells = <1>; + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, + <&pd IMX_SC_R_AUDIO_CLK_1>, + <&pd IMX_SC_R_MCLK_OUT_0>, + <&pd IMX_SC_R_MCLK_OUT_1>, + <&pd IMX_SC_R_AUDIO_PLL_0>, + <&pd IMX_SC_R_AUDIO_PLL_1>, + <&pd IMX_SC_R_ASRC_0>, + <&pd IMX_SC_R_ASRC_1>, + <&pd IMX_SC_R_ESAI_0>, + <&pd IMX_SC_R_ESAI_1>, + <&pd IMX_SC_R_SAI_0>, + <&pd IMX_SC_R_SAI_1>, + <&pd IMX_SC_R_SAI_2>, + <&pd IMX_SC_R_SAI_3>, + <&pd IMX_SC_R_SAI_4>, + <&pd IMX_SC_R_SAI_5>, + <&pd IMX_SC_R_SAI_6>, + <&pd IMX_SC_R_SAI_7>, + <&pd IMX_SC_R_SPDIF_0>, + <&pd IMX_SC_R_SPDIF_1>, + <&pd IMX_SC_R_MQS_0>; + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, + <&clk_mlb_clk>, + <&clk_hdmi_rx_mclk>, + <&clk_ext_aud_mclk0>, + <&clk_ext_aud_mclk1>, + <&clk_esai0_rx_clk>, + <&clk_esai0_rx_hf_clk>, + <&clk_esai0_tx_clk>, + <&clk_esai0_tx_hf_clk>, + <&clk_esai1_rx_clk>, + <&clk_esai1_rx_hf_clk>, + <&clk_esai1_tx_clk>, + <&clk_esai1_tx_hf_clk>, + <&clk_spdif0_rx>, + <&clk_spdif0_rx>, + <&clk_sai0_rx_bclk>, + <&clk_sai0_tx_bclk>, + <&clk_sai1_rx_bclk>, + <&clk_sai1_tx_bclk>, + <&clk_sai2_rx_bclk>, + <&clk_sai3_rx_bclk>, + <&clk_sai4_rx_bclk>, + <&clk_sai5_rx_bclk>, + <&clk_sai6_rx_bclk>; + clock-names = "aud_rec_clk0_lpcg_clk", + "aud_rec_clk1_lpcg_clk", + "aud_pll_div_clk0_lpcg_clk", + "aud_pll_div_clk1_lpcg_clk", + "mlb_clk", + "hdmi_rx_mclk", + "ext_aud_mclk0", + "ext_aud_mclk1", + "esai0_rx_clk", + "esai0_rx_hf_clk", + "esai0_tx_clk", + "esai0_tx_hf_clk", + "esai1_rx_clk", + "esai1_rx_hf_clk", + "esai1_tx_clk", + "esai1_tx_hf_clk", + "spdif0_rx", + "spdif1_rx", + "sai0_rx_bclk", + "sai0_tx_bclk", + "sai1_rx_bclk", + "sai1_tx_bclk", + "sai2_rx_bclk", + "sai3_rx_bclk", + "sai4_rx_bclk", + "sai5_tx_bclk", + "sai6_rx_bclk"; + }; + + sai4: sai@59080000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59080000 0x10000>; + interrupts = ; + clocks = <&sai4_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai4_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 18 0 1>; + fsl,dataline = <0 0xf 0x0>; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5: sai@59090000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59090000 0x10000>; + interrupts = ; + clocks = <&sai5_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai5_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma0 19 0 0>; + fsl,dataline = <0 0x0 0xf>; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1: esai@59810000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x59810000 0x10000>; + interrupts = ; + clocks = <&esai1_lpcg IMX_LPCG_CLK_0>, + <&esai1_lpcg IMX_LPCG_CLK_4>, + <&esai1_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + status = "disabled"; + }; + + sai6: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59820000 0x10000>; + interrupts = ; + clocks = <&sai6_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai6_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + power-domains = <&pd IMX_SC_R_SAI_6>; + status = "disabled"; + }; + + sai7: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x59830000 0x10000>; + interrupts = ; + clocks = <&sai7_lpcg IMX_LPCG_CLK_0>, + <&clk_dummy>, + <&sai7_lpcg IMX_LPCG_CLK_4>, + <&clk_dummy>, + <&clk_dummy>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + power-domains = <&pd IMX_SC_R_SAI_7>; + status = "disabled"; + }; + + sai4_lpcg: clock-controller@59480000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59480000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_4>; + status = "disabled"; + }; + + sai5_lpcg: clock-controller@59490000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59490000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_5>; + status = "disabled"; + }; + + esai1_lpcg: clock-controller@59c10000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c10000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ESAI_1>; + }; + + sai6_lpcg: clock-controller@59c20000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c20000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_6>; + }; + + sai7_lpcg: clock-controller@59c30000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x59c30000 0x10000>; + #clock-cells = <1>; + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&audio_ipg_clk>; + clock-indices = , ; + clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SAI_7>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index b3d01677b70c4..da49d4bad32ee 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -461,7 +461,92 @@ drc_crit0: trip1 { }; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; + + clk_mlb_clk: clock-mlb-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mlb_clk"; + }; + + clk_esai1_rx_clk: clock-esai1-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_rx_clk"; + }; + + clk_esai1_rx_hf_clk: clock-esai1-rx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_rx_hf_clk"; + }; + + clk_esai1_tx_clk: clock-esai1-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_tx_clk"; + }; + + clk_esai1_tx_hf_clk: clock-esai1-tx-hf { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "esai1_tx_hf_clk"; + }; + + clk_spdif1_rx: clock-spdif1-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "spdif1_rx"; + }; + + clk_sai5_rx_bclk: clock-sai5-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai5_rx_bclk"; + }; + + clk_sai5_tx_bclk: clock-sai5-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai5_tx_bclk"; + }; + + clk_sai6_rx_bclk: clock-sai6-rx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai6_rx_bclk"; + }; + + clk_sai6_tx_bclk: clock-sai6-tx-bclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "sai6_tx_bclk"; + }; + + clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "hdmi-rx-mclk"; + }; + /* sorted in register address */ + #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-img.dtsi" #include "imx8-ss-dma.dtsi" @@ -473,3 +558,4 @@ drc_crit0: trip1 { #include "imx8qm-ss-dma.dtsi" #include "imx8qm-ss-conn.dtsi" #include "imx8qm-ss-lsio.dtsi" +#include "imx8qm-ss-audio.dtsi" From patchwork Mon Apr 15 19:46:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630672 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2066.outbound.protection.outlook.com [40.107.105.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D9F15E5A6 for ; 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Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by PR3PR04MB7290.eurprd04.prod.outlook.com (2603:10a6:102:82::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.50; Mon, 15 Apr 2024 19:47:12 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::1e67:dfc9:d0c1:fe58]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::1e67:dfc9:d0c1:fe58%7]) with mapi id 15.20.7452.049; Mon, 15 Apr 2024 19:47:12 +0000 From: Frank Li Date: Mon, 15 Apr 2024 15:46:39 -0400 Subject: [PATCH 03/10] arm64: dts: imx8qm-mek: add sai and wm8960 support Message-Id: <20240415-dts_8qm_audio-v1-3-2976c35a0c52@nxp.com> References: <20240415-dts_8qm_audio-v1-0-2976c35a0c52@nxp.com> In-Reply-To: <20240415-dts_8qm_audio-v1-0-2976c35a0c52@nxp.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 140 +++++++++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 5c6b39c6933fc..9dd84126493ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -46,6 +46,47 @@ reg_vref_1v8: regulator-adc-vref { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + bt_sco_codec: bt_sco_codec { + #sound-dai-cells = <1>; + compatible = "linux,bt-sco"; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,name = "bt-sco-audio"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,bitclock-master = <&btcpu>; + + btcpu: simple-audio-card,cpu { + sound-dai = <&sai0>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + }; + + sound-wm8960 { + compatible = "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + audio-cpu = <&sai1>; + audio-codec = <&wm8960>; + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Mic Jack", + "Mic Jack", "MICB"; + }; }; &adc0 { @@ -65,6 +106,77 @@ &i2c1 { scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; status = "okay"; + + wm8960: wm8960@1a { + compatible = "wlf,wm8960"; + reg = <0x1a>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + wlf,shared-lrclk; + wlf,hp-cfg = <2 2 3>; + wlf,gpio-cfg = <1 3>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&sai0 { + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai1_lpcg IMX_LPCG_CLK_4>; /* FIXME: should be sai1, original code is 0 */ + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&sai6 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai6_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai7_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + status = "okay"; }; &lpuart0 { @@ -161,6 +273,16 @@ &usdhc2 { }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c @@ -256,6 +378,24 @@ IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 >; }; + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 From patchwork Mon Apr 15 19:46:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630673 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2052.outbound.protection.outlook.com [40.107.105.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4943215E7F7 for ; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi | 68 +++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + 2 files changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi new file mode 100644 index 0000000000000..d715f2a6b0378 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Dong Aisheng + */ + +#include +#include + +cm41_ipg_clk: clock-cm41-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <132000000>; + clock-output-names = "cm41_ipg_clk"; +}; + +cm41_subsys: bus@38000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x38000000 0x0 0x38000000 0x4000000>; + interrupt-parent = <&cm41_intmux>; + + cm41_i2c: i2c@3b230000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x3b230000 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>, + <&cm41_i2c_lpcg IMX_LPCG_CLK_4>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + status = "disabled"; + }; + + cm41_intmux: intmux@3b400000 { + compatible = "fsl,imx-intmux"; + reg = <0x3b400000 0x1000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cm41_ipg_clk>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; + status = "disabled"; + }; + + cm41_i2c_lpcg: clock-controller@3b630000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x3b630000 0x1000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, + <&cm41_ipg_clk>; + clock-indices = , ; + clock-output-names = "cm41_lpcg_i2c_clk", + "cm41_lpcg_i2c_ipg_clk"; + power-domains = <&pd IMX_SC_R_M4_1_I2C>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index da49d4bad32ee..96a940c6046d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -546,6 +546,7 @@ clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { }; /* sorted in register address */ + #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-img.dtsi" From patchwork Mon Apr 15 19:46:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630674 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2052.outbound.protection.outlook.com [40.107.105.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B770215E7E7 for ; Mon, 15 Apr 2024 19:47:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 50 ++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 9dd84126493ef..d321876754e9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -96,6 +96,49 @@ &adc0 { status = "okay"; }; +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + lsm303arg@19 { + compatible = "st,lsm303agr-accel"; + reg = <0x19>; + }; + + fxas21002c@20 { + compatible = "nxp,fxas21002c"; + reg = <0x20>; + }; + + isl29023@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <11 2>; + }; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + l3g4250@69 { + compatible = "st,l3g4200d-gyro"; + reg = <0x69>; + }; +}; + &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -283,6 +326,13 @@ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c >; }; + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c From patchwork Mon Apr 15 19:46:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630675 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2052.outbound.protection.outlook.com [40.107.105.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF84E15FA68 for ; Mon, 15 Apr 2024 19:47:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index d321876754e9b..4b87e13923328 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -222,6 +222,26 @@ &sai7 { status = "okay"; }; +&cm41_i2c { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cm41_i2c>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&cm41_intmux { + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -353,6 +373,13 @@ IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 >; }; + pinctrl_cm41_i2c: cm41i2cgrp { + fsl,pins = < + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c + >; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 80 ++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 4b87e13923328..94a4195d92320 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -40,6 +40,44 @@ reg_usdhc2_vmmc: usdhc2-vmmc { enable-active-high; }; + reg_can01_en: regulator-can01-gen { + compatible = "regulator-fixed"; + regulator-name = "can01-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_en: regulator-can2-gen { + compatible = "regulator-fixed"; + regulator-name = "can2-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can01_stby: regulator-can01-stby { + compatible = "regulator-fixed"; + regulator-name = "can01-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can01_en>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-name = "can2-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can2_en>; + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; @@ -242,6 +280,27 @@ &cm41_intmux { status = "okay"; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can01_stby>; + status = "okay"; +}; + +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; @@ -434,6 +493,27 @@ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 >; }; + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + pinctrl_flexcan3: flexcan3grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 From patchwork Mon Apr 15 19:46:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630677 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2078.outbound.protection.outlook.com [40.107.105.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B19941607A3 for ; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 94a4195d92320..da17161055179 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -260,6 +260,14 @@ &sai7 { status = "okay"; }; +&lsio_mu5 { + status = "okay"; +}; + +&lsio_mu6 { + status = "okay"; +}; + &cm41_i2c { #address-cells = <1>; #size-cells = <0>; From patchwork Mon Apr 15 19:46:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630678 Received: from EUR03-AM7-obe.outbound.protection.outlook.com (mail-am7eur03on2078.outbound.protection.outlook.com [40.107.105.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8795E1607A3 for ; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 96a940c6046d8..734bee4294dfe 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -333,6 +333,21 @@ rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + ocotp: ocotp { + compatible = "fsl,imx8qm-scu-ocotp"; + #address-cells = <1>; + #size-cells = <1>; + read-only; + + fec_mac0: mac@1c4 { + reg = <0x1c4 6>; + }; + + fec_mac1: mac@1c6 { + reg = <0x1c6 6>; + }; + }; + tsens: thermal-sensor { compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; #thermal-sensor-cells = <1>; From patchwork Mon Apr 15 19:46:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13630679 Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2046.outbound.protection.outlook.com [40.107.21.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F5A4161920 for ; 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Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index da17161055179..84372c060e200 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -40,6 +40,15 @@ reg_usdhc2_vmmc: usdhc2-vmmc { enable-active-high; }; + reg_fec2_supply: fec2_nvcc { + compatible = "regulator-fixed"; + regulator-name = "fec2_nvcc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_can01_en: regulator-can01-gen { compatible = "regulator-fixed"; regulator-name = "can01-en"; @@ -382,6 +391,19 @@ ethphy1: ethernet-phy@1 { }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + phy-supply = <®_fec2_supply>; + fsl,magic-packet; + nvmem-cells = <&fec_mac1>; + nvmem-cell-names = "mac-address"; + rx-internal-delay-ps = <2000>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -501,6 +523,24 @@ IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 >; }; + pinctrl_fec2: fec2grp { + fsl,pins = < + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + pinctrl_flexcan1: flexcan0grp { fsl,pins = < IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21