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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Jiri Pirko , Amit Cohen Subject: [PATCH net 1/3] mlxsw: core: Unregister EMAD trap using FORWARD action Date: Tue, 16 Apr 2024 12:24:14 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D5:EE_|DM4PR12MB6376:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fb89957-2f1e-4e02-02c5-08dc5dffbd97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Owur/vghonY1ss/KG+cZ2DYD6Os9cy4FoPtV8HbM9gAnz4ANaEyfb8oh5NpXEdozY6eX39Kx0JXWVx1wA40Bedchr2wI8/NN90E5onDdDeOTitEIUDKzSLexSdNFmsV3tUj1DmniLYnKYgMc+gnp1U3oStJPRkQp1pzY2TS38zyNVugClke7+iHsVLfCABOa/4F+P+zR4OE/oca7Lj84xRccEYpPBVc7ob1s6LX7Ir41SrXU4zEPScguu6488iJXADifbT/oLYiJtmpvmkPM9ECiOy1vB/nOhGLp2A/hOTL9hOxOoDEFYYa/743gSz6lKawUP31f1oIqxC7FMUIcdm0PRsyhiKIblK6BQ2+68ObRLSps5kzOUbA3rN+e/OYY8eW7LVPp2YUzz/89L6rrt8cWPZhtLy4fxmoxvkX9WstH2Iu8OrN4Mov66FTrH1Hl6QGQlCOVvK5vgxrqu0vAJhYjkhhlELp/75IPOlen1Ytf5+pr6VYYuWCtE4Biv15w8qR+AFmyilqiBbEtZdYi6PG/Amd66FCqdYXxDWTR8Posa7exmeAzNk6ii2AGezbafvvCKn9RndloXhJWeuo0jI8g+PbVQvglmXoxsNsM1BlhJPJAAeDnDWJdpg1s5tTrqJ+4yHWi/1RTZPvRi+13onyFCFTOTKKMqYR7KdY5jHqplb2SOVNxXp/d9mCSrVCFSzrtvic1r0Gdo5AM5B9dIdd3JzHQANjHkQ7i0Z7/8mFVnStp0A33kOorm5cqky4o X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(376005)(36860700004)(1800799015);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 10:26:55.7195 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb89957-2f1e-4e02-02c5-08dc5dffbd97 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6376 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The device's manual (PRM - Programmer's Reference Manual) classifies the trap that is used to deliver EMAD responses as an "event trap". Among other things, it means that the only actions that can be associated with the trap are TRAP and FORWARD (NOP). Currently, during driver de-initialization the driver unregisters the trap by setting its action to DISCARD, which violates the above guideline. Future firmware versions will prevent such misuses by returning an error. This does not prevent the driver from working, but an error will be printed to the kernel log during module removal / devlink reload: mlxsw_spectrum 0000:03:00.0: Reg cmd access status failed (status=7(bad parameter)) mlxsw_spectrum 0000:03:00.0: Reg cmd access failed (reg_id=7003(hpkt),type=write) Suppress the error message by aligning the driver to the manual and use a FORWARD (NOP) action when unregistering the trap. Fixes: 4ec14b7634b2 ("mlxsw: Add interface to access registers and process events") Cc: Jiri Pirko Cc: Amit Cohen Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core.c b/drivers/net/ethernet/mellanox/mlxsw/core.c index e4d7739bd7c8..4a79c0d7e7ad 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core.c @@ -849,7 +849,7 @@ static void mlxsw_emad_rx_listener_func(struct sk_buff *skb, u16 local_port, static const struct mlxsw_listener mlxsw_emad_rx_listener = MLXSW_RXL(mlxsw_emad_rx_listener_func, ETHEMAD, TRAP_TO_CPU, false, - EMAD, DISCARD); + EMAD, FORWARD); static int mlxsw_emad_tlv_enable(struct mlxsw_core *mlxsw_core) { From patchwork Tue Apr 16 10:24:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petr Machata X-Patchwork-Id: 13631659 X-Patchwork-Delegate: kuba@kernel.org Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2078.outbound.protection.outlook.com [40.107.220.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47FCE127E04 for ; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Tim 'mithro' Ansell Subject: [PATCH net 2/3] mlxsw: core_env: Fix driver initialization with old firmware Date: Tue, 16 Apr 2024 12:24:15 +0200 Message-ID: <314f08cecbcae00340390e077cf20e02d0b48446.1713262810.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|DM4PR12MB5723:EE_ X-MS-Office365-Filtering-Correlation-Id: 5bc66831-3f00-4fec-efd2-08dc5dffc029 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PQq3a988NJZVWUt98TtBLcjFRzZrDzpwsJ2iE3LUBpxaomRTD5aPbubkwvlDhZQfZFupVXbi6ybDgq20vPhrXeUcJhljdA1IZMdNnTQtJyTxvDyj6dZAZnSiPM52d1WF/SVa6a6DFID94aDh9Z+Q9DQyLvuPXPHvcwMO37AVn/t9ACj/Lx0fyaaL44b+4iCjNVMSrEHaotlbP6v9bq7sNcg8r01nXN07hEdDk75GQs3hVE/DrzxYRd9kq5H6mPcV1tswmtuyZLChvg8Q4aHimCxNNpfcZvNbOsGrCk0xRsfMICu80lpYjqRIfIhEW2lpq/aT9BsKZU3Gw7XvWsAJBa9k4fhiONED0PPH7ZOF4c0VC/WwQVbg4cLOzwQ+3l6RbLh3xonFKegPStLyUT4pCa2G9ED4YwHLpOIUhez4kVKFdtSLzjQr6duSKwb5BuNPZnvPOBLgdnammnwLJkzXpWL8ChZIIAbzIKPpb+5Q9AIn507Q1sFsifwDxsahSlaDxswlv1xcE98/t8gXW11A1942FOXqdNBVQRo/0/hkz2KzykeZWkX1/O57kVVf31J+oGlsBuGFUlSmIoeO+dGNyJpdXDTz2ijJfxTnl4W2Ub0TVSPP01S77dmKpJt5bJwfU6eEif/tQU04y3zrVcPDRfaAS6VmHt81LsaHe9HA5HZU/6UMsWqr6s0z5x7HhBR0lWnjDQayS9/p5cm03GGKKQ2Va2CMj5meEaQE0NcSU8Zo0AViUBxMsLBkZWwdp0FCArD3ddoLewfnZSo1Kzg4ARu+1hrTf0SqyyH828FurL2nJmRzfupDjyhXn28ixSqQlgYSE8hhD/k4YRhtKq/NrBngd3Ze88BTNhHpdw1WBq/eN1zqhlmQTPLF/Y9FuZp8ti2VvfhuFK7/izxYkpCe7rm/1WJ5PV8kHhGqLQoEN7eCGcTLqWTbl2oL4Mdu+bywiMYn4KF/+zLBi0ewpbeprfRWdaJSNHc9gUrout/bKKRNpcdYxax+5vVB6GyaSeqvz5phYT11eUTPPjd0AaquXBpAZKCAtTeX245UGkbCXcFnRujn+aKmKbmTXvcxEF6FrtLXaU6biZK2WUA36plBGoS9HH7Mi0bgfxbBr8SFttFnDsIRTuqq+B+itMB7swY2IryH16fX1NtsVzZsXfCY/SeprtKavWpeQexNpfDYhDAN7sgmhq5+Tf89PiZQIzk5vKT2ybyEj9KkmPBVydWgNsRc5ds2avkKV7f1QsF7nTNhmlMzboqyBnPpMPmz9gmesCnbBmrccbdSpfOenQdRSnIo0KkPicTP1IeRAQrSoGqG1A22edIlTFp+JWKSW4xZgTKEC9p/WhG+mLqNfrvZErdVA3DJAdhk+n5BxzmiSWnxn0p8bIygb3GABfLXrCEH X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(376005)(1800799015)(82310400014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 10:27:00.0066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5bc66831-3f00-4fec-efd2-08dc5dffc029 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5723 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The driver queries the Management Capabilities Mask (MCAM) register during initialization to understand if it can read up to 128 bytes from transceiver modules. However, not all firmware versions support this register, leading to the driver failing to load. Fix by treating an error in the register query as an indication that the feature is not supported. Fixes: 1f4aea1f72da ("mlxsw: core_env: Read transceiver module EEPROM in 128 bytes chunks") Reported-by: Tim 'mithro' Ansell Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/core_env.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/core_env.c b/drivers/net/ethernet/mellanox/mlxsw/core_env.c index 53b150b7ae4e..5d02b6aef4d2 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/core_env.c +++ b/drivers/net/ethernet/mellanox/mlxsw/core_env.c @@ -1360,17 +1360,15 @@ static struct mlxsw_linecards_event_ops mlxsw_env_event_ops = { static int mlxsw_env_max_module_eeprom_len_query(struct mlxsw_env *mlxsw_env) { char mcam_pl[MLXSW_REG_MCAM_LEN]; - bool mcia_128b_supported; + bool mcia_128b_supported = false; int err; mlxsw_reg_mcam_pack(mcam_pl, MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); err = mlxsw_reg_query(mlxsw_env->core, MLXSW_REG(mcam), mcam_pl); - if (err) - return err; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , , Tim 'mithro' Ansell Subject: [PATCH net 3/3] mlxsw: pci: Fix driver initialization with old firmware Date: Tue, 16 Apr 2024 12:24:16 +0200 Message-ID: <449181a5ed544dd4790ae4d650586436848007cd.1713262810.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D3:EE_|CY8PR12MB7363:EE_ X-MS-Office365-Filtering-Correlation-Id: a41ff0b6-3471-4d1a-9e86-08dc5dffc306 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tEQVpm3i8Tr5lLIHBJxgOj4c+6khKS3Hj8/wfOi9Yj0PdgLVzfaJvvzYJ91tCRyCkeP4ml8sqV2TiHKVD0jx13pG60PFlZQatNJ+dsGZgMhQ4vBGlZtbJicYHLG1Ox+n8Jpq1ZsK4TQ5qI1KFCJpe2QPfNvm8tjIEcTsYg7a4yEv9CE9TuTt7GrTUZlce/KpcCdP/PnucFTsPd2NyRusfoy2TYg0uVEQY7ptvY9k0CB9AWAN3DmdIdMN6Bf5fDgY5WB5Yr858v+g602C9NQAIxFjxmergZgeiESKpS0mXXfNeuPCbB6NFUA2nxBdXQKOBTs4L8TaqCsmRupAfep/sW0vxTb+uxBR+7z6Enr8WWdhOr0XSV0X1izky0+fhtzXug81H2hLPOzKe6zo1Zu0053S/xMv5CqHWnBb+mgrUm2ADzdYugjSSS+LSTvvhkZLuOEVn3h+fD52aBzs8tdZzKWvZSjn8PqyaNZHhSLXOye0n8jShp/nklU/i1c6saa/QcPvujrlwVOkc3I1EgkLmWAngkW/exyLYc0BZ70CJMqQie6fIBNs+Xos7eOMaCeDRLqlDLTMVUQYEYK99fBd4e9uGqwdt3sKXwPhT3Y/OrT9x6YhVtEvAUQ3tSBX1IGFY9zEpnLq0Hqi9zr9JwbO4KcksWxEtFaaukNGkwpvUcp1VD0XoHVOgtSyNE90WWG2HVNZH9l4QDmpMLtSJaWUPkKFwvtaGk33bJDHR8BWOjSUYnMBcEX4MgkzFYXczNHz X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400014)(376005)(1800799015)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Apr 2024 10:27:04.8396 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a41ff0b6-3471-4d1a-9e86-08dc5dffc306 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7363 X-Patchwork-Delegate: kuba@kernel.org From: Ido Schimmel The driver queries the Management Capabilities Mask (MCAM) register during initialization to understand if a new and deeper reset flow is supported. However, not all firmware versions support this register, leading to the driver failing to load. Fix by treating an error in the register query as an indication that the feature is not supported. Fixes: f257c73e5356 ("mlxsw: pci: Add support for new reset flow") Reported-by: Tim 'mithro' Ansell Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Signed-off-by: Petr Machata Reviewed-by: Simon Horman Reviewed-by: Kalesh AP --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 4d617057af25..13fd067c39ed 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1545,7 +1545,7 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) { struct pci_dev *pdev = mlxsw_pci->pdev; char mcam_pl[MLXSW_REG_MCAM_LEN]; - bool pci_reset_supported; + bool pci_reset_supported = false; u32 sys_status; int err; @@ -1563,11 +1563,9 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) mlxsw_reg_mcam_pack(mcam_pl, MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES); err = mlxsw_reg_query(mlxsw_pci->core, MLXSW_REG(mcam), mcam_pl); - if (err) - return err; - - mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, - &pci_reset_supported); + if (!err) + mlxsw_reg_mcam_unpack(mcam_pl, MLXSW_REG_MCAM_PCI_RESET, + &pci_reset_supported); if (pci_reset_supported) { pci_dbg(pdev, "Starting PCI reset flow\n");