From patchwork Thu Apr 18 12:42:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BAC08C04FFF for ; Thu, 18 Apr 2024 12:44:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rpjKXLO5Q6SsZKaE3AH0eTr2hOj6DhjDDic3317KYkE=; b=sM77fmr8ibnB/8 ynlI0wtgdkwXO/tKGlZUVvtvyjrQEouILCES9IEqdnOjVdMy0JLeWOHsHyMhcEqaEZRvV5Gj8GLmU VXVXclHKx2dzTn2UhvXNWcpRNAiRgK5C2nMeU9Fa1/g8Y2p93bfrdE7VmRvS+F3MaQCArEscvHCgk JGr3UzTyAOwI2oe35pOlLAZ1Bayzc/ezyKvBa3DWmoGX95vsv6JcAl7zfL2uvuY7U/JA9q/fJbnvm C+zq/Q76+x0hlf+AI+Au0Hu4kcD9tfjSAf2dlz/Hf46cGIcwAqPlE64DiHaBylGSBz3vnYfN9zaZ7 PLJucW+0JSC3VAX7rXSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Z-00000002CZy-0FYr; Thu, 18 Apr 2024 12:44:09 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Q-00000002CRJ-0O9o for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:03 +0000 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-347c6d6fc02so116276f8f.1 for ; Thu, 18 Apr 2024 05:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444235; x=1714049035; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zrjU6l9W7DikYIaMYJG/SdZ2oUTcGtwCnDHe7Ekc7IE=; b=NuWAM3kDbx8VequTg93+Qo1r4b7sTaAVBx/d0NmHVpQhg01ajHoXxXCUclA8B5C+MW qi1py/TVNEcX8LeB3tKeTKdhnbVrId9Laxd6OROuM+dVTE0bkoyPM7WYC2tmA+Nfyae/ kQQI1I60so8otLtVH34ANkyB8RfYSWa4zKBa4Ob2HmTvj/8wF0i/gUQCYTQbfspNlgfN S49dn8svv0ZJ9NCX1PpIkg7lJ3nWjkCggpb9/PGD3y5D6SbBRm4ZRP8zN8s04C1+3eF4 lw9Q0Z82tAJ6ZqP6/uRapxX5zDaA58LS2IrZ4v8fYDf1BnQ3Yr3NswJ1sB9q1afATDBj rh4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444235; x=1714049035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zrjU6l9W7DikYIaMYJG/SdZ2oUTcGtwCnDHe7Ekc7IE=; b=cRPFznlH/WYgSbRy7/+pN8TBDquH6lbXjfDtGTjSxUh5RXyLYnQbjTuNCP3MR4xTs9 JmDWCrntm6plrSVie1d6XZZfRV6palbme2kWd3hyXK2eXdysAlen+eHGdTq8ci9JWxWp tF1aZ5hzWWg1f7Ahx6E3jjdx6XvW7BSoSnrQmI+YL/q2vaigMwlB7pH1dz8HfTPKJA1S yHs6jaStsTgJn6XInuxfLBVVd4u2SOtCXq1zJn/zmEojrCU9hlTPF9QCU1N4CaTRWfl+ iuUcpD1YJJDCx/8DlTcE/lKC6U3HI/A0JhxdnvR6oSDDXt4lWPnzBiU17/lktMxivUhP Iu5g== X-Forwarded-Encrypted: i=1; AJvYcCX8bMn0GH+s2t3YDERzlhrdxbsEaaptyxmzplGphfm+Jbbm2by4AxZZYh9Z0mxOT/I2/9Ce4gsADQcwqkRm95F7YxWLZZWuyuZ9Kv6iBS5w X-Gm-Message-State: AOJu0YxtfpNCR/dWvLzSIncuHfT+avVtBp48DfLrCeuw/bMHVyohBuLQ eK2Pg/mPc1TYoj9/ho9cb6osmm0kHcbQAtCxMa7PVK3NmZWLxOnGwomdsv29/BI= X-Google-Smtp-Source: AGHT+IFFx4DMJCN/eGlinw4D8WxSb2s5Led6zbc0ypunbHRPKVqfx9J88kY5VuS8nvJuPPTEq99jAg== X-Received: by 2002:a05:600c:55d7:b0:418:ef65:4b5f with SMTP id jq23-20020a05600c55d700b00418ef654b5fmr805438wmb.3.1713444235113; Thu, 18 Apr 2024 05:43:55 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:54 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 01/12] dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description Date: Thu, 18 Apr 2024 14:42:24 +0200 Message-ID: <20240418124300.1387978-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054400_319807_9B4F36C0 X-CRM114-Status: GOOD ( 10.67 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add description for Zca, Zcf, Zcd and Zcb extensions which are part the Zc* standard extensions for code size reduction. Additional validation rules are added since Zcb depends on Zca, Zcf, depends on Zca and F, Zcd depends on Zca and D and finally, Zcf can not be present on rv64. Signed-off-by: Clément Léger Reviewed-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 616370318a66..db7daf22b863 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -220,6 +220,38 @@ properties: instructions as ratified at commit 6d33919 ("Merge pull request #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. + - const: zca + description: | + The Zca extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcb + description: | + The Zcb extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcd + description: | + The Zcd extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + + - const: zcf + description: | + The Zcf extension part of Zc* standard extensions for code size + reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on + RV64 as it contains no instructions") of riscv-code-size-reduction, + merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed + of zc.adoc to src tree."). + - const: zfa description: The standard Zfa extension for additional floating point @@ -489,5 +521,51 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + allOf: + # Zcb depends on Zca + - if: + contains: + const: zcb + then: + contains: + const: zca + # Zcd depends on Zca and D + - if: + contains: + const: zcd + then: + allOf: + - contains: + const: zca + - contains: + const: d + # Zcf depends on Zca and F + - if: + contains: + const: zcf + then: + allOf: + - contains: + const: zca + - contains: + const: f + +allOf: + # Zcf extension does not exists on rv64 + - if: + properties: + riscv,isa-extensions: + contains: + const: zcf + riscv,isa-base: + contains: + const: rv64i + then: + properties: + riscv,isa-extensions: + not: + contains: + const: zcf + additionalProperties: true ... From patchwork Thu Apr 18 12:42:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E8300C4345F for ; Thu, 18 Apr 2024 12:44:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=lW4yez1MtTQLEnDgTasLhk4u76EmV3SMxP7No79F3vg=; b=dsE9bXLGskU8qg MgOaF3wTnZN8FPZ6pSxMKgAfVcPeAynH/dutB+keYpfHzrLmdBAXfkvfSboDsAMVBRIVZBId5xQRv eJeCsJnpKzTxzf2Xu1XH9YgIILLQ4pRbKudZWRmdj/2yh6iZKE5mydtOhRBew9Ck4qxrdGkh8wLu3 yEraNGOwjQXLb1H3Xs8K9cxU1H2HAvy4hE2JlpWEjphAObe6kxbZ5vEGJj8Qo5oPSj4DZOMDlDRn8 EaDQyt9H9PVyjyfpNE+MIx2XYg1xXwDwhChXoOzicRL3XqSRSyDA9Pt17sxTLvuvrhYj00fzRnweh OvmnilhXWxxwt7/krGtQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7n-00000002CnG-3n8a; Thu, 18 Apr 2024 12:44:23 +0000 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Q-00000002CRM-14m5 for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:07 +0000 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-349a35ae298so80021f8f.2 for ; Thu, 18 Apr 2024 05:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444236; x=1714049036; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oAl9pLtTmdQ7M+Wok6zdTTXvycSGmEGoH9Hb6PFq4BA=; b=EzHiWobbXpSXUHf0EAeOWQuDIVSAdSS41rj0YDVBo17Czk/9QzXjZ9BeIUhFaJYCNa bY320fgwADOmhhNdYWmBptigtI47Vykwuwn+Muw40SUvb1hExUKXxx7Hrx5FeXziUdxX tA+G+8xhBZlc6LRVBZ/Xql7uDeGA/bbRAZsCJllEuqeMfc65kl1NV9yzpGNf9iimUmrV L9fW8IJyHy5UCGmnY9SoAk5AntmL78W1DoZdJkUeyXZNhsRcr3iHW0UJE2qSjWYPajxn C1p3OOuh+Qo7PsYvUW6z8woP3729Dr7+bH4IVHYl/PaQ2+0StfrHtXxqYv+IzJ+dk/JM e8UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444236; x=1714049036; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oAl9pLtTmdQ7M+Wok6zdTTXvycSGmEGoH9Hb6PFq4BA=; b=IStMLs1U/5RU6U68SzwnbTKEMa2r2TDhuMYQXuAesUevIYhrMa0zpqou/dADavR+wi EYz0YcBItfJcWJYdfEDKA/tgxve7mjak9Tn9spuXZEFd/WwD+7x6Wt5RTpsSd2+oroq3 L+Jhi+5icVofcxeo1yRpjl+Et2bvxHwL2/eBIsgQLjp/Ju05p2cAuAkTnM9qYsHo1xGC ngaCJ2fOHCjNXBCIyykY/L9Qlbbtf1ClOAnFRH2wOKrthPlH3isfY+azGJsoDKJZsIWw fxHegdNJbIUEMumUUOrMAYWcF/bUQBbd1eaooxnxMB/O9bu77mQbEglvMiAYhq1ecfUb 0EMQ== X-Forwarded-Encrypted: i=1; AJvYcCXf/9GsEf0lupXmfR8NtN26De3EePAmA8yU1S9rdy8sup6XrgzS31Xmyk6mWdPWEsRVgVqibBQ6xLzm14ZGghTjoPIzL9O3Wpvzc8N/M3v6 X-Gm-Message-State: AOJu0Yxl2mtIt7bu68AXsmyTtbjIkXMpQfvSp36pINWAJvPNx+u9rbAl kEXCbVUV6ruNtIb1/UH8hryEAOpVmfHC5z/Qg/6VDyE7TZsn5zFBU90XufkS3Eo= X-Google-Smtp-Source: AGHT+IFKhZshgTTpNugctUIBKjo1ziNnne6N8VGVQW4Spy090KZRQKoznik9yMPwCUs6CVPn34LP8A== X-Received: by 2002:a5d:5989:0:b0:34a:513:5c46 with SMTP id n9-20020a5d5989000000b0034a05135c46mr1797065wri.5.1713444236215; Thu, 18 Apr 2024 05:43:56 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:55 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 02/12] riscv: dts: enable Zc* extensions when needed Date: Thu, 18 Apr 2024 14:42:25 +0200 Message-ID: <20240418124300.1387978-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054400_437803_292F172F X-CRM114-Status: GOOD ( 11.24 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Zc* spec states that: "The C extension is the superset of the following extensions: - Zca - Zcf if F is specified (RV32 only) - Zcd if D is specified As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only)" Add these extensions to existing device-trees that contains "c" extension in "riscv,isa-extensions". Signed-off-by: Clément Léger --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 4 +- arch/riscv/boot/dts/microchip/mpfs.dtsi | 20 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 +- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 20 +- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 4 +- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 +++++++++--------- arch/riscv/boot/dts/starfive/jh7100.dtsi | 8 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 +- arch/riscv/boot/dts/thead/th1520.dtsi | 16 +- 10 files changed, 186 insertions(+), 186 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..05e0e5f0eed7 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 9883ca3554c5..82ac84afdda7 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -24,8 +24,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -53,8 +53,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -115,8 +115,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -146,8 +146,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index f35324b9173c..b5e06fbfdf65 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -26,8 +26,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm", "xandespmu"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm", "xandespmu"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 156330a9bbf3..2872515dab17 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -31,8 +31,8 @@ cpu0: cpu@0 { reg = <0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -57,8 +57,8 @@ cpu1: cpu@1 { reg = <1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -84,8 +84,8 @@ cpu2: cpu@2 { reg = <2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -111,8 +111,8 @@ cpu3: cpu@3 { reg = <3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -138,8 +138,8 @@ cpu4: cpu@4 { reg = <4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 6150f3397bff..4336ed11db9a 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -32,8 +32,8 @@ cpu0: cpu@0 { reg = <0x0>; riscv,isa = "rv64imac"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zca", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -59,8 +59,8 @@ cpu1: cpu@1 { reg = <0x1>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -86,8 +86,8 @@ cpu2: cpu@2 { reg = <0x2>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -113,8 +113,8 @@ cpu3: cpu@3 { reg = <0x3>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -140,8 +140,8 @@ cpu4: cpu@4 { reg = <0x4>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 2d6f4a4b1e58..1fa5c57acf48 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -28,8 +28,8 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..6d03076314aa 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -259,8 +259,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -284,8 +284,8 @@ cpu1: cpu@1 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -309,8 +309,8 @@ cpu2: cpu@2 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -334,8 +334,8 @@ cpu3: cpu@3 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -359,8 +359,8 @@ cpu4: cpu@4 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -384,8 +384,8 @@ cpu5: cpu@5 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -409,8 +409,8 @@ cpu6: cpu@6 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -434,8 +434,8 @@ cpu7: cpu@7 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -459,8 +459,8 @@ cpu8: cpu@8 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -484,8 +484,8 @@ cpu9: cpu@9 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -509,8 +509,8 @@ cpu10: cpu@10 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -534,8 +534,8 @@ cpu11: cpu@11 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -559,8 +559,8 @@ cpu12: cpu@12 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -584,8 +584,8 @@ cpu13: cpu@13 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -609,8 +609,8 @@ cpu14: cpu@14 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -634,8 +634,8 @@ cpu15: cpu@15 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -659,8 +659,8 @@ cpu16: cpu@16 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -684,8 +684,8 @@ cpu17: cpu@17 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -709,8 +709,8 @@ cpu18: cpu@18 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -734,8 +734,8 @@ cpu19: cpu@19 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -759,8 +759,8 @@ cpu20: cpu@20 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -784,8 +784,8 @@ cpu21: cpu@21 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -809,8 +809,8 @@ cpu22: cpu@22 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -834,8 +834,8 @@ cpu23: cpu@23 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -859,8 +859,8 @@ cpu24: cpu@24 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -884,8 +884,8 @@ cpu25: cpu@25 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -909,8 +909,8 @@ cpu26: cpu@26 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -934,8 +934,8 @@ cpu27: cpu@27 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -959,8 +959,8 @@ cpu28: cpu@28 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -984,8 +984,8 @@ cpu29: cpu@29 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1009,8 +1009,8 @@ cpu30: cpu@30 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1034,8 +1034,8 @@ cpu31: cpu@31 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1059,8 +1059,8 @@ cpu32: cpu@32 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1084,8 +1084,8 @@ cpu33: cpu@33 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1109,8 +1109,8 @@ cpu34: cpu@34 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1134,8 +1134,8 @@ cpu35: cpu@35 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1159,8 +1159,8 @@ cpu36: cpu@36 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1184,8 +1184,8 @@ cpu37: cpu@37 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1209,8 +1209,8 @@ cpu38: cpu@38 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1234,8 +1234,8 @@ cpu39: cpu@39 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1259,8 +1259,8 @@ cpu40: cpu@40 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1284,8 +1284,8 @@ cpu41: cpu@41 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1309,8 +1309,8 @@ cpu42: cpu@42 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1334,8 +1334,8 @@ cpu43: cpu@43 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1359,8 +1359,8 @@ cpu44: cpu@44 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1384,8 +1384,8 @@ cpu45: cpu@45 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1409,8 +1409,8 @@ cpu46: cpu@46 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1434,8 +1434,8 @@ cpu47: cpu@47 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1459,8 +1459,8 @@ cpu48: cpu@48 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1484,8 +1484,8 @@ cpu49: cpu@49 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1509,8 +1509,8 @@ cpu50: cpu@50 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1534,8 +1534,8 @@ cpu51: cpu@51 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1559,8 +1559,8 @@ cpu52: cpu@52 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1584,8 +1584,8 @@ cpu53: cpu@53 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1609,8 +1609,8 @@ cpu54: cpu@54 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1634,8 +1634,8 @@ cpu55: cpu@55 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1659,8 +1659,8 @@ cpu56: cpu@56 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1684,8 +1684,8 @@ cpu57: cpu@57 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1709,8 +1709,8 @@ cpu58: cpu@58 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1734,8 +1734,8 @@ cpu59: cpu@59 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1759,8 +1759,8 @@ cpu60: cpu@60 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1784,8 +1784,8 @@ cpu61: cpu@61 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1809,8 +1809,8 @@ cpu62: cpu@62 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1834,8 +1834,8 @@ cpu63: cpu@63 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "zicntr", "zicsr", "zifencei", - "zihpm"; + "zca", "zcd", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 9a2e9583af88..7e53c539c871 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -35,8 +35,8 @@ U74_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -64,8 +64,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 4a5708f7fcf7..f01024f50561 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -29,8 +29,8 @@ S7_0: cpu@0 { next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zca", "zicntr", + "zicsr", "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { @@ -58,8 +58,8 @@ U74_1: cpu@1 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -91,8 +91,8 @@ U74_2: cpu@2 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -124,8 +124,8 @@ U74_3: cpu@3 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -157,8 +157,8 @@ U74_4: cpu@4 { next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", - "zicsr", "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zca", + "zcd", "zicntr", "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 8b915e206f3a..530355bda7c1 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -21,8 +21,8 @@ c910_0: cpu@0 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -45,8 +45,8 @@ c910_1: cpu@1 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -69,8 +69,8 @@ c910_2: cpu@2 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -93,8 +93,8 @@ c910_3: cpu@3 { device_type = "cpu"; riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", "zcd", "zicntr", + "zicsr", "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; From patchwork Thu Apr 18 12:42:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E467DC4345F for ; Thu, 18 Apr 2024 12:44:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5pBHJ1lBchkAtQHBJAd9vlorc90utg0eQl0H019JnX8=; b=1k6wU53WukbTZo 6xr3xmEg9yEF6Fyc5Hlc99yhdE2PCL2xDFdmOCUgzTJCP5D1wB9G+Nd9voIrDr+SS/dI8PuCfz2VE +nz8lzi/DrsQls+bqgkn6aSExzJMb65aecYa81nQKX5hMqq7aJM5DmFZsTZD93O2i+wei2AhD3qfk Bb7DKG1BmKom10+H/Cpgq/Ck3T9kd9nZlp849EZpsnJuxYhbocXqG0lNVQ/m+64eAAPiX6mIPzmU8 rXgHurnUeb7ofA05foIYExwJSjsyaTqHnRIojvD/pstS0YtsUAvYrpBMGgwwyYvyY3nbLLtTsqqgR mqfzl0vRLrc1gQaccuLg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7X-00000002CXz-0KDs; Thu, 18 Apr 2024 12:44:07 +0000 Received: from mail-lj1-x22a.google.com ([2a00:1450:4864:20::22a]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Q-00000002CRO-04rT for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:02 +0000 Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2d9f829d398so1957631fa.0 for ; Thu, 18 Apr 2024 05:43:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444237; x=1714049037; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VqinG7vx90NXqlB3cCAWzb6LZzjfwkXKYqGSSxQF2QU=; b=ehXSDB06S/Jdq+rbJDNIFRszt7gqHSFCRbGAQ0DD3ppmJMjkDrohLKK5uz2BxZ8H5i qd1IkoA0HiOIEpn0iY0Molwf+jGnO4ArgLVVW0NqGigLUhmz0EfZNAS6/6Az53PmRM3t vtmp1x1EAroVnUQxMUO//BAEI/CPGtBPM4B9fA91A/jDLpLiTCSybfUJd1LVsEnn2+zO zAxGuB1yTlN5YnotjKb3OLJWUllAheEfYHfUcfYpyzho1uCzYt8un/1UDtm02YU5phTJ SM7euEgn++ObUbRGLFrvOkPRSBWk/gJR2V9MOzxcpdH2DO6wKoRTGbtNHxUbQNTgWcDm K0sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444237; x=1714049037; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VqinG7vx90NXqlB3cCAWzb6LZzjfwkXKYqGSSxQF2QU=; b=ht945H/JHISbrpcpTLkkNiTdlDQylq1M8bo/EXqFd66IfiWorbraYJR4fwGyqX1XIs PLcohzbemWIquu3JxZ5mrs7Z0N+EYxkVCfPJb2ClTxXrO6zHBsDwnLK8pa6L9nD4Jftg CfZ5JrAphnPsX1uKJ+ONaOpc6uVSKLMLGQUECWNDns8bU3zyWkLAjB6kAzqwgPcaqrqy exYxBZ1VdEOwZIIzPCSXJycPQ0O8eMWOWBdIMtox+7GpLD3F8qKKCpkqyfWjXV72HaPE e59oVeFGpya7xyAU8X1PPU6rWjjlaacZj1eVcr4jRAhdZeLWXZFMzzLwNEu9sVFY+1rn TNdQ== X-Forwarded-Encrypted: i=1; AJvYcCVv06IGWuOE74DlUJjrRxBVfPlyaXGCdmi6llplHYQgsbVEBqt3cgcjY3ngNdDiWWmLH37tlxTRxkQ11L+D3uqAG9RKtqOfJa+nWck+wNa5 X-Gm-Message-State: AOJu0YwFBpEBj7Zs9LU52RudvKKtLP1jO3eq6PnnfZAxOaaeUe2AixWO UWwZ7THbRtHXkZ/Hf/0wlvq5JlmaelH7V7E+Z/lhJRndbsKlkgrTrT7oM+XqUqQ= X-Google-Smtp-Source: AGHT+IFXBu2QshCmevcqDNI9qC29EYmJ3ZQBbQK0N8BE6U3hHj6+0OsosVqzAbOLR3+7A5/jwaHB/w== X-Received: by 2002:a2e:8387:0:b0:2d6:c59e:37c0 with SMTP id x7-20020a2e8387000000b002d6c59e37c0mr1507578ljg.2.1713444237161; Thu, 18 Apr 2024 05:43:57 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:56 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 03/12] dt-bindings: riscv: add Zc* extension rules implied by C extension Date: Thu, 18 Apr 2024 14:42:26 +0200 Message-ID: <20240418124300.1387978-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054400_092131_ED38A6EB X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org As stated by Zc* spec: "As C defines the same instructions as Zca, Zcf and Zcd, the rule is that: - C always implies Zca - C+F implies Zcf (RV32 only) - C+D implies Zcd" Add additionnal validation rules to enforce this in dts. Signed-off-by: Clément Léger --- .../devicetree/bindings/riscv/cpus.yaml | 8 +++-- .../devicetree/bindings/riscv/extensions.yaml | 34 +++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..c4e2c65437b1 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -168,7 +168,7 @@ examples: i-cache-size = <16384>; reg = <0>; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "c"; + riscv,isa-extensions = "i", "m", "a", "c", "zca"; cpu_intc0: interrupt-controller { #interrupt-cells = <1>; @@ -194,7 +194,8 @@ examples: reg = <1>; tlb-split; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd"; cpu_intc1: interrupt-controller { #interrupt-cells = <1>; @@ -215,7 +216,8 @@ examples: compatible = "riscv"; mmu-type = "riscv,sv48"; riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zca", + "zcd"; interrupt-controller { #interrupt-cells = <1>; diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index db7daf22b863..0172cbaa13ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -549,6 +549,23 @@ properties: const: zca - contains: const: f + # C extension implies Zca + - if: + contains: + const: c + then: + contains: + const: zca + # C extension implies Zcd if d + - if: + allOf: + - contains: + const: c + - contains: + const: d + then: + contains: + const: zcd allOf: # Zcf extension does not exists on rv64 @@ -566,6 +583,23 @@ allOf: not: contains: const: zcf + # C extension implies Zcf if f on rv32 only + - if: + properties: + riscv,isa-extensions: + allOf: + - contains: + const: c + - contains: + const: f + riscv,isa-base: + contains: + const: rv32i + then: + properties: + riscv,isa-extensions: + contains: + const: zcf additionalProperties: true ... From patchwork Thu Apr 18 12:42:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0ED78C04FFF for ; Thu, 18 Apr 2024 12:44:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8DPQTJ9I3jZBDPwr2IK6SJhiJXDEATrFX6C7Ib9c0cM=; b=ac5nA84zg0XaR6 yeMmzpD7EDo9EdU+y72W3lBXsIvtbVFbIRIWdzhDwVoxyFEQML06cqoDeCvl0Qc5b9L5o2B5qsQzU XUCJUidlfriUTntioJaJZsjsc4Q0qQshBpVENxVNxfilsJICjwI8+BXVSkxuVQSvrPgjZNJjwIYeb 0N9efBf6VgDsznI4lJuOeHCpXzdDcnprEf+CPTi/BJUJULThCW9BbPP8CjDWkO2mfrH27xUHYzM1P RNrZO1mxOvwUwcVA8lTZWiJ9fLCt3QGZzqzt7ntvd8+ivH9sqYpYNLyDUgdBx1mYa8gXr7zr3lbgn E8saJF9bzXHzMbtT8uig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7p-00000002CpM-3tjd; Thu, 18 Apr 2024 12:44:25 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7U-00000002CRV-3fUK for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:08 +0000 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-349bd110614so143260f8f.3 for ; Thu, 18 Apr 2024 05:44:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444239; x=1714049039; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hAM+PbC/Wqgx6Q9RB0x39wuP2KdW0QgVrrLDnXaQ5i0=; b=wnVYidbXmNp1IhU/WYnCVFMlBTc+hKwJd6BPRESneAq+ZgFkfXOlEVs3/HMeoYaEgZ FzGKlrDDz3Sa2wPciQpU0IxW26FJixABu89QKnlqN404iXcorJwueFcs1eImRUavSkQD CIjGt03ekqiQ/601MHAD/0hinNZbyEUoZWkKOJtsiC/kpUGtRHXw3hr/yz78SZNPDIdT QfY3cgN194Qy3oA09WpBBXQZHCg5S6UhUzMp0MIacA+RmbOYG3JhGTLLgnKLdLHgDqNW oTl2KmmUVrSFgheDanRUpK3hkzV6GBtOr8ScPv6k7O+bT1H18BH0hBVw7Sa+vJD5u4l1 rqIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444239; x=1714049039; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hAM+PbC/Wqgx6Q9RB0x39wuP2KdW0QgVrrLDnXaQ5i0=; b=YGh1Yr652jRlMYQVTzOR/t4HUiH+u2HQFJ2boc0CIpjrf2jCGf1vOTam0uDwGiKY7g Wsa6yHjiiEliKxsW8dySWBIPY5E8pycAw6CrvUGM59lm0G2P3x/bb6AdUxeyiuye6n/J tLKJ6hmSimHWCmf8pvSAPakTwvDZM0JDmbiTwPSw6Not5QFL033Tg4KQHPe4MQAO0l90 nswfC6PaeBzl5aE5Y1xfPcn2QwSNUjtwd5HiAhB+YQU/uz/2Myaf7vz4Tm752geTh37B eSKtx1GSHMkr0jRL5u/Z90S03nAoZgI3f3pqKMdNPFi5FGazKF6okLzGq22VWWzJUl8L BtDA== X-Forwarded-Encrypted: i=1; AJvYcCUkN72CfDXAC/EL3/oCuAwM0tYhBrlD7GtBTgnQ4X0M8BKghECzXXTc78C4MEmHanRwuJFTvg4TBwX4ckr4/tl14LU8mz271/DHgKZOt/bV X-Gm-Message-State: AOJu0Yzf0PujKcDgPogVLPyXvxrCueoAMYDbF7f2kHnDdq838PypJONn aaksJ4T/wK5rGgBlxerxvOsC/n1kP61K/ZO0GBdwD+1TPbcWkOkvvrTfIc1hL7w= X-Google-Smtp-Source: AGHT+IEfRUjBsR081et3wJOadMgBsrPT+MF87MwTDvd2ymBdOvFDiLCp8AN/vnIfSdOc1TYzaATntQ== X-Received: by 2002:adf:f60c:0:b0:343:3f59:c97e with SMTP id t12-20020adff60c000000b003433f59c97emr1553063wrp.6.1713444238851; Thu, 18 Apr 2024 05:43:58 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:57 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 04/12] riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb Date: Thu, 18 Apr 2024 14:42:27 +0200 Message-ID: <20240418124300.1387978-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054404_965787_F7872521 X-CRM114-Status: UNSURE ( 9.89 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The Zc* standard extension for code reduction introduces new extensions. This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp are left out of this patch since they are targeting microcontrollers/ embedded CPUs instead of application processors. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 543e3ea2da0e..b7551bad341b 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -82,6 +82,10 @@ #define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_XANDESPMU 74 #define RISCV_ISA_EXT_ZIMOP 75 +#define RISCV_ISA_EXT_ZCA 76 +#define RISCV_ISA_EXT_ZCB 77 +#define RISCV_ISA_EXT_ZCD 78 +#define RISCV_ISA_EXT_ZCF 79 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 115ba001f1bc..09dee071274d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -261,6 +261,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), + __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), + __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), + __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), From patchwork Thu Apr 18 12:42:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9B7CBC4345F for ; Thu, 18 Apr 2024 12:44:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Mpp8vDXHvWCNWcnO8chuwNr0iqFKl6zBeS5SpExdTM4=; b=wDgV0/Ai2g1wlL ydyJvajUL08ynuZ0wM5OSplf09C4aHYCSPNjUtzRo3e1AYZ2SD6sorGyB2s1g8Aov+ZWYu/NJ6Uk1 g4gL7tCb4uHsqUEDRD9CgLnQTcv6CIevaQGs9f1Xgg3010rXuHZ9pDgBaF8TUUPpjzFgYzAHUiXyu 9cp8nTAEbAAvW7Shps8//tPSmOmTbU8lW7Om1vXf3rQkO/T2/q2ChNnHdgTpqqFl9q7HPdZQVkd2f 409tClvWVHq9lD0vqecQWcF9RwkuuXl9VQF5ryaHlOKVBu+PB0rj9M9EvBwQSsIk4k0o7Amvf9WsC K250r05htA2IeIF/aBkA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7g-00000002ChG-3J14; Thu, 18 Apr 2024 12:44:16 +0000 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7U-00000002CSg-2PUU for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:07 +0000 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-349a31b2babso94919f8f.2 for ; Thu, 18 Apr 2024 05:44:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444240; x=1714049040; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t82SHWSKnQwBrCB557sYOimgSCzDvuCob+i4t0Pqx/Q=; b=hiwvMnD9wVVFPdsdVjLO8J32Otc2VNJVmrREegGNcfgFoozQEynFEz83d8DqpMrVHE wcXbfYuOOS4ZbbTVuWxGqZy4oPj+DS9Y1PLcmhRTttP0jvO7sSxmOemtgQaoF9Txa0zP 0iR0Ij/lyoN+aHiq5BVO8PQe2xBlnh7G+FlBRmU3M0VziwEioKYWntonMl7sAfJi1A9D cpDJD8rQkR3c3OqGmNPB0WTPY6ecqBWADPkYdGBwHuftEXONB6ncO6Yr2Z8p2o/GbXkA zNKrR5oUPK8PJFyHU5jxC4g+25RsJWs++Lit3YvoX7sSn/v1LmNfZY0Y/kZyH5aPSZcL S1yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444240; x=1714049040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t82SHWSKnQwBrCB557sYOimgSCzDvuCob+i4t0Pqx/Q=; b=aXTOmK7kz76AwYkGhIPS2ibvV/PTtGJuWlSTMDxWPEX7dArGv2a1nCn9Xz7Z34pStH n37GKgUrsCefGBDjVCUTG/YEQstV7X9gWMWYLNdEikAKV6pFLPcCStFfrG6YHj5eTGL4 Yy8rKw+cxGt6vgJmV6d+J/KGlbEgz3M91fEuIS3Hut2geZef8cM8KN4KO5pk3rc8QBA5 +nZSlt181oVTJ7zXE8fM1xKoBzjf6rMoSKQi15oor34ELGVqQAGrSnhFwCfGgUr38x4u Ye/fPczI9BnQERHTZxfDTzwwhCxCyJ7raPZLmJ2wEBpBhrquBA97USnjmZFOd4afZBpA 5M5g== X-Forwarded-Encrypted: i=1; AJvYcCUal8zfuX9PJ7EIblVoAhY06uEzWHNZWDLM2RmjUTZHDlU6G0qKKYaVb60NJIL1K+7ZWoQ55giHdUIXellU/8xY49Hlj/R7mwefZxmP334E X-Gm-Message-State: AOJu0YzxN1qplH/XvDFSXaenqJtqLaIZT7Zo53pg93+/hxCILO3Qlvsj SGcpS1eQWOHSIy4L4YUYydqMNXNGKttJZSJoms34qQOJIUPeZl1m4edtkO4/S0k= X-Google-Smtp-Source: AGHT+IErS9LwS4/40J0dhVyrk/U2WpAaf5Tm6m07tMubctlbr1giuR0xo76AOxJlKf5jHdgFbxuJkw== X-Received: by 2002:a05:600c:5101:b0:416:a773:7d18 with SMTP id o1-20020a05600c510100b00416a7737d18mr1843734wms.0.1713444239836; Thu, 18 Apr 2024 05:43:59 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:43:59 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 05/12] riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions Date: Thu, 18 Apr 2024 14:42:28 +0200 Message-ID: <20240418124300.1387978-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054404_730917_50E89E00 X-CRM114-Status: GOOD ( 10.57 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ arch/riscv/kernel/sys_hwprobe.c | 4 ++++ 3 files changed, 28 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 9ca5b093b6d5..bf96b4e8ba3b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -192,6 +192,26 @@ The following keys are defined: supported as defined in the RISC-V ISA manual starting from commit 58220614a5f ("Zimop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + + * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index ac6874ab743a..dd4ad77faf49 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -60,6 +60,10 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 36) +#define RISCV_HWPROBE_EXT_ZCA (1ULL << 37) +#define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) +#define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) +#define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index c99a4cf231c5..2ffa0fe5101e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -112,6 +112,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZACAS); EXT_KEY(ZICOND); EXT_KEY(ZIMOP); + EXT_KEY(ZCA); + EXT_KEY(ZCB); if (has_vector()) { EXT_KEY(ZVBB); @@ -132,6 +134,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZFH); EXT_KEY(ZFHMIN); EXT_KEY(ZFA); + EXT_KEY(ZCD); + EXT_KEY(ZCF); } #undef EXT_KEY } From patchwork Thu Apr 18 12:42:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 850A0C4345F for ; Thu, 18 Apr 2024 12:44:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=CYnC6BozqNS9kQzohFpD9gynL6SBYnPtH7aXfwSd6ps=; b=2KfUD0c1iE5I4k 7EET6Tgg7oRP5gQzpn/KOPoHaCoESMh3S6Pe4hMXc5Bhx6J1t9Y7fwXnV0ovE9p4F0G4ofhpuwIGO Ta5kxRr6r2oeTWf747v53txfaBBz/f+7Wy4x6CIQf8nCAjW7qMVY/Yjm0hvKihWoJSZlIrM/on2xZ LQw3rEeTe3IDzYCLofdQSgvXW3QaHN47wNRmoridyiH/v8Yddi3vW3kZLQIItZ14Zl94Cr/M5sHMe czi7KA9V1VeUqsfz9vYdREXQIUNwJiHz2vfpqMfw8VnFw4LWT0M7dX9bwEXSMjrprtWDvublSzw5B qEmg5OSjnVqp1yIFcv/w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7t-00000002Csk-4A0U; Thu, 18 Apr 2024 12:44:30 +0000 Received: from mail-lj1-x236.google.com ([2a00:1450:4864:20::236]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7U-00000002CTw-3dCZ for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:09 +0000 Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2dba429a246so195251fa.2 for ; Thu, 18 Apr 2024 05:44:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444241; x=1714049041; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=av0fCRvJ5d6BdL5At0wE/CNS0oRVP43ZLfrJceTJ89w=; b=Zm/JSt7AgCHSSwNhV9Zj6Y/sT3SPBttcqaDCdqOSggbMRlRiRiVeOsSA2hiLenxMUq p1arziri8oOeO6KbENI1a8Be0aFjDkVt1MlVmYH3ex4qJxh3AM+/rBMZd/Dikk0jCyaW FKdRgZUuWdFgv+xZqF1vTJbQ75mdQ5GNkHO7GSlaJZ2S2wznM7LBWm9HoBl0M9oWTOut 5FaP3SbtUSPoTMdu2jn7j7PR40tECV5DruoZz+k84xpprfm3E8UUaUGS5dLEcR38a+bI cFQ3yTW2/2ViptWdvoJZXPDOp7QHH9MBTe1s56o4ngwx/z8c+wUpqBferIuU3ejGKErn DKpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444241; x=1714049041; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=av0fCRvJ5d6BdL5At0wE/CNS0oRVP43ZLfrJceTJ89w=; b=QHcfwfYclK6ycU+bmlMY1FlfdqkgcZSv30lvWmpKds5/MKsGoYzdDX/H9sC20lQrmp JjHwWbyVyJ8NdLF3EOukmVLZ8VulIw3o7gVAY4G/X015Z9Il6MTnlatA1e4QJH05uL5A 8yD0fOS5ZOPtlN2Xo1h0DE4u6R9qe8ASq18LDS65ridtdTZbRqw5Q+2ZHX6WaglTNGyo LUSxupkACdeOJkC/YMXnOcZjUr3FN4hWDIxLhdYzFjp1TuvX39AtN+ttZNeulSvMSwif 5KzQ43lh28rvx3Z0FcK3mqLYGtsUhvhIxL4s6xbJutXupyY7pkrmK8T+JrMXEcPxE9mN hkmw== X-Forwarded-Encrypted: i=1; AJvYcCUGWrc7UFuSGMf2ZhFW90Q370oBgJqi/jJvYNetNcdflRDlCgM3A0IlLWY8wyJnSjvodLhRX0du55QUuRa2VKiMj8n5Kp7SVSsaBUVHxoft X-Gm-Message-State: AOJu0Yxkoa8dluFLbIJFkZejHm462AkCZo5YVFaHPjBXcHpeMUql9ksW xLiWPowOzEeJTNrr3m1apKAas2/TLgcs0V9+W/CKHXpwQ3GJNzLMesL/x0EpOk4= X-Google-Smtp-Source: AGHT+IHdzMsUCMCexL1xcSXK55gyqNVYHzfsqQON0oQtcwPFlYxqOUNzTjfk86rgRUdr+Vw8mFv+bw== X-Received: by 2002:a2e:3a19:0:b0:2da:320a:6739 with SMTP id h25-20020a2e3a19000000b002da320a6739mr1487240lja.1.1713444241121; Thu, 18 Apr 2024 05:44:01 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.43.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:00 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 06/12] RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM Date: Thu, 18 Apr 2024 14:42:29 +0200 Message-ID: <20240418124300.1387978-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054405_008655_A565FFFF X-CRM114-Status: UNSURE ( 9.51 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 4 ++++ arch/riscv/kvm/vcpu_onereg.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 35a12aa1953e..57db3fea679f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -168,6 +168,10 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZTSO, KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_ZIMOP, + KVM_RISCV_ISA_EXT_ZCA, + KVM_RISCV_ISA_EXT_ZCB, + KVM_RISCV_ISA_EXT_ZCD, + KVM_RISCV_ISA_EXT_ZCF, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 12436f6f0d20..a2747a6dbdb6 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -48,6 +48,10 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -128,6 +132,10 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBKC: case KVM_RISCV_ISA_EXT_ZBKX: case KVM_RISCV_ISA_EXT_ZBS: + case KVM_RISCV_ISA_EXT_ZCA: + case KVM_RISCV_ISA_EXT_ZCB: + case KVM_RISCV_ISA_EXT_ZCD: + case KVM_RISCV_ISA_EXT_ZCF: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN: From patchwork Thu Apr 18 12:42:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4132CC4345F for ; Thu, 18 Apr 2024 12:44:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FcydCKnI95qi4XTlWt3FCotUVu5EhO9XHhvsYfwA1yc=; b=JbIQY8d33oMhqY j5nxHF2g1d9zI18GkFQbNZcvrayDuUHYUv2Z4tfvozTAoPFHLBi7h81B9SQlHxiGPdMU8OwKxV0cU ilMdme/s2xc5YzwVJDpwJUvKR634cT0AMkY60tH9jMrH+7EsnuN3+/+i73ixqtMUBHJ/cKbw7Mezv o30CKeljdBI1n6HPCE9fUrR1UwfC3rkUGUwOeup6NN9BbALL9eRkSCunCdtnKvU13yKIRd+VfdSqe KPRz7PdNQcx2858E2phLbdsSy5uQLec4Y87vAdNrFWrEakhu/VWQ3UWKVZWOCiPPotltA6+WJZTXj c5hXU3hrbSkJ19yb29dg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR87-00000002D5e-3kc0; Thu, 18 Apr 2024 12:44:43 +0000 Received: from mail-lf1-f52.google.com ([209.85.167.52]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7W-00000002CVC-0F9Y for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:10 +0000 Received: by mail-lf1-f52.google.com with SMTP id 2adb3069b0e04-51a70f6b3e3so42489e87.0 for ; Thu, 18 Apr 2024 05:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444242; x=1714049042; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Bj6qFEBTQkW22oNb4zguAXGn3Gn0KYF9aSmL0IcZwU=; b=PKMkWbhNlkp0Is1dF3CbmcQA0W40WBvo6Ne9t71v6C4PIKrIMM0PJ6X2g+UFggUu2M XJe4IDIzXkxKMlnpWTyJ+uyXWRH5H9EorEtsqTFoPWsQ/1tQZaAK8nCfiull6DI5FdGO Gpa2OArKQu66hUdtsNvwP6srfLaHgr29bT2AKPMei15PqkkXM3hKxu1RGMhXfqgZnGrz 4sBVMaSZNtvlBCx9yXFplHeCBb9wWFPCJyOyUdlpCE90u/O8KQ49sFe6AQCPbzFhYdNH Wjhv1GRyS2KtzEOYZVN5SwDtgInns864Wix1npMEyZ/wVmbU1KZa2/7J/udc8PMomXIo /a6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444242; x=1714049042; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Bj6qFEBTQkW22oNb4zguAXGn3Gn0KYF9aSmL0IcZwU=; b=rbZQUrd3FsK7o/TC/Pwq4DloXgiYDJNmyQNcCZBuY1AVaYYoywKbdY3YcEW5Z25aRJ M49gtxDE/tOjPoKhVu4higQk2C9FQecLvW5LI1E6YEeuFmEzDvtr7wdTvBxGse3Wypkj NPNzWwJ4pYk4QHY9gVetsD8o4KqBFAVC7sqVV7btSzmYYzX/tZbxwU3ZhFBboBZYn99Y CJFSKWNzhaiM5CxoVQ9RWXYp9+9AkRgQuE0qYF59abGoyCVz2Vg8ZtAkkGfj6/Wq9FGs H9I1vtecmbsVDeL5/R145NLGU/n9RFIFuZloaBLfjQyLoQKCbztEhjeQ7R1u3r9LMWf5 8aRg== X-Forwarded-Encrypted: i=1; AJvYcCU0TV0bniLhOo9+Uu0mVp5rUAt/mcbilgl8BQxcpGTtGUo4+7ZlixrHryt64qBFweuzGxfOrvZvVlXk1d3fGmTqu9sWhEHTmC3Mv/r7i3Y0 X-Gm-Message-State: AOJu0YyozNAa7pRcbeM3B5mfLPd1rX5rFUiozQAUuvLVjSLHavUVoypE bGqT6LR7vQYorHEppNcG/RvB+sonnAlXgDc4RGsMGQGVOFi6WMw1ZRQ7rKBQZFs= X-Google-Smtp-Source: AGHT+IGuPTx5xyQ5D84Wxe16Njbe8/Zc2rt6PLP6jz46BTrSDooOvgKGDoT7RA33/hfmMjVJRZ9Clg== X-Received: by 2002:a2e:7314:0:b0:2da:590:db77 with SMTP id o20-20020a2e7314000000b002da0590db77mr1413729ljc.0.1713444242557; Thu, 18 Apr 2024 05:44:02 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:01 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 07/12] KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test Date: Thu, 18 Apr 2024 14:42:30 +0200 Message-ID: <20240418124300.1387978-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054406_275732_3C1B2933 X-CRM114-Status: UNSURE ( 8.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The KVM RISC-V allows Zca, Zcf, Zcd and Zcb extensions for Guest/VM so add these extensions to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 40107bb61975..61cad4514197 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -55,6 +55,10 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -421,6 +425,10 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZBKC), KVM_ISA_EXT_ARR(ZBKX), KVM_ISA_EXT_ARR(ZBS), + KVM_ISA_EXT_ARR(ZCA), + KVM_ISA_EXT_ARR(ZCB), + KVM_ISA_EXT_ARR(ZCD), + KVM_ISA_EXT_ARR(ZCF), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -945,6 +953,10 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB); KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC); KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX); KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS); +KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), +KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), +KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), +KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1001,6 +1013,10 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zbkc, &config_zbkx, &config_zbs, + &config_zca, + &config_zcb, + &config_zcd, + &config_zcf, &config_zfa, &config_zfh, &config_zfhmin, From patchwork Thu Apr 18 12:42:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 33826C04FF8 for ; Thu, 18 Apr 2024 12:44:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=BT1zlojInJR2QP/R9iUOOba0248vWxSap/EzyMZ72gs=; b=a688GA0t2CBozz RvEefDNdgNKmD+hnalNmo0sAXibx1DHBMiehd73toeHh6768VNusE6NXFyxqCq01aqv+bnvNae0UV 6CnUahE/0PLePkdXU5PnK0rSzBnkd20PKZQ9Y1ZHjz7LjbZ/P92M3sizkIN12NMSoM060tp+GA9KU 9ZAq6pWvoRWmpR9lYLm0quJ4ADV4i1iU813ZQJWXvgU3kbSPBci57+fBn/U4Sw4pPcUfGbk0uEouc s5m+dEa2Xw+g0R0cfvw7hTWqlbNMVPEgAG+JefBq1Ueu3JOvV7EzNUg9NB/P3LJw3qiSKofWl+Bmw NSXLipZ8aOkOCnTYjBSA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR84-00000002D25-0pb5; Thu, 18 Apr 2024 12:44:40 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Z-00000002CZq-2GYR for linux-riscv@bombadil.infradead.org; Thu, 18 Apr 2024 12:44:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=HCF5E0lf403bRxRvK1+a63xMUHlXis3iiu/dcBPgPms=; b=R9oCcBzlQWdo9DlQuX9YkWNXLk nyUVexFO1rJ2OFuJXQu5Lok6BskpTWUsYSK75Dbpv/DN2BN87GbKxUH+VBMyDEOc+z2c7NMcu9Niw 5M45tu5/W3lG53haRje8BHDizxL77UNWU/aVA08Ct8ch4NQiQ1Oai/EaOqv0dgo58uoQcFC+jQdOz emNNtA3qh6ILtU6pKb3+JEFqvYCDPSH8XhdtjJyGb+yaCsg3U1pcuW+VnETZ3ydVcdp9AeGbhjKET HF65TgS/XQFaiSwF2E3Lc+Nr2Oe+h/2g+ayJIcecfzIhiK4E4asUBtsfJJdMa59nOPDeviAWpE0M7 lLg+bE1w==; Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7W-0000000Bzr6-02Px for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:08 +0000 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-349a31b2babso94929f8f.2 for ; Thu, 18 Apr 2024 05:44:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444244; x=1714049044; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HCF5E0lf403bRxRvK1+a63xMUHlXis3iiu/dcBPgPms=; b=i/C8DTe4A0WfdA3YiEhzRBmi3Y8kSKNNmY/CVY/oyHJSvOluMFklyGgfDVqUkXuLsN jIpcbvRW3kjKzg6UmYo6zWDciT8oHUYWoLVtBxP47WIOCFPUMvHNIFYPHFDx3NEZEDpc FgHUF+J7/dyhr3fVO2NS5JRZrEOqPDDFQazbKi6/mY1CrevrfkqJK7+r5OyjjdL/aXvO l0Y0l105syP98OKE7sPd8Ku5kRuDqgZHqrJGz0z4wjEfbRvPrZEQYvrA1miSzhhiETRi ECsOzXqwykC/eiSGzhrIrUQQSC/h0E6HUbdNy5NeUJ1KCchQkng/bBLzgJu4ZVOWl5wR odtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444244; x=1714049044; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HCF5E0lf403bRxRvK1+a63xMUHlXis3iiu/dcBPgPms=; b=drjDVoo9EDb+ucjM7JQDdWkvFRb6hVnbhDAwnnXWvdFmzkrNwZ8mjxGEJ1l7GVsFjp 5vxLmKKD69mZVR87PnioM5NYkYrv1TAwJ9rfGT6BMwBl0HH97fRreNo1CPA4VQtJKAsd V5mMiOMa1/3YSZME1KV8h0rMCVfNLACsqfsUxhoLzi1KrglihYxbXnvlcJgCAiYo5zcb zd2pZyvoNLWODKJIP0euA+iSBqLH8C49d/+2EzbKJ9MdUngDZmYsNleUs70AgX8hGcNP zCFIvdrGeskvfNzyXoDxRIVbg2eixo/qhCY1L+B5WIqC92MH38feGXLZyu8X8/+w3azG KX3g== X-Forwarded-Encrypted: i=1; AJvYcCXJhfKfU8lB2CCnLxtF0eoNr23sF877XE5rKqH+iNuRu1QGMyOoLIbcZBWAyPjm2K8rV5bU5Levm/xnURSTBVL6pHjeXaToCC8PLC+YFs7P X-Gm-Message-State: AOJu0Yxt9/ndK0yrinV/u6XBqa8N4qW5qr3zJx8ROGoRGYr1/pxwVBlk JBPGBSjZ0pZ2tmPvhkQ8OVcm2r7woZMYNSAnU097RF9vR6vIAa3dV3UKAQzjhTI= X-Google-Smtp-Source: AGHT+IHf5iuv0LIJwrYLLs/M29+a7bnqtqrULSppwC9XA+JzBmE6As/f1Ah2mDNqzxt/R7Bqm6p1VA== X-Received: by 2002:a5d:5046:0:b0:349:eb59:c185 with SMTP id h6-20020a5d5046000000b00349eb59c185mr1524481wrt.1.1713444244182; Thu, 18 Apr 2024 05:44:04 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:03 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 08/12] dt-bindings: riscv: add Zcmop ISA extension description Date: Thu, 18 Apr 2024 14:42:31 +0200 Message-ID: <20240418124300.1387978-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_134406_256388_C87E9B79 X-CRM114-Status: UNSURE ( 8.99 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add description for the Zcmop (Compressed May-Be-Operations) ISA extension which was ratified in commit c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 0172cbaa13ca..a0113cb46893 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -252,6 +252,11 @@ properties: merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed of zc.adoc to src tree."). + - const: zcmop + description: + The standard Zcmop extension version 1.0, as ratified in commit + c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual. + - const: zfa description: The standard Zfa extension for additional floating point @@ -566,6 +571,13 @@ properties: then: contains: const: zcd + # Zcmop depends on Zca + - if: + contains: + const: zcmop + then: + contains: + const: zca allOf: # Zcf extension does not exists on rv64 From patchwork Thu Apr 18 12:42:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56971C4345F for ; Thu, 18 Apr 2024 12:44:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ht8J48sFZwUwjp6RKdfF0/O6LTbBO+RU1M1DTddgh7M=; b=IZGcuphoxPyGIK uvG6krpuEJtwZlTH7oZ2FxLMR1a0arOs36FbkS0Ax7Gu3PQdONoWX/p9/pworgdgIDZzO6ENgihCe /R7Y3rQ4I0+gCbUzZoE1UlzcxDcCGOUW9zGkUP1Iz+c74N68/bHuX8C2mfDtEbSR+MGW7eW1bnzBq zY8xtpIUMDaSW+F4BPkAkHTavY78Q5w227MxI2KU95RK8lJBDPrtpdhJ406ltEapAB9Lv4vctGHVu XFseY3UjIpRTPAKA+w4OB/wcl3JZd9t65pKsto6sNx1JLtncpIkTPPPAJdcbjXRf59IKxQUrdVYc2 FXATUV4B/kHhv2HGt6Lw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR8D-00000002DA6-19xL; Thu, 18 Apr 2024 12:44:49 +0000 Received: from mail-lj1-f177.google.com ([209.85.208.177]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Y-00000002CXX-1Jxl for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:11 +0000 Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-2dac628f08fso2491291fa.3 for ; Thu, 18 Apr 2024 05:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444245; x=1714049045; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AJJluMz+u6UTg8XM641LtNTBq3D7zPplm+46K1BBT3g=; b=h3AajMf0R3IqZsLbddCI39mu5GWOuomWIRGSyiZqRHQx5OEqUn9fGhOAgNuMpkD2o/ k1bzvqb2K4auDpvfTB0ltonfSuEx0pHHKhbnyGrqx+GX3k6CNC9FkT4VNt5Ei6vJNXte H9hZeg4zgphQ1T7GfABYu6BrdFZO9lH9UBHcHtWDFCmW7L0QPYlzOvzNAU4D/4Zte2cc FIzoA7TspDGbdpcyvzBrNX6amzh6dXymInqAKbrPofOc8q84B+l3TTilGw7WFYK5nblM iNfkSssMgzJPIkhywkcenlDcS/0UTEObT3KAJYQVn00AAXuuRL/mHYgMZ8SDVDQi85ye ugKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444245; x=1714049045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJJluMz+u6UTg8XM641LtNTBq3D7zPplm+46K1BBT3g=; b=Q/6883TcxG4KWvOEI5U5x5GJj4j0Q36rpxQLWTsZJ2c+caFqQ2YYw+4yCNchpygW+r ePESlevo0RoDRmQ3PchknDeTAYldCHV3+UUrDkEdRTXaHBoFAaYvjuBtDjWv63otG7bI 4I46LbV1d5esr9jMo1V9xB0Rq1XsGCiUINctCJSYNntkG594I5pqpjf+gQRwKjOH029r j492nQ2oLzG4M1XDuAJ5gPY+5g/ijDOcaUpqLPMB20BL0L+QsAo1yLJJXmFL7OVgS7Ue +329/qmCsNsPfDoLp0ssIMGLbfxdPYoFhJxfwvS/RXJZTS4/tZGprKZ2Cw2f2rmwGzNm sHmg== X-Forwarded-Encrypted: i=1; AJvYcCWcIzehDGA57UU9E+pv+TQ2yM6O1L0rf1Rfj9S+DxBC8l/HnBHFSMb9kbO69ckE/jn5uuO4mBnAsKklz3cB9uA/aRvpU0AXT421vF1R4UXb X-Gm-Message-State: AOJu0YylsxlGah1RJzPnh6IP4kYJYbPFwHx3DdXNjg12nODqgZ/Mkm2M aMdxDjtFAog+/XWKj308Ix0AB7ory2sNr/5MUJj5+hMpU9pecyxlhb5/y5ilsNo= X-Google-Smtp-Source: AGHT+IEA98F7NhkSpgbqjXTJDAARemLQxPRyTCHu7WNOEPKgiNpZ7WkvoQPUAaqjKtkLyPbtJUVEhQ== X-Received: by 2002:a2e:9ccf:0:b0:2d9:e54d:8208 with SMTP id g15-20020a2e9ccf000000b002d9e54d8208mr1639216ljj.0.1713444245128; Thu, 18 Apr 2024 05:44:05 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:04 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 09/12] riscv: add ISA extension parsing for Zcmop Date: Thu, 18 Apr 2024 14:42:32 +0200 Message-ID: <20240418124300.1387978-10-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054408_509416_105C5312 X-CRM114-Status: UNSURE ( 9.54 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add parsing for Zcmop ISA extension which was ratified in commit b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7551bad341b..cff7660de268 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -86,6 +86,7 @@ #define RISCV_ISA_EXT_ZCB 77 #define RISCV_ISA_EXT_ZCD 78 #define RISCV_ISA_EXT_ZCF 79 +#define RISCV_ISA_EXT_ZCMOP 80 #define RISCV_ISA_EXT_XLINUXENVCFG 127 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 09dee071274d..f1450cd7231e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -265,6 +265,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zcb, RISCV_ISA_EXT_ZCB), __RISCV_ISA_EXT_DATA(zcd, RISCV_ISA_EXT_ZCD), __RISCV_ISA_EXT_DATA(zcf, RISCV_ISA_EXT_ZCF), + __RISCV_ISA_EXT_DATA(zcmop, RISCV_ISA_EXT_ZCMOP), __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), From patchwork Thu Apr 18 12:42:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24D4DC4345F for ; Thu, 18 Apr 2024 12:45:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7hyTpju/nnUS/DmiEf83/G7pnb9Fb55NyKWDhsatQPg=; b=ldfFck4dasffAa YSsQaMjylJ+/r6lletuO5i46xBM6AGpG1FF5Z6B8JyjW9p5fyM/oZ8RGgboNMJ46++sXBxFwWqsPi h+n/VOnpYyzv/8fYII2VHa+gzUPkwDC7pKH9pNwym7cM/DFRFtKntRoGESrTEZzLqKwby5rg1c9VQ pIdwAnUKgVTQRv0pdLLVLX2mj4jn5q/+k0/UoLUG9RCjRkUeyeyOuNgc6R/CWEfRT9vKBO4VeUEgX qjsOYxy/YejE9y8gYItESvdbIiDzOX7eNvCdnAvWF4j+DV8hBdwrwjKd8zKMwsjOFlWW5vVUUyhNk s3o16AIBvDdLkwY86FVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR8Y-00000002DQr-2Xzl; Thu, 18 Apr 2024 12:45:10 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7e-00000002CeG-1GNc for linux-riscv@bombadil.infradead.org; Thu, 18 Apr 2024 12:44:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Content-Transfer-Encoding:Content-Type :MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Sender:Reply-To:Content-ID:Content-Description; bh=rdCfPjm06PN8DLWdVlWU7iGB8QhHqS8f5T3HQCXkkpY=; b=NwHav7QhXtBOFGkNkCAtRRWIYw 2QjUTlwasgcmMyMHrpSg7wvOJGKo0rTm4F/M/TP/YY74Eb7/VRtLeKGrV2VZITQarBi2wqEVdoYNa OWMp+R8vAgLJLc+YdeV5gINHTJV76rGReBGmVX8l8GJPnkRlaOr7hckITV2jItidKltt8X4r1XCfT fH+/8gwGYRN6CQ26rmtCFlr5kDqyHq0RDy1Md8PotGtykQeKhhoD7lOslypA/Tc2TuVfWgrpgJjtL K6i3Y3uJBBd+MnAGAGE0AVXlHj5fU4LTg6Q84mkP9wXiS0/swoKQWTfHH2A22y/mmPhzw1O9HlzY4 mLxijDaw==; Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by desiato.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7Y-0000000Bzrd-1Sz1 for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:12 +0000 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-347c6d6fc02so116320f8f.1 for ; Thu, 18 Apr 2024 05:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444246; x=1714049046; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rdCfPjm06PN8DLWdVlWU7iGB8QhHqS8f5T3HQCXkkpY=; b=XUjeQCkwJVsSV6+XotCLWQw0aqwJplmmbSvvbOt59vu3bstz+/Nriet7B0i6c9P/BC e7xfzvorIeFtMlaRfK6uNJUZJMeAuyzuWOIP5DCzGT3pJzE4oLtD4ryzAzW14pZ8ssnf LVdSYARwF7sdWalyVm5tcv/W7XG6uD9VMeOXz/QhevdameuS5PmtA2WIW+TIvMNTjTce Pxgq+jbrs8iVh4Ufcu9w1B4J3jjlmEUlJI2AfKLzYmfKNN0mvE1CSwVG/+DWourjRaW0 JyQwUov+aY3b8PQY4kreA2gGFEo9ouWbcj5IpBKLhL8yHp/JeZszeLK1Y49QDemhVTaH PKVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444246; x=1714049046; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rdCfPjm06PN8DLWdVlWU7iGB8QhHqS8f5T3HQCXkkpY=; b=cvmbtY4SOd2Lk6d/03LqFqxDXyA+rlNbdKznN1C4x/vNySzGA+Ou7l7n913yZE1mys LzyCM99B+jgxz9sLoJ5F9yPVY53gHHoy1EIdmv3GANmd2lxkRvGduNrxPhJ/LuI68POX 2bExRrm19g8CpLutguaI929GecqhrWpPrWh7nvhB9C10ZNBhkSuCnadFBDAhQLoGjiJs eUZSlsPkzA07Cv1Nib/W/1MbxTpw+AJqjf6Ef5ZrRMZOsFMh7WM2QgR0zNo3pB6jwkRc Bdf5nIN/MZ0mQYXKpEQSLDNa5Fv3CvuOiA0b6mpD7epOeftiJuEEhVJXz018eHF0r40G ZtgQ== X-Forwarded-Encrypted: i=1; AJvYcCUr86ATF0qJQyunS+Rxe+UTQ0KjEuhrX0FQNyDTPdS9Ad8Vgsm06FjjgNBMDEe1TxQ0NfLt4cnXop0ioRRujebobTBX8pz0UM56qcC1wGsQ X-Gm-Message-State: AOJu0YyfDiRLBSXvB9+IXX5ID5G6OO5iElvziKJ6UO6mFHj/o2rm93tr 1X1voyFkp1lBwKt0toIilitDE4Go24zjOy4i3EYShSC+AB4VwlZa1B5h6TOOZRw= X-Google-Smtp-Source: AGHT+IGMuL1VEcAVu36oqMeDfSFjQ3yk2Wj7i500rFn3wK2To4nptMyU7omA9B2isyVdkpsEUDxcgg== X-Received: by 2002:a05:600c:1ca2:b0:418:2a57:3806 with SMTP id k34-20020a05600c1ca200b004182a573806mr1932349wms.0.1713444246501; Thu, 18 Apr 2024 05:44:06 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:05 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 10/12] riscv: hwprobe: export Zcmop ISA extension Date: Thu, 18 Apr 2024 14:42:33 +0200 Message-ID: <20240418124300.1387978-11-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_134408_688542_4BDEB9C5 X-CRM114-Status: GOOD ( 11.08 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Export Zcmop ISA extension through hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index bf96b4e8ba3b..e3187659a077 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -212,6 +212,10 @@ The following keys are defined: ("Zcf doesn't exist on RV64 as it contains no instructions") of riscv-code-size-reduction. + * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is + supported as defined in the RISC-V ISA manual starting from commit + c732a4f39a4 ("Zcmop is ratified/1.0"). + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index dd4ad77faf49..d97ac5436447 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -64,6 +64,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZCB (1ULL << 38) #define RISCV_HWPROBE_EXT_ZCD (1ULL << 39) #define RISCV_HWPROBE_EXT_ZCF (1ULL << 40) +#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 41) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 2ffa0fe5101e..9457231bd1c0 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -114,6 +114,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIMOP); EXT_KEY(ZCA); EXT_KEY(ZCB); + EXT_KEY(ZCMOP); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Thu Apr 18 12:42:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7877CC04FF8 for ; Thu, 18 Apr 2024 12:45:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=3ApSonKAdmsKTO9mbK6/SL3NFT1od6dakSsUE/EgpSA=; b=h82L9aoMYQiiqj H0sTF+E2YQZQRF/rTFGi3g+UpWYGrQHxagcwgvKWHviro/vUYi/OxI5VPTyozDwVVKID+T7IIanY4 uBMKNSHD87XSCBY1+jskyonDJuOrIS/XhMZxNQFe3NVXEekckKYw4GU/x9Nm3bQUGJDgqwxx5Z1ir AawcUKsx6fOztwcgikTMLu8bniSSI3W34j/lWOcz3kg0zjgjTYEfNptWmRdmXbvR/cPTLHOqaY91l iR0eDzjBfhKPxp5dYSxYKCKUrsBgnFzUJZZgV2MZQ9AFZby7abec7CyEE7DQlHD3oD4u3RcYfAEPr v/ghHoj5F2LBkNyHrK2w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR8c-00000002DTO-0QC4; Thu, 18 Apr 2024 12:45:14 +0000 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7a-00000002CZo-3vQ8 for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:13 +0000 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-347c6d6fc02so116325f8f.1 for ; Thu, 18 Apr 2024 05:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444248; x=1714049048; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FohdVePPG5jzF3AfSRVe1tr20y+8LhH20P3MwlhF1eo=; b=FhN64NhQERRODOWG2fwEhqXJetf9KBT6bsBRzs+LVdJXlXClziGjuGs4iDf1iUp3tq xgjJUObfOYh1q2Nz3atKb3inix0q4Vb8nIVyY6UGAvXMdk59lvn5b1itAu3MdXOxOfYH U3t5fbpaGxrS0MtKkOkcoliKwqymyoRpxJmxeyZk8UPLI+wOZRAHTccGFQ+RxiPHxoFL yXHP5lYCVtmtUKZFcoVRe7K+9PaMK6DLs1TJMeeh494d31TPUtQr/YabGMJ0mippYv9L sDHK1DRZvlEON7CjSnuPWCrCi9MHXBolsWA86oRBsIM5Vb3LCwkz5ir3W3/bYyvVrEzn 7ZlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444248; x=1714049048; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FohdVePPG5jzF3AfSRVe1tr20y+8LhH20P3MwlhF1eo=; b=m/tPvLRH8R5KjvERYMEckX8jpL5d1jdiUSawV6QyNW9h1UtxmfAi/3Nr3MQESVtm80 CU6Bub3yFtsj9DdiyXd7jrR5v/klWQCbY0mALL/94Mj1VP+bTRzwFpKerVm9CUU8cJ7W Qa7eMOjCGJV1Zl3QY0AIcCsUBmfNMKXeq83eDoQKdUSvMAxo17oyBO5ptX8oQHXMf4oS l0WDcilQc1oCxhl29FTz1mf3tEOB8pK6FwUdnFr3m3/4T23CFB7N1RkjaeYiz4d9YFLE 7lseYyMHB1+jzsfKDSN6xXWi/bTVuHw+KXrRb1jTerlNEKPd+sjczNTRQz25wBR1lngE C/BA== X-Forwarded-Encrypted: i=1; AJvYcCWYpHckAOteOEd8HoC1w4dvWRYmW4Xz5XnoOtP3Zz/UMV8WCUoxP6rHfKYKMPNS4mv7YbZODQmOzdLVJ2wR8l8eVrYYcQ9T8hG6qZUJHV1z X-Gm-Message-State: AOJu0YxyFnz5uF91gcD6kcCf3PIVXE/FUoP4wda8pPb3J/jL5JmdcTpW n3qaqf3T9CjRpUGkfZW0UIE5CVAwrSns7IlGg4JXxiVPwuBBSE6PkfpGA3mTBZ4= X-Google-Smtp-Source: AGHT+IF2De8slGmiEH7R+Sd8JWMFq3iRx3g2xhyGy7kAAvUUYk8LgiIFDjRM+gQKByYDrF2dau+9Wg== X-Received: by 2002:adf:f984:0:b0:343:f2e0:449c with SMTP id f4-20020adff984000000b00343f2e0449cmr1668881wrr.0.1713444248202; Thu, 18 Apr 2024 05:44:08 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:07 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 11/12] RISC-V: KVM: Allow Zcmop extension for Guest/VM Date: Thu, 18 Apr 2024 14:42:34 +0200 Message-ID: <20240418124300.1387978-12-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054411_395196_8871BD98 X-CRM114-Status: UNSURE ( 9.35 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 57db3fea679f..0366389a0bae 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -172,6 +172,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCB, KVM_RISCV_ISA_EXT_ZCD, KVM_RISCV_ISA_EXT_ZCF, + KVM_RISCV_ISA_EXT_ZCMOP, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index a2747a6dbdb6..77a0d337faeb 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -52,6 +52,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -136,6 +137,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZCB: case KVM_RISCV_ISA_EXT_ZCD: case KVM_RISCV_ISA_EXT_ZCF: + case KVM_RISCV_ISA_EXT_ZCMOP: case KVM_RISCV_ISA_EXT_ZFA: case KVM_RISCV_ISA_EXT_ZFH: case KVM_RISCV_ISA_EXT_ZFHMIN: From patchwork Thu Apr 18 12:42:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 13634682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C01FC4345F for ; Thu, 18 Apr 2024 12:45:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qSEbjcsdMk7wjlnOXhArkT3nv6XunSGXnHSgkJ9Bu0o=; b=wqtkWCGe76WeCQ JtXXXdrYxAormveKC+bpeyfJa4ldqyMCq0opLHf5qDEh0SfSGfqczRHJ0X+UdcOloCh+6hD5Gwhd6 qA+tyQC/lkg8SJ/BmoX4m5s4WUECkq7YWGlKYpG5LrNJ+2uMywXGUfJeZD452y1+N1k3yDJfSX9cj Z3q6xG/Lc9xP02HBLKKYk03+eZaF7JAJvRs5Szrcp1Uvfzi4SkDT0sqdy81o+AA4Z9C1Q+pUVs7Q5 LeSBcQYG/LyasHPpTVA8JoL65nFNNNGSuAnoLoJ5fUuL24quuifezBGnY2m94DXpGHiKf+OH/A/Jr QivoV13tY12nA6pD2sgg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR8V-00000002DNu-1L79; Thu, 18 Apr 2024 12:45:08 +0000 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxR7a-00000002Caq-3wFm for linux-riscv@lists.infradead.org; Thu, 18 Apr 2024 12:44:13 +0000 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-349a31b2babso94944f8f.2 for ; Thu, 18 Apr 2024 05:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713444249; x=1714049049; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OKIlCd7jL5ol5qvLgWGPfJLjgIu96MFC3958FRvJI8w=; b=pNC+lqG3JmePw6erqOzK6elephyHAYFEBBPYROdqPiRkUZzCwudIldHUXxbhKwmPca gQ6Z3A6H5fT9WjSV5cWp2BErND322j+4F9wFXvnx/3SZ8w/l8BdmbtuENhh7vHV0tHcf Zxd+I6+zJnHxiUGENdLABNSU5NPAzCMjwb3qb/SeVav9wiMNH2lLeyVv/xW5ddfYimDR mGjx4EkKIP3vtw1uHWzU4aqE0AK/IBXthYo/fKx6Do0wcv6uSKetKw7l7ZDUR97uGpX1 rPJn2z+ZLW8WjOqS6XARZ54QSH8L7KYAmfEii6Yfa49VRScVlGjkZtUOvURwMGJrFOLD sbAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713444249; x=1714049049; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OKIlCd7jL5ol5qvLgWGPfJLjgIu96MFC3958FRvJI8w=; b=EjmNBhej5zXd6Og53hH3N+XkQCCKIbwnik2ERJTqr70m/Iz9a0lzCfcH3hXkPL3pMI 0pPqM4x+JQLbIu8wmv0u1U2fUZsWyvncPY5F+eBqXdBhRf5+ZTonF9Zh1OqEI6XzZGjP PdkkcqzO4JjIIyMZ4Gl1DOGcatV7VMxT4Yu5BK4b1G68y2iFabGsC8YzQfXRLYB5+Nmy feMCMQQjaKJGCqUiF6KfrC3B20i5P4jSXu1cY6LovtCUJMHiNIXc9qBmk01zmVjsB57j 4R3VQUueuEk3t4NHwVb4W878uJDtFQsp6SKCdksxRIVZQfkhpccolATCx2zr/M5/3hM3 eaNA== X-Forwarded-Encrypted: i=1; AJvYcCVtd7Fo8FC2+eaPO60XRpzpFaUyoAgG2WKdL5PumXVEHyHRdelZvVmWozLQ+HFiMOYneE/OAMAkkzB4f256KDev4rkiM1gVVqjGgLvUm2// X-Gm-Message-State: AOJu0YwMDnaB5aTiVi12sVDG5FbpMOVILPma0rdmCLDNzB9K63+Y2SFT nsreobNaY65kVrs7P5xKd36j6ADT7mjUyTtxoCj6TFKoimLxZPkAI3Nt4yROsVc= X-Google-Smtp-Source: AGHT+IEuz3T/wADyuU6lhNByO66nc3HwRSSRfc4RI/wUE1r6vwDm0YQy96IvGIrIEPLWf2aV5baVXg== X-Received: by 2002:a05:600c:47cf:b0:418:f991:70ff with SMTP id l15-20020a05600c47cf00b00418f99170ffmr135350wmo.1.1713444249424; Thu, 18 Apr 2024 05:44:09 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:7b64:4d1d:16d8:e38b]) by smtp.gmail.com with ESMTPSA id bi18-20020a05600c3d9200b00418d5b16fa2sm3373412wmb.30.2024.04.18.05.44.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Apr 2024 05:44:08 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Anup Patel , Shuah Khan Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Subject: [PATCH v2 12/12] KVM: riscv: selftests: Add Zcmop extension to get-reg-list test Date: Thu, 18 Apr 2024 14:42:35 +0200 Message-ID: <20240418124300.1387978-13-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240418124300.1387978-1-cleger@rivosinc.com> References: <20240418124300.1387978-1-cleger@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_054411_464529_28615DDE X-CRM114-Status: UNSURE ( 9.24 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org The KVM RISC-V allows Zcmop extension for Guest/VM so add this extension to get-reg-list test. Signed-off-by: Clément Léger Reviewed-by: Anup Patel Acked-by: Anup Patel --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 61cad4514197..9604c8ece787 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -59,6 +59,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN: @@ -429,6 +430,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(ZCB), KVM_ISA_EXT_ARR(ZCD), KVM_ISA_EXT_ARR(ZCF), + KVM_ISA_EXT_ARR(ZCMOP), KVM_ISA_EXT_ARR(ZFA), KVM_ISA_EXT_ARR(ZFH), KVM_ISA_EXT_ARR(ZFHMIN), @@ -957,6 +959,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA), KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB), KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD), KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF), +KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP); KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA); KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH); KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN); @@ -1017,6 +1020,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_zcb, &config_zcd, &config_zcf, + &config_zcmop, &config_zfa, &config_zfh, &config_zfhmin,